Memory cell and integrated circuit

Abstract

The embodiment of the utility model provides a memory unit cell and an integrated circuit, and particularly relates to a multi-time programmable (MTP) memory unit cell which comprises two or more bits. In one embodiment, the memory cell includes a fin field effect transistor (FinFET) transistor having two or more storage nodes formed around a channel region, and two or more gate electrodes formed over the two or more storage nodes. The memory unit cell can be realized by an n-type channel transistor or a p-type channel transistor.

Description

Technical Field

[0001] Some embodiments of the present disclosure provide memory cells and integrated circuits. Background Art

[0002] Many modern electronic devices contain electronic memory for storing data. Electronic memory can be volatile memory or non-volatile memory (NVM). Volatile memory stores data when power is on, while NVM can retain data when power is off. Multi-time programmable (MTP) cells are a promising candidate for the next generation of NVM. NVM is sometimes embedded in integrated circuits and is referred to as eNVM. Conventional eNVM uses a floating poly gate as a charge storage node. However, thin oxide and metal gate processes during technology scaling have become bottlenecks for eNVM. Embodiments of the present disclosure provide a new NVM cell suitable for use as an eNVM. Utility Model Content

[0003] Some embodiments of the present disclosure provide a memory cell comprising: a source region, a drain region, a channel region, a first gate dielectric layer, a storage gate electrode layer, a first control gate electrode layer, and a second control gate electrode layer. The channel region connects the source region and the drain region, wherein the channel region has a first sidewall, a second sidewall, and a top surface connecting the first sidewall and the second sidewall. The first gate dielectric layer is disposed on the channel region. The storage gate electrode layer is disposed on the first gate dielectric layer. The first control gate electrode layer is disposed on the storage gate electrode layer, wherein the first control gate electrode layer faces the first sidewall of the channel region. The second control gate electrode layer is disposed on the storage gate electrode layer, wherein the second control gate electrode layer faces the second sidewall of the channel region, and the first control gate electrode layer and the second control gate electrode layer are electrically isolated from each other.

[0004] Some embodiments of the present disclosure provide a memory cell comprising: a source region, a drain region, a channel region, a storage gate electrode layer, a first control gate electrode layer, and a second control gate electrode layer. The channel region connects the source region and the drain region, wherein the channel region has a first sidewall, a second sidewall, and a top surface connecting the first sidewall and the second sidewall. The storage gate electrode layer is disposed on the channel region. The first control gate electrode layer is disposed on the storage gate electrode layer, wherein the first control gate electrode layer faces the first sidewall of the channel region. The second control gate electrode layer is disposed on the storage gate electrode layer, wherein the second control gate electrode layer faces the second sidewall of the channel region, and the first control gate electrode layer and the second control gate electrode layer are electrically isolated from each other. The storage gate electrode layer comprises a first portion, a second portion, and a top portion. The first portion is disposed between the first control gate electrode layer and the first sidewall of the channel region. The second portion is disposed between the second control gate electrode layer and the second sidewall of the channel region. The top portion is disposed above the top surface of the channel region, wherein the top portion connects the first portion and the second portion.

[0005] Some embodiments of the present disclosure provide an integrated circuit comprising an array, a first word line, a second word line, a first bit line, and a second bit line. The array comprises a plurality of memory cells, wherein each memory cell comprises: a source region, a drain region, a channel region, a first storage node, a second storage node, a first control gate electrode layer, and a second control gate electrode layer. The channel region is connected between the source region and the drain region, wherein the channel region has a first sidewall, a second sidewall, and a top surface connecting the first sidewall and the second sidewall. The first storage node is formed on the first sidewall of the channel region. The second storage node is formed on the second sidewall of the channel region. The first control gate electrode layer is disposed on the first storage node. The second control gate electrode layer is disposed on the second storage node. The first word line is connected to the first control gate electrode layers of the memory cells in the first row of the array; the second word line is connected to the second control gate electrode layers of the memory cells in the first row of the array. The first bit line is connected to the drain regions of the memory cells in the first column of the array. The second bit line is connected to the source regions of the memory cells in the first row of the array. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure are best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figures 1A to 1E Various views illustrating a two-bit memory cell according to an embodiment of the present disclosure;

[0008] Figure 2A An embodiment of the present disclosure has an n-type channel region. Figures 1A to 1C Block diagram of a two-bit memory cell;

[0009] Figure 2B With programmed bits and erased bits Figure 2A Schematic cross-section of a two-bit memory cell;

[0010] Figure 2C For reading Figure 2B Schematic circuit during operation of the first bit of the two-bit memory cell shown in ;

[0011] Figure 2D For reading Figure 2B Schematic circuit during operation of the second bit of the two-bit memory cell shown in ;

[0012] Figure 2E To show Figure 2B Table of the reading results of the two-bit memory cell under various storage conditions;

[0013] Figure 3A The embodiment of the present disclosure has a P-type channel region. Figures 1A to 1C Block diagram of a two-bit memory cell;

[0014] Figure 3B With programmed bits and erased bits Figure 3A Schematic cross-section of a two-bit memory cell;

[0015] Figure 3C For reading Figure 3B Schematic circuit during operation of the first bit of the two-bit memory cell shown in ;

[0016] Figure 3D For reading Figure 3B Schematic circuit during operation of the second bit of the two-bit memory cell shown in ;

[0017] Figure 3E To show Figure 3B Table of the reading results of the two-bit memory cell under various storage conditions;

[0018] Figures 4A to 4B Description and Figures 1A to 1C Table corresponding to the operating conditions of the memory cell;

[0019] Figure 5A is a layout diagram of a memory circuit according to an embodiment of the present disclosure;

[0020] Figures 5B to 5C for Figure 5A A schematic partial cross-sectional view of a memory cell in a memory circuit;

[0021] Figure 6 is a layout diagram of a memory circuit according to an embodiment of the present disclosure;

[0022] Figure 7 is a flow chart of a method for forming a memory cell according to an embodiment of the present disclosure;

[0023] Figures 8 to 10 、 Figures 10A to 10C 、 Figure 11 、 Figures 11A to 11C 、 Figure 12 、 12A to 12C as well as 13A to 13C Various views illustrating the formation of a memory cell according to an embodiment of the present disclosure;

[0024] Figure 14 is a flow chart of a method for forming a memory cell according to an embodiment of the present disclosure;

[0025] Figure 15 、 Figures 15A to 15C 、 Figure 16 、 16A to 16C as well as 17A to 17C Various views illustrating the formation of a memory cell according to an embodiment of the present disclosure.

[0026]

Explanation of symbols

[0027] 100, 202, 2521, 252 n 450, 450a: memory cell

[0028] 100N, 100P: Transistor / memory cell

[0029] 101: Centerline

[0030] 102: semiconductor substrate

[0031] 104: Channel area / Fin channel area

[0032] 104sa: Side wall / first side wall

[0033] 104sb: Second side wall

[0034] 104t: Top surface

[0035] 106: Isolation Area

[0036] 108d, 260: drain region

[0037] 108s, 258: source region

[0038] 110: Gate structure

[0039] 112: Gate electrode layer / first gate electrode layer

[0040] 112a: Part 1

[0041] 112b: Part 2

[0042] 114, 424, 424a: gate dielectric layer / first gate dielectric layer

[0043] 116: Gate electrode layer / second gate electrode layer

[0044] 116a: second gate electrode layer / first part

[0045] 116b: second gate electrode layer / second portion

[0046] 118, 430: second gate dielectric layer

[0047] 120: third gate dielectric layer

[0048] 122: sidewall spacer

[0049] 124a, 124b, 436: Gate contact features

[0050] 126a, 126b: control lines

[0051] 128d: Drain contact features

[0052] 128s: Source contact characteristics

[0053] 130a: Storage node / first storage node

[0054] 130b: Storage node / second storage node

[0055] 132a, 132b, 134a, 134b: current

[0056] 200, 400, 400a: memory circuits

[0057] 250: Multi-bit multi-time programmable cell / multi-bit MTP cell

[0058] 2541, 254 n , 2561, 256 n :Control Gate

[0059] 300, 500: Method

[0060] 302, 304, 306, 308, 310, 506, 508: Operation

[0061] 402:Substrate

[0062] 404:Semiconductor fins

[0063] 406: Isolation layer

[0064] 408: Sacrificial gate dielectric layer

[0065] 410: Sacrificial gate electrode layer

[0066] 412: Gate sidewall spacer / sidewall spacer

[0067] 414, 414a: Replacement gate structure

[0068] 416: Sacrificial gate structure

[0069] 418: Source / drain region

[0070] 420: Contact Etch Stop Layer / CESL

[0071] 422: Interlayer dielectric layer / ILD layer

[0072] 426, 426a: gate electrode layer

[0073] 428, 428', 428a, 428b: storage nodes

[0074] 432, 432a: storage gate electrode layer

[0075] 434: Central axis

[0076] 437:Contact Line

[0077] 438: Contact through hole

[0078] 440: Source / drain contact features

[0079] 442, BL_m, BL_m+1, BL_m+2: bit lines 446, WLA_n, WLA_n+1, WLA_n+2, WLB_n, ​​WLB_n+2: word lines AA, BB, CC: lines

[0080] D:Thickness / Distance

[0081] HV: High Voltage

[0082] -HV: Negative high voltage

[0083] T:Thickness

[0084] Vdd: voltage / positive voltage

[0085] Vdd1, Vdd2: voltage / positive voltage

[0086] -Vdd: voltage / negative voltage

[0087] Vdd3: voltage / positive voltage

[0088] Vdd4: positive voltage / negative voltage DETAILED DESCRIPTION

[0089] The following disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first and second features are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first and second features so that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or configurations discussed.

[0090] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0091] Embodiments of the present disclosure provide an MTP memory cell comprising a fin field effect transistor (FinFET) forming one or more storage bits. In some embodiments, the MTP memory cell comprises a source region, a drain region, a channel region connecting the source region and the drain region, two storage nodes formed above the channel region, and two control gates formed above the two storage nodes, respectively. In some embodiments, the storage gate comprises a silicon nitride gate electrode. The control gate comprises a metal-containing gate electrode. The channel region is a fin-shaped region having a first sidewall, a second sidewall, and a top surface connecting the first and second sidewalls. Storage nodes are formed above the first and second sidewalls, respectively. A control gate is formed above the storage gate. In some embodiments, the two storage nodes may comprise a storage electrode layer formed continuously above the first sidewall, top surface, and second sidewall of the fin-shaped region. In a process for manufacturing complementary metal-oxide semiconductor (CMOS) transistors, a cut metal gate sequence may be used to form the storage nodes and control gates. The MTP memory cell according to the present disclosure may be formed by a P-type FinFET or an N-type FinFET.

[0092] The configuration of the storage gate and the metal control gate enables high-density memory cell configuration and high-efficiency programming and erasure. Electrons can be selectively captured in the storage nodes of the MTP memory cell, so that the MTP memory cell can be selectively set in a programmed state or an erased state. For example, in the programmed state, electrons are captured in the storage gate, resulting in a low read current. In the erased state, electrons are cleared from the storage gate, resulting in a high read current. The MTP cell can be programmed or erased by applying a suitable control voltage to the control gate. The MTP cell can be programmed and / or erased via Fowler-Nordheim (FN) tunneling, channel hot electron injection (CHE) or band-to-band hot hole injection (BBHH). The storage nodes on the opposite sides of the fin channel region can be read independently using the corresponding control gate, these storage nodes are charged and these storage nodes are erased.

[0093] Figures 1A to 1C Various views are illustrated of a two-bit memory cell 100 according to the present disclosure. Figure 1C FIG. 1 is a schematic top view of a two-bit memory cell 100 . Figure 1A For a two-bit memory cell 100 along Figure 1C Schematic cross-sectional view of line AA in FIG. Figure 8 For a two-bit memory cell 100 along Figure 1C Schematic cross-sectional view of line BB in FIG. Figures 1A to 1C As shown in FIG, a two-bit memory cell 100 is a FinFET transistor formed on a semiconductor substrate 102. The two-bit memory cell 100 may include a fin-shaped channel region 104. The fin-shaped channel region 104 may be formed by the semiconductor substrate 102 and surrounded by an isolation region 106. The two-bit memory cell 100 includes a gate structure 110 (including a gate structure 110a and a gate structure 110b) extending in a direction substantially perpendicular to the fin-shaped channel region 104. The gate structure 110 is formed above the fin-shaped channel region 104 and the isolation region 106. The source region 108s and the drain region 108d are disposed on opposite sides of the gate structure 110. The source region 108s and the drain region 108d may be epitaxially grown from the fin-shaped channel region 104.

[0094] In the gate structure 110 , the fin channel region 104 includes a first sidewall 104sa, a second sidewall 104sb, and a top surface 104t connecting the first sidewall 104sa and the second sidewall 104sb. The first sidewall 104sa and the second sidewall 104sb face opposite sides of the fin channel region 104.

[0095] The gate structure 110 may include a first gate dielectric layer 114, a second gate dielectric layer 118, a third gate dielectric layer 120, a first gate electrode layer 112, and a second gate electrode layer 116 disposed between two sidewall spacers 122. The sidewall spacers 122 separate the source region 108s and the drain region 108d from the gate dielectric layers 114, 118, 120 and the gate electrode layers 112, 116. The first gate dielectric layer 114 is disposed over the fin-shaped channel region 104 and a portion of the sidewall spacers 122.

[0096] The first gate electrode layer 112 is disposed above the first gate dielectric layer 114 and surrounds the fin channel region 104 between the sidewall spacers 122. In some embodiments, the first gate electrode layer 112 may be substantially symmetrically disposed around the center line 101 of the fin channel region 104. Figure 1A As shown in FIG, the first gate electrode layer 112 is disposed on the sidewalls 104s of the fin-shaped channel region 104. In some embodiments, the first gate electrode layer 112 may extend from both sides of the fin-shaped channel region 104 to a distance D. Figure 1A As shown in FIG, the first gate electrode layer 112 includes a first portion 112a disposed above the first sidewall 104sa of the fin channel region 104 and a second portion 112b disposed above the second sidewall 104sb of the fin channel region 104. In some embodiments, the first portion 112a and the second portion 112b have substantially the same thickness D. The first portion 112a and the second portion 112b are connected above the top surface 104t of the fin channel region 104.

[0097] The second gate electrode layer 116 is disposed outside the first gate electrode layer 112. In some embodiments, two portions of the second gate electrode layers 116a and 116b are disposed on the first portion 112a and the second portion 112b of the first gate electrode layer 112, respectively. A second gate dielectric layer 118 is disposed between the first gate electrode layer 112 and the second gate electrode layer 116. A third gate dielectric layer 120 is disposed between the second gate electrode layer 116 and the sidewall spacers 122, and between the second gate electrode layer 116 and the isolation region 106.

[0098] Figure 1D and Figure 1E 1 is a simplified cross-sectional view and a top view of a two-bit memory cell 100 to illustrate the two-bit structure. Figure 1D and Figure 1EAs shown in FIG, a first portion 112a of the gate electrode layer 112 and the first gate dielectric layer 114 form a first storage node 130a, while a second portion 112b of the gate electrode layer 112 and the first gate dielectric layer 114 form a second storage node 130b. In some embodiments, the first storage node 130a and the second storage node 130b each serve as a memory device for forming one bit of the two-bit memory cell 100. The second electrode layer 116 adjacent to the storage node 130a or 130b can serve as a control gate to program and erase the storage node 130a or the storage node 130b. Charge carriers (such as electrons) can be independently stored in or erased from the storage nodes 130a and 130b by applying appropriate voltages over the first portion 116a and the second portion 116b of the second electrode layer 116.

[0099] By connecting the first portion 116a and the second portion 116b of the second electrode layer 116 via interconnects, an appropriate control gate voltage can be applied to the storage nodes 130a and 130b to program and erase the two-bit memory cell 100. The efficiency of the programming and erasing operations can be improved by selecting an appropriate control gate voltage. Furthermore, the distance D between the second gate electrode layer 116 and the channel region 104 can be selected to achieve a desired cell coupling ratio. For example, reducing the distance D can improve the efficiency of the programming / erase operations. In some embodiments, the distance D is within a range from approximately 5 nanometers to approximately 100 nanometers. A distance D greater than 100 nanometers may not enable efficient programming and erasing operations. A distance D less than 5 nanometers may not provide a storage volume in the storage nodes 130a and 130b to capture electrons sufficient to cause a detectable difference between the programmed state and the erased state.

[0100] Different voltage combinations can be applied to the first and second portions 116a, 116b of the second gate electrode layer 116, the source region 108s, and the drain region 108d to program (charge), erase, and read the charge in the storage nodes 130a, 130b. Gate contact features 124a, 124b are formed to contact the first and second portions 116a, 116b of the second gate electrode layer 116. In some embodiments, the gate contact features 124a, 124b are electrically connected to control lines 126a, 126b, respectively. A control voltage can be applied to the first and second portions 116a, 116b of the second gate electrode layer 116 via the control lines 126a, 126b, respectively. Source contact features 128s and drain contact features 128d are in contact with the source and drain regions 108s, 108d, respectively. A voltage may be applied to the source region 108s and the drain region 108d via the source contact feature 128s and the drain contact feature 128d, respectively.

[0101] The semiconductor substrate 102 may be or include a bulk semiconductor substrate (eg, a bulk silicon substrate), a silicon-on-insulator (SOI) substrate, or another suitable substrate material. In some embodiments, the semiconductor substrate 102 may include one or more doped regions.

[0102] The fin channel region 104 may be formed in a discrete doped region or well region in the semiconductor substrate 102. The fin channel region 104 may include p-type dopants or n-type dopants, resulting in the two-bit memory cell 100 being a p-type FinFET or an n-type FinFET.

[0103] The source region 108s and the drain region 108d may include one or more layers of Si, SiP, SiC, and SiCP for n-type devices, or Si, SiGe, or Ge for p-type devices. For n-type devices, the source region 108s and the drain region 108d also include n-type dopants such as phosphorus (P) and arsenic (As). For p-type devices, the source region 108s and the drain region 108d may include p-type dopants such as boron (B).

[0104] The first gate electrode layer 112 may be formed of silicon nitride, silicon oxynitride, an alloy of silicon oxide and silicon nitride, a combination thereof, or any other suitable material for storing charges therein.

[0105] The first gate electrode layer 116 may be one or more layers of a conductive material such as aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, a metal alloy, other suitable materials, and / or combinations thereof. In some embodiments, the first gate electrode layer 116 may include tungsten, aluminum, titanium nitride, tantalum nitride, or combinations thereof.

[0106] The first gate dielectric layer 114, the second gate dielectric layer 118, and the third gate dielectric layer 120 may include one or more layers of a dielectric material such as silicon oxide, silicon nitride, or a high-k dielectric material, other suitable dielectric materials, and / or combinations thereof. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, a hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloy, other suitable high-k dielectric materials, and / or combinations thereof. In some embodiments, the first gate dielectric layer 114, the second gate dielectric layer 118, and the third gate dielectric layer 120 may include SiOx, HfOx, and ZrOx, or combinations thereof. Depending on the circuit design, the first gate dielectric layer 114, the second gate dielectric layer 118, and the third gate dielectric layer 120 may have the same or different compositions and / or thicknesses.

[0107] Figure 2A illustrate Figures 1A to 1C FIG. 1 is a block diagram of a circuit of a two-bit memory cell 100 . Figure 2B A program bit and an erase bit Figure 2A Schematic cross-sectional view of a two-bit memory cell 100. Figure 2C For reading Figure 2B Schematic circuit during operation of the first bit of the two-bit memory cell 100 shown in FIG. Figure 2D For reading Figure 2B Schematic circuit during operation of the second bit of the two-bit memory cell 100 shown in FIG. Figure 2E To show Figure 2B Table showing the readout results of the two-bit memory cell under various storage conditions.

[0108] like Figure 2A As shown in FIG, source region 108s, drain region 108d, channel region 104, and gate structure 110 form an n-type field-effect transistor 100N, in which the majority of charge carriers are electrons. In this case, transistor 100N is an N-type FinFET. In some embodiments, transistor 100N is an N-channel enhancement-mode metal-oxide-semiconductor field-effect transistor (MOSFET). When transistor 100N is turned on, that is, when a sufficient positive voltage Vdd is applied to drain region 108d and a sufficient positive voltage, such as Vdd, is applied to first portion 116a and / or second portion 116b of second gate electrode layer 116, electron current flows through channel region 104. In some embodiments, voltage Vdd indicates the positive power supply voltage of the MOSFET circuit. Depending on the circuit design, voltage Vdd can be approximately 5V, approximately 3.3V, approximately 1.8V, approximately 1.2V, or any suitable value. In some embodiments, the first portion 116 a and / or the second portion 116 b of the second gate electrode layer 116 are independently controlled by signals from control lines 126 a and 126 b , respectively.

[0109] Figure 2B The transistor 100N of the two-bit memory cell 100 is shown, wherein the storage node 130a is in a programmed state and the storage node 130b is in an initial state or erased state.

[0110] For the storage node 130a, a portion of carrier electrons near the first sidewall 104sa of the fin-shaped channel region 104 are trapped in the first portion 112a of the gate electrode layer 112. Figure 2CAs shown in FIG, when a voltage is applied only through the first portion 116a of the second electrode layer 116 to turn on the transistor 100N, a current 132a flows along the first sidewall 104sa and the first storage node 130a through the channel region 104. Because the first storage node 130a is in a programmed state that reduces carrier electrons along the first sidewall 104sa of the channel region 104, the current 132a is in a low current state.

[0111] For the storage node 130b, electrons are not trapped or pushed out from the second portion 112b of the gate electrode layer 112. Figure 2D As shown in FIG, when a voltage is applied only through the second portion 116b of the second electrode layer 116 to turn on the transistor 100N, a current 132b flows along the second sidewall 104sb through the channel region 104. Because the second storage node 130b is in an initial or erased state, which does not reduce the carrier electrons along the second sidewall 104sb of the channel region 104, the current 132b is a normal or high current.

[0112] During a read operation, the two-bit value in the two-bit memory cell 100 is obtained by currents 132a, 132b by applying appropriate voltages to the first and second portions 116a, 116b of the second electrode layer 116. A high current 132a, 132b passing through the channel region 104 indicates that the storage nodes 130a, 130b of the two-bit memory cell 100 are in an erased or initial state, while a low current 132a, 132b passing through the channel region 104 indicates that the storage nodes 130a, 130b of the two-bit memory cell 100 are in a programmed state.

[0113] Figure 2E Listed Figure 2B Combinations of possible charging conditions in the storage node of the two-bit memory cell 100N and the reading results under different reading conditions.

[0114] Alternatively, the source region 108s, the drain region 108d, the channel region 104 and the gate structure 110 may also be P-type transistors and function in a similar manner.

[0115] Figure 3A illustrate Figures 1A to 1C A block diagram of the circuit of a two-bit memory cell 100 is shown. Figure 3A In the embodiment, the source region 108s, the drain region 108d, the channel region 104 and the gate structure 110 form a p-type field effect transistor 100P, in which most of the carriers are electrons. Figure 3B With programmed bits and erased bits Figure 3A Schematic cross-sectional view of a two-bit memory cell 100P. Figure 3C For reading Figure 3BSchematic circuit during operation of the first bit of the two-bit memory cell 100P shown in FIG. Figure 3D For reading Figure 3B Schematic circuit during operation of the second bit of the two-bit memory cell 100P shown in FIG. Figure 3E To show Figure 3B Table showing the readout results of the two-bit memory cell under various storage conditions.

[0116] like Figure 3B As shown in FIG, transistor 100N is a P-type FinFET. In some embodiments, transistor 100P is a P-type channel enhancement mode MOSFET. When transistor 100P is turned on, that is, by applying a sufficiently negative voltage -Vdd to drain region 108d and applying a sufficiently negative voltage, such as -Vdd, to first portion 116a and / or second portion 116b of second gate electrode layer 116, electron current flows through channel region 104. In some embodiments, voltage -Vdd indicates the negative power supply voltage of the MOSFET circuit. Depending on the circuit design, voltage -Vdd can be approximately -5V, approximately -3.3V, approximately -1.8V, approximately -1.2V, or any suitable value. In some embodiments, first portion 116a and / or second portion 116b of second gate electrode layer 116 are independently controlled by signals from control lines 126a and 126b, respectively.

[0117] Figure 3B The transistor 100P of the two-bit memory cell 100 is shown, wherein the storage node 130a is in a programmed state and the storage node 130b is in an initial state or erased state.

[0118] For the storage node 130a, electrons from the first sidewall 104sa of the fin channel region 104 are driven to the first portion 112a of the gate electrode layer 112 and are trapped in the first portion 112a. Therefore, carrier holes are increased along the first sidewall 104sa of the fin channel region 104. Figure 3C As shown in FIG, when a voltage is applied only through the first portion 116a of the second electrode layer 116 to turn on the transistor 100P, a current 134a flows along the first sidewall 104sa and the first storage node 130a through the channel region 104. Because the first storage node 130a is in a programmed state, which results in an increase in carrier holes along the first sidewall 104sa of the channel region 104, the current 134a is in a high current state.

[0119] For the storage node 130b, electrons are not trapped or pushed out from the second portion 112b of the gate electrode layer 112. Therefore, the carrier holes along the second sidewall 104sb of the fin-shaped channel region 104 are not affected. Figure 3DAs shown in FIG, when a voltage is applied only through the second portion 116b of the second electrode layer 116 to turn on the transistor 100P, a current 134b flows along the second sidewall 104sb through the channel region 104. Because the second storage node 130b is in an initial or erased state, this does not increase carrier holes along the second sidewall 104sb of the channel region 104, so the current 132b is a normal or low current.

[0120] During a read operation, the two-bit value in the two-bit memory cell 100 is obtained by currents 134a, 134b by applying appropriate voltages to the first and second portions 116a, 116b of the second electrode layer 116. Low currents 134a, 134b flowing through the channel region 104 indicate that the storage nodes 130a, 130b of the two-bit memory cell 100 are in an erased or initial state, while high currents 134a, 134b flowing through the channel region 104 indicate that the storage nodes 130a, 130b of the two-bit memory cell 100 are in a programmed state.

[0121] Figure 3E Listed Figure 3B Combinations of possible charging conditions in the storage node of the two-bit memory cell 100P and the reading results under different reading conditions.

[0122] As discussed above, the two-bit memory cell 100 is a multiply programmable MTP cell with two states: a programmed state and an erased state. Electrons are stored in storage nodes 130a, 130b in the programmed state and released from storage nodes 130a, 130b in the erased state. The electrons stored in storage nodes 130a, 130b affect the threshold voltage of the two-bit memory cell 100 and the current through the channel region 104. For memory cells with an n-type channel, the programmed state has a low current, while the erased state has a high current. For memory cells with a p-type channel, the programmed state has a high current, while the erased state has a low current.

[0123] By applying appropriate voltages to the source region 108s, the drain region 108d, and the first and second portions 116a, 116b of the second gate electrode layer 116 or the control gate, the storage nodes 130a, 130b of the two-bit memory cell 100 can be programmed and erased. The two-bit memory cell 100 can be programmed via Fowler-Nordheim (FN) tunneling or channel hot electron (CHE) injection. The two-bit memory cell 100 can be erased via Fowler-Nordheim (FN) tunneling or band-to-band hot hole (BBHH) injection.

[0124] Figures 4A to 4B Description and Figures 1A to 1C The table of operating conditions of the memory cell corresponds to: Figure 4A The programming and erasing operations of the first storage node 130a of the two-bit memory cell 100 having an N-type field effect transistor (FET) 100N are described. The second storage node 130b can be programmed and erased in a similar manner.

[0125] To program the storage node 130a of a memory cell having an N-type FET 100N using channel hot electron injection (CHE), a positive voltage Vdd2 is applied to the control gate or first portion 116a of the second gate electrode layer 116, a positive voltage Vdd1 is applied to the drain region 108d, and a voltage of approximately 0 volts (V) is applied to the source region 108s and the second portion 116b of the second gate electrode layer 116. The positive voltages Vdd2 and Vdd1 turn on the FET 100N on the sidewall 104sa, generating an electron current along the sidewall 104sa through the channel region 104. A portion of the electrons in the current may be injected and trapped in the storage node 130a, thereby adjusting the first storage node 130a of the two-bit memory cell 100 to a programmed state. In some embodiments, the positive voltages Vdd1 and Vdd2 are greater than Vdd. The voltages Vdd1 and Vdd2 may be selected based on the circuit design. In some embodiments, voltage Vdd2 is greater than voltage Vdd1 to achieve increased charging speed.

[0126] To program a memory cell having an N-type FET 100N using Fowler-Nordheim (FN) tunneling, a positive high voltage HV is applied to the control gate or first portion 116a of the second gate electrode layer 116, while a voltage of approximately 0V is applied to the second portion 116b of the second gate electrode layer 116, the source region 108s, and the drain region 108d. When the positive high voltage HV is applied to the first portion 116a of the second gate electrode layer 116, electrons along the sidewalls 104sa of the channel region 104 are "drawn in" and trapped in the storage node 130a, thereby adjusting the storage node 130a of the two-bit memory cell 100 to a programmed state. In some embodiments, the high voltage HV may be, for example, in the range of approximately 7V to 10V, approximately 11V to 18V, approximately 7V to 18V, or another suitable value.

[0127] To erase a memory cell having an N-type FET 100N using band-to-band hot hole injection (BBHH), a negative voltage Vdd4 is applied to the control gate or first portion 116a of the second gate electrode layer 116 to attract holes injected into the storage gate. A positive voltage Vdd3 is applied to the drain region 108d and the source region 108s. A voltage of 0V is applied to the second portion 116b of the second gate electrode layer 116. Positive voltage Vdd4 is lower than positive voltage Vdd3. The higher voltage Vdd3 in the source region 108s and the drain region 108d drives hot holes along the sidewalls 104sa of the channel region 104 into the storage node 130, erasing trapped electrons in the storage node 130a and thereby placing the storage node 130a of the two-bit memory cell 100 in an erased state. In some embodiments, positive voltages Vdd3 and Vdd4 are greater than Vdd.

[0128] To erase a memory cell having an N-type FET 100N using Fowler-Nordheim (FN) tunneling, a negative high voltage -HV is applied to the control gate or first portion 116a of the second gate electrode layer 116, while a voltage of approximately 0V is applied to the second portion 116b of the second gate electrode layer 116, the source region 108s, and the drain region 108d. When the negative high voltage -HV is applied to the first portion 116a of the second gate electrode layer 116, electrons trapped in the storage node 130a are driven back into the channel region 104 through the sidewall 104sa, thereby adjusting the storage node 130a of the two-bit memory cell 100 to an erased state. In some embodiments, the negative high voltage -HV may be, for example, in the range of approximately -7V to -10V, in the range of approximately -11V to -18V, in the range of approximately -7V to -18V, or another suitable value.

[0129] Depending on the circuit design, programming and erasing methods can be mixed and combined. Figure 4B 1 is a table showing voltage conditions applied to the control gate or the first and second portions 116a and 116b of the second gate electrode layer 116, the source region 108s, and the drain region for various operations.

[0130] Even though one fin-shaped channel region 104 is shown in the two-bit memory cell 100 , a memory cell according to the present disclosure may include two or more fin-shaped structures to obtain a larger channel region.

[0131] Figure 5A FIG. 2 is a layout diagram of a memory circuit 200 according to an embodiment of the present disclosure. Figures 5B to 5C The memory circuit 200 is respectively along Figure 5A Schematic partial cross-sectional view along lines BB and CC.

[0132] Memory circuit 200 includes multiple rows and columns of memory cells 202. In some embodiments, each memory cell 202 may have a structure similar to a two-bit memory cell 100. In some embodiments, memory cells 202 are formed into an array. Memory circuit 200 includes multiple memory cells 202, multiple bit lines BL_m (m is an integer), multiple source lines SL_m (m is an integer), and multiple word lines WLA_n and WLB_n (n is an integer). Each memory cell 100 (memory cell 202) in memory circuit 200 is connected to word lines WLA_n and WLB_n at two portions 116a and 116b of the second electrode layer 116, such that word lines WLA_n and WLB_n independently control operations on two storage nodes 130a and 130b in memory cell 100. Memory cells 100 (memory cells 202) in the same row share the same word lines WLA_n and WLB_n. Each memory cell 100 (memory cell 202) in the memory circuit 200 is connected to two bit lines BL_m and BL_m+1 at its source region 108s and drain region 108d, respectively. The source regions 108s and drain regions 108d of adjacent memory cells 100 (memory cells 202) in the same row may be combined and share the same bit line BL_m.

[0133] Figure 6 FIG2 is a layout diagram of a multi-bit MTP unit cell 250 according to an embodiment of the present disclosure. In addition to including four or more bits, the multi-bit MTP unit cell 250 can be used to replace the memory unit cell 100. The multi-bit MTP unit cell 250 includes n memory units 2521, ..., 252 formed in a row. n In some embodiments, the memory cells 2521, ..., 252 n The memory cells 2521, ..., 252 may be similar to the two-bit memory cell 100 described above. n Each of the two control gates 2541, . . . , 254 may be a FinFET transistor having two storage nodes and two control gates 2541, . . . , 254 formed above the storage nodes. n and 2561, ..., 256 n Memory cells 2521, ..., 252 can be manufactured using one or more identical semiconductor fins. n Memory cells 2521, ..., 252 n A pair of source region 258 and drain region 260 are shared. The number n is equal to or greater than 2.

[0134] During operation, the control gates 2541, ..., 254 n and 2561, ..., 256 nThe source region 258 and the drain region 260 are connected to two bit lines. n 、2561、……、256 n Appropriate voltages are applied to the source region 258 and the drain region 260 to read, charge, and erase each bit in the multi-bit MTP cell 250 .

[0135] In some embodiments, the multi-bit MTP unit cell 250 may include two memory cells 252 and 252 disposed between the source region 258 and the first memory cell 2521 and the nth memory cell 252. n and a bit line transistor between the drain region 260. The bit line may be connected to the drain of the bit line transistor.

[0136] Multiple multi-bit MTP cells 250 can be arranged in an array in a memory circuit. The configuration of the multi-bit MTP cells 250 allows minimization of the two-bit memory cell 100, thereby achieving high cell density.

[0137] Figure 7 is a flow chart of a method 300 for forming a memory circuit according to an embodiment of the present disclosure. Figures 8 to 10 、 Figures 10A to 10C 、 Figure 11 、 Figures 11A to 11C 、 Figure 12 、 12A to 12C as well as 13A to 13C Various views illustrating the formation of a memory circuit 400 according to an embodiment of the present disclosure. The memory circuit 400 may include a plurality of memory cells similar to the two-bit memory cell 100 discussed above.

[0138] In operation 302 of method 300, semiconductor fins 404 are formed on a substrate 402, and an isolation layer 406 is formed in trenches between the semiconductor fins 404, as shown in FIG. Figure 8 As shown in . Figure 8Schematic perspective view of a memory circuit 400 according to the present disclosure. Substrate 402 may include single crystal semiconductor materials such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. Depending on the circuit design, substrate 402 may include various doping configurations. For example, substrate 402 may include one or more p-type doped regions and one or more n-type doped regions. One or more patterning and etching processes are then used to form semiconductor fins 404. Isolation layer 406 is formed in the trenches between semiconductor fins 404 by suitable deposition, followed by an etch-back process. As an example, the bottom profile of isolation layer 406 is shown as curved. Depending on the spacing and / or height of semiconductor fins 404, the bottom profile of isolation layer 406 may vary, such as being curved, substantially flat, or having other shapes. The isolation layer 406 may be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD), or other suitable deposition processes. In some embodiments, the isolation layer 406 may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, or a combination thereof. In some embodiments, the isolation layer 406 is formed by a suitable deposition process to cover the semiconductor fins 404, thereby filling the trenches between the semiconductor fins 404. A planarization process may be performed to expose the semiconductor fins 404, and then a suitable anisotropic etching process may be used to etch a recess to expose a portion of the semiconductor fins 404, such as Figure 8 As shown in .

[0139] In operation 304, a sacrificial gate structure 416 and source / drain regions 418 are formed, such as Figure 9 As shown in . Figure 9 is a schematic perspective view of a memory circuit 400 according to the present disclosure.

[0140] To form the sacrificial gate structure 416, a sacrificial gate dielectric layer 408 is conformally formed over the substrate 402. The sacrificial gate dielectric layer 408 is formed over the semiconductor fins 404 and the isolation layer 406. The sacrificial gate dielectric layer 408 may include silicon oxide, silicon nitride, combinations thereof, or the like. The sacrificial gate dielectric layer 408 may be deposited or thermally grown according to acceptable techniques such as thermal CVD, CVD, ALD, and other suitable methods.

[0141] A sacrificial gate electrode layer 410 is deposited on the sacrificial gate dielectric layer 408 and then planarized, such as by a CMP process. The sacrificial gate electrode layer 410 comprises silicon, such as polycrystalline silicon, amorphous silicon, polycrystalline silicon germanium (poly-SiGe), or the like. In some embodiments, the sacrificial gate electrode layer 410 is subjected to a planarization operation. The sacrificial gate electrode layer 410 can be deposited using CVD (including LPCVD and PECVD), PVD, ALD, or other suitable processes. The sacrificial gate electrode layer 410 and the sacrificial gate dielectric layer 408 are patterned using one or more etching processes, such as one or more plasma etching processes or one or more wet etching processes, to form a sacrificial gate structure 416. In some embodiments, a patterning process is first used to pattern a mask layer and a liner layer (not shown). The patterned mask layer and liner layer are then used as an etch mask to pattern the sacrificial gate electrode layer 410. In some embodiments, the sacrificial gate electrode layer 410 can be etched via anisotropic etching, such as a reactive ion etching (RIE) process. Anisotropic etching has a higher etching rate along the Z direction than along the X and Y directions. During etching of the sacrificial gate electrode layer 410, the sacrificial gate dielectric layer 408 on the semiconductor fin 404 can act as an etch stop to prevent the etchant from removing the semiconductor fin 404. In some embodiments, after patterning the sacrificial gate electrode layer 410, any exposed residual sacrificial gate dielectric layer 408 is removed via a suitable etching process. In some embodiments, the residual sacrificial gate dielectric layer 408 can be etched by adjusting one or more parameters of the etching process used to etch the sacrificial gate electrode layer 410, such as the etchant, etching temperature, etching solution concentration, etching pressure, power supply, radio frequency (RF) bias, and etchant flow rate.

[0142] The sacrificial gate structure 416 covers a portion of the semiconductor fin 404. The portion of the semiconductor fin 404 covered by the sacrificial gate structure 416 ultimately forms a channel region. Gate sidewall spacers 412 are formed on the sidewalls of the sacrificial gate structure 416. The gate sidewall spacers 412 may include one or more dielectric layers.

[0143] The semiconductor fin 404 not covered by the sacrificial gate structure 416 is recessed and etched to form source / drain recesses on both sides of the sacrificial gate structure 416. Epitaxial source / drain regions 418 are formed in the source / drain recesses. In some embodiments, the epitaxial source / drain regions 418 can be grown in an epitaxial chamber using a suitable process.

[0144] A contact etch stop layer (CESL) 420 and an interlayer dielectric (ILD) layer 422 are formed above the memory circuit 400. Figure 10 、 Figure 10A 、 Figure 10B and Figure 10C As shown in . Figure 10 is a schematic perspective view of a memory circuit 400 according to the present disclosure.

[0145] Figure 10A 、 Figure 10B and Figure 10C The memory circuit 400 is respectively Figure 10 Schematic cross-sectional view along lines AA, BB and CC.

[0146] CESL 420 is conformally formed over the exposed surface of memory circuit 400. Upon exposure of epitaxial source / drain regions 418, gate sidewall spacers 412, and isolation layer 406, CESL 420 is formed over epitaxial source / drain regions 418, gate sidewall spacers 412, and isolation layer 406. CESL 420 may comprise SiN, SiON, SiCN, or any other suitable material and may be formed via CVD, PVD, or ALD. An interlayer dielectric (ILD) layer 422 is formed over CESL 420. Materials for ILD layer 422 include compounds containing Si, O, C, and / or H, such as silicon oxide, SiCOH, and SiOC. Organic materials, such as polymers, may be used for ILD layer 422. In some embodiments, ILD layer 422 may be formed via flowable CVD (FCV). The ILD layer 422 protects the epitaxial source / drain regions 418 during the removal of the sacrificial gate structure 416 .

[0147] In operation 306, as Figure 11 、 Figure 11A 、 Figure 11B and Figure 11C As shown in , a replacement gate structure 414 is formed. Figure 11 is a schematic perspective view of a memory circuit 400 according to the present disclosure. Figure 11A 、 Figure 11B and Figure 11C The memory circuit 400 is respectively along Figure 11 Schematic cross-sectional view along lines AA, BB and CC.

[0148] The sacrificial gate dielectric layer 408 and the sacrificial gate electrode layer 410 are removed by one or more suitable processes such as dry etching, wet etching, or a combination thereof to expose the semiconductor fin 404. In some embodiments, a wet etchant such as tetramethylammonium hydroxide (TMAH) solution is used. The replacement gate structure may include a first gate dielectric layer 424 and a gate electrode layer 426.

[0149] The first gate dielectric layer 424 can be conformally deposited on the exposed surface in the gate cavity. The first gate dielectric layer 424 can have different compositions and dimensions for N-type and P-type devices and can be formed separately using patterned mask layers and different deposition recipes. The first gate dielectric layer 424 can include one or more layers of dielectric material such as silicon oxide, silicon nitride, or a high-k dielectric material, other suitable dielectric materials, and / or combinations thereof. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, a hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloy, other suitable high-k dielectric materials, and / or combinations thereof. The first gate dielectric layer 424 can be formed via CVD, ALD, or any suitable method.

[0150] A gate electrode layer 426 is then formed on the first gate dielectric layer 424 to fill the gate cavity. The gate electrode layer 426 may include one or more layers of a conductive material such as aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, a metal alloy, other suitable materials, and / or combinations thereof. In some embodiments, the gate electrode layer 426 may be formed by CVD, ALD, electroplating, or other suitable methods. After forming the gate electrode layer 426, a planarization process, such as a CMP process, is performed to remove excess gate electrode material and expose the top surface of the ILD layer 422.

[0151] In operation 308, as Figure 12 、 Figure 12A 、 Figure 12B 、 Figure 12C As shown in FIG, storage nodes 428 a, 428 b (collectively referred to as 428 ) are formed over the semiconductor fin 404 between the sidewall spacers 412 . Figure 12 is a schematic perspective view of a memory circuit 400 according to the present disclosure. Figure 12A 、 Figure 12B and Figure 12C The memory circuit 400 is respectively Figure 12 Schematic cross-sectional view along lines AA, BB and CC.

[0152] Storage nodes 428a and 428b are formed within the replacement gate structure 414 and above the semiconductor fin 404. A patterning process may be performed to "cut" the replacement gate structure 414 into multiple portions by removing the gate electrode layer 426 and the first gate dielectric layer 424 above the semiconductor fin 404. After the cutting process, the semiconductor fin 404 is exposed between the sidewall spacers 412. A second gate dielectric layer 430 is then deposited over the exposed surface including the semiconductor fin 404, the isolation layer 406, the sidewall spacers 412, the first gate dielectric layer 424, and the gate electrode layer 426. A storage gate electrode layer 432 is then deposited over the second gate dielectric layer 430 and fills the opening above the semiconductor fin 404. The storage gate electrode layer 432 and the second gate dielectric layer 430 form the storage node 428.

[0153] In some embodiments, the second gate dielectric layer 430 may include one or more layers of a dielectric material such as silicon oxide, silicon nitride, or a high-k dielectric material, other suitable dielectric materials, and / or combinations thereof. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, a hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloy, other suitable high-k dielectric materials, and / or combinations thereof. In some embodiments, the second gate dielectric layer 430 may include SiOx, HfOx, and ZrOx, or combinations thereof. The second gate dielectric layer 430 may be selected and formed by CVD, ALD, or any other suitable method. The composition and dimensions of the second gate dielectric layer 430 may be selected based on the circuit design.

[0154] In some embodiments, the storage gate electrode layer 432 may include one or more layers of materials suitable for trapping electrons therein. In some embodiments, the storage gate electrode layer 432 may be formed of silicon nitride, silicon oxynitride, an alloy of silicon oxide and silicon nitride, combinations thereof, or any other suitable material for storing charge therein. The storage gate electrode layer 432 may be formed via CVD, ALD, or any other suitable method. After depositing the storage gate electrode layer 432, a planarization process, such as CMP, may be performed to expose the gate electrode layer 426 for subsequent formation of gate contact features.

[0155] In some embodiments, the storage nodes 428 may be formed substantially symmetrically about the central axis 434 of the corresponding semiconductor fin 404. Figure 12AAs shown in FIG, the storage gate electrode layer 432 may have a substantially equal thickness T on either side of the semiconductor fin 404. The thickness T may be in a range of about 5 nanometers to about 100 nanometers. In some embodiments, the second gate dielectric layer 430 may have a thickness in a range of about 2 nanometers to about 10 nanometers. In some embodiments, the thickness ratio of the second gate dielectric layer 430 to the storage gate electrode layer 432 may be in a range of about 0.01 to about 0.2.

[0156] like Figure 12A As shown in FIG, the second gate dielectric layer 430 is disposed between the gate electrode layer 426 and the storage gate electrode layer 432. In some embodiments, the first gate dielectric layer 424 and the second gate dielectric layer 430 may be formed of the same material. In other embodiments, the first gate dielectric layer 424 and the second gate dielectric layer 430 may be formed of different materials depending on the circuit design.

[0157] After operation 308, a plurality of memory cells 450 are formed over the substrate 402. The memory cells 450 are similar to Figures 1A to 1C Two-bit memory cell 100.

[0158] In operation 310, gate contact features 436 and / or source / drain contact features 440 may be formed to connect to the memory cell 450, such as Figure 13A 、 Figure 13B 、 Figure 13C As shown in . Figure 13A 、 Figure 13B and Figure 13C The memory circuit 400 is respectively along Figure 12 Schematic cross-sectional view along lines AA, BB and CC.

[0159] In operation 310, conductive lines and vias are formed in the dielectric material in the layer to provide electrical connections to the source / drain regions 418 and the gate electrode layer 426, enabling reading, programming, and erasing of the memory cell 450. In some embodiments, gate contact features 436 are formed to connect the gate electrode layer 426 to word lines 446 via contact lines 437 and contact vias 438. Source / drain contact features 440 are formed to connect the source / drain regions 418 to bit lines 442. In some embodiments, bit lines 442 are disposed in the first IMD layer and extend along the y-axis, while word lines 446 are disposed in the second IMD layer and extend along the x-axis. The conductive lines and vias can be arranged in different configurations depending on the circuit design.

[0160] Figure 14 is a flow chart of a method 500 for forming a memory circuit according to an embodiment of the present disclosure. Figure 15 、 Figures 15A to 15C 、 Figure 16 、 16A to 16C as well as 17A to 17C Various views illustrating the formation of a memory circuit 400a according to an embodiment of the present disclosure. The memory circuit 400a may include a plurality of memory cells similar to the two-bit memory cell 100 discussed above. The method 500 begins with operations 302 and 304, as discussed above and as Figures 8 to 10 As shown in .

[0161] In operation 506, a storage node 428' is formed by cutting the sacrificial gate electrode layer 410 over the semiconductor fin 404 and depositing a storage gate electrode layer 432a. Figure 15 、 Figure 15A 、 Figure 15B 、 Figure 15C As shown in . Figure 15 is a schematic perspective view of a memory circuit 400a according to the present disclosure. Figure 15A 、 Figure 15B and Figure 15C The memory circuit 400a is respectively along Figure 15 Schematic cross-sectional view along lines AA, BB and CC.

[0162] A storage node 428' is formed within the sacrificial gate structure 416 and above the semiconductor fin 404. A patterning process may be performed to "cut" the sacrificial gate electrode layer 410 into multiple portions through patterning and etching processes. After the cutting process, the sacrificial gate dielectric layer 408 is exposed between the sidewall spacers 412. A storage gate electrode layer 432a is then deposited over the sacrificial gate dielectric layer 408 and fills the openings between the sidewall spacers 412. The storage gate electrode layer 432a and the sacrificial gate dielectric layer 408 form a storage node 428'. The storage gate electrode layer 432a contacts the sidewall spacers 412 and portions of the sacrificial gate electrode layer 410.

[0163] In some embodiments, the storage gate electrode layer 432a may include one or more layers of materials suitable for trapping electrons therein. In some embodiments, the storage gate electrode layer 432a may be formed of silicon nitride, silicon oxynitride, an alloy of silicon oxide and silicon nitride, a combination thereof, or any other suitable material for storing charge therein. The storage gate electrode layer 432a may be formed via CVD, ALD, or any other suitable method. After depositing the storage gate electrode layer 432a, a planarization process, such as CMP, may be performed to expose the sacrificial gate electrode layer 410 for use in the replacement gate process.

[0164] In operation 508, a replacement gate structure 414a is formed, such as Figure 16 、 Figure 16A 、 Figure 16B and Figure 16C As shown in . Figure 16is a schematic perspective view of a memory circuit 400a according to the present disclosure. Figure 16A 、 Figure 16B and Figure 16C The memory circuit 400a is respectively along Figure 16 Schematic cross-sectional view along lines AA, BB and CC.

[0165] In some embodiments, the sacrificial gate electrode layer 410 is selectively etched to expose the underlying sacrificial gate dielectric layer 408. In some embodiments, the sacrificial gate dielectric layer 408 can be removed by one or more suitable processes such as dry etching, wet etching, or a combination thereof to expose the semiconductor fin 404. A gate cavity is formed between the sidewall spacers 412 and the storage gate electrode layer 432a.

[0166] A gate dielectric layer 424a is then deposited on the exposed surfaces in the gate cavity. Specifically, the gate dielectric layer 424a may be deposited over the sidewalls of the storage gate electrode layer 432a, the sidewall spacers 412, and the isolation layer 406.

[0167] The first gate dielectric layer 424a can have different compositions and dimensions for N-type and P-type devices and can be formed separately using patterned mask layers and different deposition recipes. The gate dielectric layer 424a can include one or more layers of dielectric materials such as silicon oxide, silicon nitride, or high-k dielectric materials, other suitable dielectric materials, and / or combinations thereof. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloys, other suitable high-k dielectric materials, and / or combinations thereof. The gate dielectric layer 424a can be formed by CVD, ALD, or any other suitable method.

[0168] A gate electrode layer 426a is then formed on the gate dielectric layer 424a to fill the gate cavity. The gate electrode layer 426a may include one or more layers of conductive materials such as aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof. In some embodiments, the gate electrode layer 426a may be formed via CVD, ALD, electroplating, or other suitable methods. After forming the gate electrode layer 426a, a planarization process, such as a CMP process, is performed to remove excess gate electrode material and expose the top surface of the ILD layer 422.

[0169] After operation 508, a plurality of memory cells 450a are formed on the substrate 402. The memory cells 450a are similar to Figures 1A to 1C Two-bit memory cell 100.

[0170] Operation 310 is then performed to form gate contact features 436 and / or source / drain contact features 440 to connect the memory cell 450a, such as Figure 17A 、 Figure 17B 、 Figure 17C As shown in . Figure 17A 、 Figure 17B and Figure 17C The memory circuit 400 is respectively Figure 16 Schematic cross-sectional view along lines AA, BB and CC.

[0171] Embodiments of the present disclosure provide an MTP memory cell and a method for forming the same. The MTP memory cell includes a FinFET transistor having two or more storage nodes formed around a channel region and corresponding metal gate electrodes located above the storage nodes. Multi-bit memory cells can be implemented by n-type channel transistors or p-type channel transistors, thereby providing design flexibility. The MTP memory cell includes only a single transistor and can therefore be used to implement high-density memory arrays. The MTP memory cell can be programmed / erased via various methods including CHE, BBHH, and FN adjustments, thereby providing additional design options. In addition, existing processing sequences (such as cutting metal gate sequences) can be used to manufacture MTP memory cells.

[0172] It should be understood that not all advantages are necessarily discussed herein, not all embodiments or examples require a particular advantage, and other embodiments or examples may provide different advantages.

[0173] An embodiment of the present disclosure provides a memory cell, comprising: a source region; a drain region; a channel region connecting the source region and the drain region, wherein the channel region has a first sidewall, a second sidewall, and a top surface connecting the first sidewall and the second sidewall; a first gate dielectric layer disposed on the channel region; a storage gate electrode layer disposed on the first gate dielectric layer; a first control gate electrode layer disposed on the storage gate electrode layer, wherein the first control gate electrode layer faces the first sidewall of the channel region; and a second control gate electrode layer disposed on the storage gate electrode layer, wherein the second control gate electrode layer faces the second sidewall of the channel region, and the first control gate electrode layer and the second control gate electrode layer are electrically isolated from each other.

[0174] In some embodiments, the storage gate electrode layer comprises silicon nitride. In some embodiments, the storage gate electrode layer comprises: a first portion disposed between the first control gate electrode layer and a first sidewall of the channel region; a second portion disposed between the second control gate electrode layer and a second sidewall of the channel region; and a top portion disposed above a top surface of the channel region, wherein the top portion connects the first portion and the second portion. In some embodiments, the memory cell further comprises: a second dielectric layer disposed between the storage gate electrode layer and the first control gate electrode layer. In some embodiments, the first gate dielectric layer and the second dielectric layer comprise different materials. In some embodiments, the first gate dielectric layer extends along the bottom surface of the storage gate electrode layer and is disposed between the storage gate electrode layer and the first control gate electrode layer. In some embodiments, the channel region is a p-type channel. In some embodiments, the channel region is an n-type channel. In some embodiments, the channel region comprises two or more semiconductor fins.

[0175] Some embodiments of the present disclosure relate to a method for operating a memory cell, comprising: providing a multi-programmable memory cell, comprising: a source region; a drain region; a channel region connected between the source region and the drain region, wherein the channel region has a first sidewall, a second sidewall, and a top surface connecting the first sidewall and the second sidewall; a first storage node formed on the first sidewall of the channel region; a second storage node formed on the second sidewall of the channel region; a first control gate electrode layer disposed on the first storage node; and a second control gate electrode layer disposed on the second storage node; and injecting electrons into the first storage node by applying a first control voltage to the first control gate electrode layer while applying a second control voltage to the second control gate electrode layer, wherein the first control voltage is different from the second control voltage.

[0176] In some embodiments, injecting electrons into the first storage node further comprises: applying a source voltage to the source region; and applying a drain voltage to the drain region, wherein the first control voltage is a positive voltage, and the second control voltage, the source voltage, and the drain voltage are approximately 0 volts. In some embodiments, injecting electrons into the first storage node further comprises: applying a source voltage to the source region; and applying a drain voltage to the drain region, wherein the first control voltage is a positive voltage, the second control voltage and the source voltage are approximately 0 volts, and the drain voltage is a positive voltage. In some embodiments, the method further comprises: removing electrons from the first storage node by applying a third control voltage to the first control gate electrode layer while applying a fourth control voltage to the second control gate electrode layer, wherein the third control voltage is different from the fourth control voltage. In some embodiments, removing electrons from the first storage node comprises: applying a source voltage to the source region; and applying a drain voltage to the drain region, wherein the third control voltage is a negative voltage, and the fourth control voltage, the source voltage, and the drain voltage are approximately 0 volts. In some embodiments, removing electrons from the first storage node includes applying a source voltage to the source region and applying a drain voltage to the drain region, wherein the third control voltage is a positive voltage, the source voltage and the drain voltage are multiple positive voltages greater than the third control voltage, and the fourth control voltage is approximately 0 volts.

[0177] Some embodiments of the present disclosure relate to an integrated circuit, comprising: an array, the array comprising a plurality of memory cells, wherein each memory cell comprises: a source region; a drain region; a channel region connected between the source region and the drain region, wherein the channel region has a first sidewall, a second sidewall, and a top surface connecting the first sidewall and the second sidewall; a first storage node formed on the first sidewall of the channel region; a second storage node formed on the second sidewall of the channel region; a first control gate electrode layer disposed on the first storage node; and a second control gate electrode layer disposed on the second storage node; a first word line connected to the first control gate electrode layer of the memory cells in a first row of the array; a second word line connected to the second control gate electrode layer of the memory cells in the first row of the array; a first bit line connected to the drain region of the memory cells in a first column of the array; and a second bit line connected to the source region of the memory cells in the first column of the array.

[0178] In some embodiments, the first word line and the second word line extend along a first direction, and the first bit line and the second bit line extend along a second direction. In some embodiments, the channel region extends along the first direction. In some embodiments, the memory cell further includes: a third storage node formed on a first sidewall of the channel region; a fourth storage node formed on a second sidewall of the channel region, wherein the third storage node and the fourth storage node are arranged side by side with the first storage node and the second storage node, respectively; a third control gate electrode layer arranged on the third storage node; and a fourth control gate electrode layer arranged on the fourth storage node. In some embodiments, the integrated circuit further includes: a third word line connected to the third control gate electrode layer of the memory cells in the first row of the array; and a fourth word line connected to the fourth control gate electrode layer of the memory cells in the first row of the array.

[0179] Some embodiments of the present disclosure provide a memory cell comprising: a source region; a drain region; a channel region connecting the source region and the drain region, wherein the channel region has a first sidewall, a second sidewall, and a top surface connecting the first sidewall and the second sidewall; a storage gate electrode layer disposed on the channel region; a first control gate electrode layer disposed on the storage gate electrode layer, wherein the first control gate electrode layer faces the first sidewall of the channel region; and a second control gate electrode layer disposed on the storage gate electrode layer, wherein the second control gate electrode layer faces the second sidewall of the channel region, and the first control gate electrode layer and the second control gate electrode layer are electrically isolated from each other. The storage gate electrode layer comprises a first portion, a second portion, and a top portion. The first portion is disposed between the first control gate electrode layer and the first sidewall of the channel region. The second portion is disposed between the second control gate electrode layer and the second sidewall of the channel region. The top portion is disposed above the top surface of the channel region, wherein the top portion connects the first portion and the second portion.

[0180] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures for achieving the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications may be made herein without departing from the spirit and scope of the present disclosure.

Claims

1. A memory cell, characterized in that: include: a source region; a drain region; a channel region connecting the source region and the drain region, wherein the channel region has a first sidewall, a second sidewall, and a top surface connecting the first sidewall and the second sidewall; a first gate dielectric layer disposed on the channel region; a storage gate electrode layer disposed on the first gate dielectric layer; a first control gate electrode layer disposed on the storage gate electrode layer, wherein the first control gate electrode layer faces the first sidewall of the channel region; and A second control gate electrode layer is disposed on the storage gate electrode layer, wherein the second control gate electrode layer faces the second sidewall of the channel region, and the first control gate electrode layer and the second control gate electrode layer are electrically isolated from each other.

2. The memory cell according to claim 1, wherein: The storage gate electrode layer includes: a first portion disposed between the first control gate electrode layer and the first sidewall of the channel region; a second portion disposed between the second control gate electrode layer and the second sidewall of the channel region; and A top portion is disposed above the top surface of the channel region, wherein the top portion connects the first portion and the second portion.

3. The memory cell according to claim 1, wherein: The first gate dielectric layer extends along a bottom surface of the storage gate electrode layer and is disposed between the storage gate electrode layer and the first control gate electrode layer.

4. The memory cell according to claim 1, wherein: The channel region includes two or more semiconductor fins.

5. A memory cell, characterized in that: include: a source region; a drain region; a channel region connecting the source region and the drain region, wherein the channel region has a first sidewall, a second sidewall, and a top surface connecting the first sidewall and the second sidewall; a storage gate electrode layer disposed on the channel region; a first control gate electrode layer disposed on the storage gate electrode layer, wherein the first control gate electrode layer faces the first sidewall of the channel region; and a second control gate electrode layer disposed on the storage gate electrode layer, wherein the second control gate electrode layer faces the second sidewall of the channel region, and the first control gate electrode layer and the second control gate electrode layer are electrically isolated from each other; The storage gate electrode layer includes: a first portion disposed between the first control gate electrode layer and the first sidewall of the channel region; a second portion disposed between the second control gate electrode layer and the second sidewall of the channel region; and A top portion is disposed above the top surface of the channel region, wherein the top portion connects the first portion and the second portion.

6. An integrated circuit, characterized in that: include: An array includes a plurality of memory cells, wherein each memory cell includes: a source region; a drain region; a channel region connected between the source region and the drain region, wherein the channel region has a first sidewall, a second sidewall, and a top surface connecting the first sidewall and the second sidewall; a first storage node formed on the first sidewall of the channel region; a second storage node formed on the second sidewall of the channel region; a first control gate electrode layer disposed on the first storage node; and a second control gate electrode layer, disposed on the second storage node; a first word line connected to the first control gate electrode layer of the plurality of memory cells in a first row of the array; a second word line connected to the second control gate electrode layers of the plurality of memory cells in the first row of the array; a first bit line connected to the drain regions of the memory cells in a first column of the array; and A second bit line is connected to the source regions of the plurality of memory cells in the first column of the array.

7. The integrated circuit according to claim 6, wherein: The first word line and the second word line extend along a first direction, and the first bit line and the second bit line extend along a second direction.

8. The integrated circuit according to claim 7, wherein: The channel region extends along the first direction.

9. The integrated circuit according to claim 6, wherein: The memory cell further comprises: a third storage node formed on the first sidewall of the channel region; a fourth storage node formed on the second sidewall of the channel region, wherein the third storage node and the fourth storage node are disposed side by side with the first storage node and the second storage node, respectively; a third control gate electrode layer disposed on the third storage node; and A fourth control gate electrode layer is disposed on the fourth storage node.

10. The integrated circuit according to claim 9, wherein: Further including: a third word line connected to the third control gate electrode layer of the plurality of memory cells in the first row of the array; and A fourth word line is connected to the fourth control gate electrode layer of the plurality of memory cells in the first row of the array.

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