Testing device with Interlock circuit and ATE testing system

Abstract

The utility model provides a testing device with an Interlock circuit and an ATE testing system, the testing device comprises a control board and a plurality of electrically connected testing boards, the Interlock circuit is arranged on the control board, and at least three corners of each testing board are respectively provided with at least one first detection point; the Interlock circuit comprises an isolation power supply and an isolation ground, the isolation power supply is connected with a first output end through a first driving chip, the isolation ground is connected with a first input end, and the Interlock circuit is sequentially connected with first detection points of a plurality of test boards in series through the first output end and then connected back to the first input end to form a closed-loop first detection loop; the driving end of the first driving chip is connected with a power supply switch of the system and drives the power supply switch to be switched on or switched off according to the detection result of the first detection loop so as to control the system to supply power to the test board. According to the invention, the electrical connection condition of a plurality of test boards can be comprehensively detected, and the reliability and integrity of Interlock circuit detection are ensured.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit testing, and in particular to a testing device with an interlock circuit and an ATE testing system. Background Art

[0002] During ATE (Automatic Test Equipment) system testing, especially high-power and high-voltage testing, power cabinets or external instruments output high-voltage signals to the test head and the boards within the test head, causing dangerous voltages to be present in the test equipment. For the personal safety of operators, interlock circuits are usually added to the test equipment to ensure that under normal circumstances, operators are not exposed to dangerous voltages.

[0003] However, the current interlock circuit usually has only one or two detection points, which cannot fully and accurately detect the electrical connection status of each test board in the test equipment, and is prone to erroneous judgment. Utility Model Content

[0004] In view of this, the present application proposes a test device and an ATE test system with an interlock circuit. By setting detection points at multiple corners of the test board, and connecting the interlock circuit in series with the detection points of each test board to form a closed-loop detection circuit, a comprehensive detection of the electrical connection conditions of multiple test boards can be achieved, thereby ensuring the reliability and integrity of the interlock circuit detection.

[0005] In a first aspect, the present application provides a test device with an interlock circuit, comprising a control board and a plurality of electrically connected test boards, wherein the interlock circuit is arranged on the control board, and at least three corners of each test board are respectively provided with at least one first detection point;

[0006] The interlock circuit includes an isolated power supply and an isolated ground. The isolated power supply is connected to the first output terminal through a first driver chip, and the isolated ground is connected to the first input terminal. The interlock circuit is connected in series with the first detection points of the plurality of test boards through the first output terminal and then connected back to the first input terminal to form a closed first detection circuit for detecting whether the electrical connections of the plurality of test boards are normal.

[0007] The driving end of the first driving chip is connected to the power switch of the system, and drives the power switch to be turned on or off according to the detection result of the first detection circuit, so as to control the power supply of the system to the test board.

[0008] As described above, the present application arranges an interlock circuit on the control board, sets at least one first detection point at at least three corners of each test board, and connects the interlock circuit in series with the first detection point of each test board to form a closed-loop first detection circuit, which can detect the electrical connection status between several test boards in real time, and the first driver chip in the interlock circuit controls the power switch of the system according to the detection result of the first detection circuit. If an abnormal connection between the test boards is detected, the system can automatically cut off the power supply, thereby avoiding misjudgment in cases such as single point contact or board warping of the test board, avoiding potential electrical hazards and equipment damage, and enhancing the safety of the entire test system. In addition, the present application also reduces the impact of electrical interference on the detection circuit by using isolated power and isolated ground, and avoids misjudgment caused by short circuit between the detection circuit and other ground terminals. Through the functions of real-time monitoring and automatic power cut-off, the test device can respond quickly when a fault occurs, reducing equipment damage and downtime caused by the expansion of the fault. The present application also has high flexibility and scalability, and the number of instruments connected to the interlock circuit can be increased or decreased according to actual needs to adapt to different test scenarios and requirements.

[0009] Optionally, at least one switch module is connected in parallel to the output side of the first driver chip of the interlock circuit, and the output end of the switch module is connected in parallel to several extended interlock circuits. The first driver chip realizes interlock control of several extended interlock circuits by controlling the conduction or disconnection of the switch module.

[0010] From the above, the first driver chip controls the conduction or disconnection of the switch module, thereby realizing the interlocking control of several extended interlock circuits connected in parallel to the output end of the switch module, thereby making the present application more flexible and scalable, and being able to connect and manage multiple external devices or subsystems as needed.

[0011] Optionally, the first output terminal and the first input terminal of the interlock circuit are connected in parallel with a first shielding switch circuit for implementing short-circuit control of the first detection loop.

[0012] As described above, by setting a first shielding switch circuit in the Interlock circuit, the user can temporarily disable the detection function of the Interlock circuit by short-circuiting the first detection loop during debugging or special testing scenarios, avoiding triggering the protection mechanism of the Interlock circuit unnecessarily, thereby improving the convenience of debugging and testing.

[0013] Optionally, a microprocessor is also arranged on the control board, which is used to store the switching state of the first shielding switch circuit and / or the detection result and / or short-circuit state of the first detection loop, so that the system performs logical control of the test board according to the switching state and / or detection result and / or short-circuit state.

[0014] As shown above, the microprocessor not only stores the test results or short-circuit status of the first detection circuit, but also stores the on / off status of the first shielding switch circuit. This design enables the system to fully understand the status of the test device, including which parts are being tested and which parts are temporarily shielded. Based on this information, the system can perform more precise and efficient logic control while ensuring data integrity and traceability.

[0015] Optionally, the first shielding switch circuit includes a first switch with two normally open contacts connected in parallel to the first output end and the first input end of the interlock circuit, wherein one normally open contact is used to implement short-circuit control of the first detection loop, and the other normally open contact is used to output the switching state of the first switch to the microprocessor.

[0016] From the above, the present application can realize short-circuit control of the first detection circuit through a switch with dual normally open contacts. Specifically, the short-circuit control of the first detection circuit can be realized by utilizing one normally open contact of the switch, and the other normally open contact is used to output the switching state of the switch to the microprocessor, so that the system can obtain the switch state stored in the microprocessor at any time, and execute corresponding logical control according to the switch state to ensure the accuracy and safety of the testing process.

[0017] Optionally, the first shielding switch circuit includes a first driving circuit and a first isolation circuit;

[0018] The input end of the first driving circuit is connected to the output end of the microprocessor, the output end of the first driving circuit is connected to the input end of the first isolation circuit, and the output end of the first isolation circuit is connected to the first output end of the interlock circuit and the isolation ground respectively;

[0019] The microprocessor controls the first drive circuit to be turned on, so as to turn on the first isolation circuit, thereby achieving short-circuit control of the first detection loop.

[0020] Based on the above, the present application can also design the first shielding switch circuit to include a combination of a first drive circuit and a first isolation circuit. Specifically, when the detection function of the interlock circuit needs to be shielded, the microprocessor sends a control signal to turn on the first drive circuit, thereby triggering the first isolation circuit to turn on, short-circuiting the first output terminal of the interlock circuit to the isolation ground, thereby achieving short-circuit control of the first detection loop. The first isolation circuit can also achieve electrical isolation, effectively isolating the direct electrical connection between the control signal and the interlock circuit, which not only improves system safety but also reduces malfunctions caused by electrical interference.

[0021] Optionally, the system further includes an explosion-proof shell disposed on top of the plurality of test boards, wherein at least one second detection point is respectively disposed on at least two opposite corners of the explosion-proof shell and each test board;

[0022] The isolated power supply of the interlock circuit is connected to the second output terminal through the second driver chip and is isolatedly connected to the second input terminal. The interlock circuit is connected in series with several test boards and the second detection point of the explosion-proof shell through the second output terminal and then connected back to the second input terminal to form a closed second detection circuit for detecting whether the explosion-proof shell is properly covered;

[0023] The second input terminal is connected to the power control circuit of at least one of the test boards through a trigger circuit, and the trigger circuit controls the switching state of the power control circuit of the test board according to the high and low levels output by the second output terminal.

[0024] As mentioned above, an explosion-proof shell is usually set on the top of the test board of the test device to protect the test board and its internal components from potential dangers in the external environment, and to prevent abnormal situations such as pipe explosion during testing from causing danger to operators and nearby equipment. Since the explosion-proof shell needs to be opened every time the device under test is replaced, if the detection point of the explosion-proof shell is connected in series with the first detection circuit, each time the explosion-proof shell is opened, the power supply of the system will be disconnected, and the system will take time to re-power, thereby affecting the efficiency of the test. Therefore, the present application sets a second detection point at the opposite corners of the test board and the explosion-proof shell, and connects the interlock circuit in series with the second detection point of each test board and the explosion-proof shell to form a closed-loop second detection circuit. This can detect the covering state of the explosion-proof shell. When it is detected that the explosion-proof shell is not covered properly, the system can control the power control circuit of the test board to disconnect through a trigger circuit. The trigger circuit can be flexibly connected to different test boards, thereby cutting off the power supply of a certain test board according to the test requirements without cutting off the power supply of the entire system, preventing potential dangers or test errors caused by the explosion-proof shell not being covered properly.

[0025] Optionally, the second output terminal and the second input terminal of the interlock circuit are connected in parallel with a second shielding switch circuit for implementing short-circuit control of the second detection loop.

[0026] As described above, by providing a second shielding switch circuit in the interlock circuit, the user can temporarily disable the detection function of the interlock circuit by shorting the second detection loop during debugging or special testing scenarios, thereby avoiding triggering the protection mechanism of the interlock circuit unnecessarily, thereby improving the convenience of debugging and testing.

[0027] Optionally, a microprocessor is also arranged on the control board, which is used to store the switching state of the second shielding switch circuit and / or the detection result or short-circuit state of the second detection loop, so that the system performs logical control of the test board according to the switching state and / or detection result or short-circuit state.

[0028] Furthermore, the microprocessor is used not only to store the detection result or short-circuit status of the second detection circuit, but also to store the switch status of the second shielding switch circuit, so that the system can perform more accurate and effective logic control while ensuring the integrity and traceability of the data.

[0029] Optionally, the second shielding switch circuit includes a second switch connected in parallel to the second output terminal and the second input terminal of the interlock circuit, and the second switch is used to implement short-circuit control of the second detection loop.

[0030] As described above, when it is necessary to temporarily disable the interlock circuit from detecting the closing state of the explosion-proof housing, the switch can be used to implement short-circuit control of the second detection circuit, thereby improving the safety, reliability and test efficiency of the system.

[0031] Optionally, the second shielding switch circuit includes a second driving circuit and a second isolation circuit;

[0032] The input end of the second driving circuit is connected to the output end of the microprocessor, the output end of the second driving circuit is connected to the input end of the second isolation circuit, and the output end of the second isolation circuit is connected to the second output end of the interlock circuit and the isolation ground respectively;

[0033] The microprocessor controls the second driving circuit to be turned on, so as to turn on the second isolation circuit, thereby achieving short-circuit control of the second detection loop.

[0034] Based on the above, the present application can also design the second shielding switch circuit to include a combination of a second drive circuit and a second isolation circuit. Specifically, when the detection function of the interlock circuit needs to be shielded, the microprocessor sends a control signal to turn on the second drive circuit, thereby triggering the second isolation circuit to turn on, short-circuiting the second output terminal of the interlock circuit to the isolation ground, thereby achieving short-circuit control of the second detection loop. The second isolation circuit can also achieve electrical isolation, effectively isolating the direct electrical connection between the control signal and the interlock circuit, not only improving system safety but also reducing malfunctions caused by electrical interference.

[0035] Optionally, a plurality of switch modules are connected in series between the first input terminal of the interlock circuit and the isolation ground, and the plurality of switch modules are used to connect at least one external device to implement interlocking control between the interlock circuit and the external device.

[0036] As described above, by connecting several switch modules in series between the first input terminal of the interlock circuit and the isolation ground, these modules can act as a bridge connecting the external device and the interlock circuit. Through the switch modules, signals from the external device can be received and transmitted to the interlock circuit, thereby realizing interlocking control between the interlock circuit and the external device.

[0037] In a second aspect, the present application provides an ATE test system, comprising a host computer system, a power supply system, and the above-mentioned test device with an interlock circuit;

[0038] The host computer system performs logic control on the test board in the test device with the interlock circuit according to the detection result of the test device with the interlock circuit;

[0039] The power supply system controls power supply to a test board in the test device having the interlock circuit according to a detection result of the test device having the interlock circuit.

[0040] These and other aspects of the present application will become more apparent from the following description of the embodiment(s). BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 A circuit diagram of a first test device with an interlock circuit provided in an embodiment of the present application;

[0042] Figure 2 A circuit diagram of a second test device with an interlock circuit provided in an embodiment of the present application;

[0043] Figure 3 A structural diagram of a first test device with an interlock circuit provided in an embodiment of the present application;

[0044] Figure 4 A structural diagram of a second test device with an interlock circuit provided in an embodiment of the present application;

[0045] Figure 5 A circuit diagram of a first shielding switch circuit provided in an embodiment of the present application;

[0046] Figure 6 A circuit diagram of a second shielding switch circuit provided in an embodiment of the present application;

[0047] Figure 7 A circuit diagram of a first optocoupler circuit provided in an embodiment of the present application;

[0048] Figure 8-Figure 9 A circuit diagram of a second optocoupler circuit provided in an embodiment of the present application;

[0049] Figure 10-11 A circuit diagram of a third optocoupler circuit provided in an embodiment of the present application;

[0050] Figure 12 A circuit diagram of an extended interlock circuit provided in an embodiment of the present application;

[0051] Figure 13 This is a structural diagram of an ATE test system provided in an embodiment of the present application.

[0052] It should be understood that the sizes and shapes of the blocks in the above structural diagrams are for reference only and should not constitute an exclusive interpretation of the embodiments of this application. The relative positions and inclusion relationships between the blocks presented in the structural diagrams are only schematic representations of the structural relationships between the blocks, and do not limit the physical connection methods of the embodiments of this application. DETAILED DESCRIPTION

[0053] The technical solution provided by this application is further described below with reference to the accompanying drawings and examples. It should be understood that the system structure and business scenarios provided in the examples of this application are mainly for illustrating possible implementation methods of the technical solution of this application and should not be interpreted as the sole limitation of the technical solution of this application. It is known to those skilled in the art that with the evolution of the system structure and the emergence of new business scenarios, the technical solution provided by this application is also applicable to similar technical problems.

[0054] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of this application. In the event of any inconsistency, the meaning described in this specification or the meaning derived from the contents recorded in this specification shall prevail. In addition, the terms used herein are only for the purpose of describing the embodiments of the present application and are not intended to limit this application.

[0055] The embodiments of the present application provide a test device and an ATE test system with an interlock circuit. By setting detection points at multiple corners of each test board of the test device, and connecting the interlock circuit in series with the detection points of each test board to form a closed-loop detection circuit, a comprehensive detection of the electrical connection conditions of multiple test boards can be achieved, thereby ensuring the reliability and integrity of the interlock circuit detection. The detection results are also stored by a microprocessor so that the system can perform logical control of the test boards based on the detection results.

[0056] like Figure 1 As shown, an embodiment of the present application provides a test device with an interlock circuit, which includes a control board (Power Management Unit, PMU) and several test boards. Exemplarily, the test board can be a test resource interface board (Tester Interface Board, TIB), a test head board (Tester Head Board, THB) and a device interface board (Device Interface Board, DIB). The three test boards TIB, THB, and DIB can be electrically connected through spring pins or PCB connectors. The interlock circuit is arranged on the control board PMU, and at least three corners of the test boards TIB, THB, and DIB are respectively provided with at least one detection point, with reference to Figure 1 As shown, the detection points of the three corners of each test board are pinA1, pinB1, and pinC1. It can be understood that in the embodiment of the present application, the number of test boards can be two, and the present application is not limited to this.

[0057] The interlock circuit of the control board PMU includes an isolated power supply F12V and an isolated ground FGND. These are electrically isolated from all other system grounds (DGND and AGND). They can be used to power the detection circuit, reduce the impact of electrical interference on the detection circuit, and prevent misjudgments caused by short circuits between the detection circuit and other parts of the system. Specifically, the isolated power supply F12V is connected to the first output terminal Interlock+ of the interlock circuit via a resistor R1 and a driver chip K1. The isolated ground FGND is connected to the first input terminal Interlock- of the interlock circuit.

[0058] Reference Figure 1 As shown, the Interlock circuit can connect the detection points of the three corners of the test boards TIB, THB, and DIB in series through its first output terminal Interlock+ and then connect back to the first input terminal Interlock- to form a closed-loop first detection circuit (Interlock detection circuit) to detect whether the electrical connections of the three test boards TIB, THB, and DIB are normal. The specific connection method of the Interlock detection circuit is F12V→R1→K1→Interlock+→pinA1 of TIB→pinA1 of THB→pinA1 of DIB→pinB1 of DIB→pinB1 of THB→pinB1 of TIB→pinC1 of TIB→pinC1 of THB→pinC1 of DIB→Interlock-→FGND. Based on this, the Interlock circuit can detect the electrical connection status of the three test boards TIB, THB, and DIB based on whether the Interlock detection circuit is conductive, avoiding misjudgment in situations such as single-point contact or warping of the test board surface. When the interlock detection circuit is connected, the driver chip K1 is turned on, driving the system's power switch to turn on, ensuring normal power supply to the test boards TIB, THB, and DIB. If the interlock detection circuit connection is abnormal, the driver chip K1 is turned off, driving the system's power switch to turn off, cutting off the normal power supply to the test boards TIB, THB, and DIB. This prevents current from flowing through the faulty path, thereby avoiding potential electrical hazards and equipment damage, and enhancing the safety of the entire test system.

[0059] like Figure 2As shown, the embodiment of the present application provides another test device with an interlock circuit, which includes a control board (Power Management Unit, PMU) and three test boards, wherein the control board PMU is arranged with an interlock circuit and a microprocessor MCU, and two detection points are set at the four corners of the test board TIB, THB, and DIB respectively. Figure 2 As shown in FIG, the detection points of the four corners of each test board are pinA1, pinA2, pinB1, pinB2, pinC1, pinC2, pinD1, pinD2.

[0060] The interlock circuit of the control board PMU includes an isolated power supply F12V and an isolated ground FGND. The isolated power supply F12V and the isolated ground FGND are electrically isolated from all other grounds in the system (DGND, AGND). They can be used to power the detection circuit, reduce the impact of electrical interference on the detection circuit, and prevent misjudgments caused by short circuits between the detection circuit and other parts of the system. Specifically, the isolated power supply F12V is connected to the first output terminal Interlock+ of the interlock circuit through a resistor R1 and a driver chip K1. The isolated ground FGND can be connected in series with multiple switch modules (Handler, Tester, Cabinet) and then connected to the first input terminal Interlock- of the interlock circuit. The multiple switch modules can each be connected to at least one external device. Through the switch module, signals from the external device can be received and transmitted to the interlock circuit, thereby achieving interlock control between the interlock circuit and the external device.

[0061] Reference Figure 2 and Figure 3As shown, the Interlock circuit can connect two detection points at the four corners of the test boards TIB, THB, and DIB in series through its first output terminal Interlock+ and then connect back to the first input terminal Interlock- to form a closed-loop first detection circuit (Interlock detection circuit) for detecting whether the electrical connections of the three test boards TIB, THB, and DIB are normal. The specific connection method of the Interlock detection circuit is F12V→R1→K1→Interlock+→pinA1 of TIB→pinA1 of THB→pinA1 of DIB→pinA2 of DIB→pinA2 of THB→pinA2 of TIB→pinB1 of TIB→pinB1 of THB→pinB1 of DIB→pinB2 of DIB→pinB2 of THB→pinB2 of TIB→pinC1 of TIB→pinC1 of THB→pinC1 of DIB→pinC2 of DIB→pinC2 of THB→pinC2 of TIB→pinD1 of TIB→pinD1 of THB→pinD1 of DIB→pinD2 of DIB→pinD2 of THB→pinD2 of TIB→Interlock-→Handler→Tester→Cabinet→FGND. Based on this, the interlock circuit can detect the electrical connection status of the three test boards TIB, THB, and DIB based on whether the interlock detection circuit is conductive, avoiding misjudgments in situations such as single-point contact or board warping on the test board. When the interlock detection circuit is conductive, the driver chip K1 is conductive, which drives the system's power switch to turn on, ensuring normal power supply to the system's test boards TIB, THB, and DIB. When the interlock detection circuit is abnormally connected, the driver chip K1 is not conductive, thereby driving the system's power switch to turn off, cutting off the system's normal power supply to the test boards TIB, THB, and DIB, preventing current from passing through the fault path, thereby avoiding potential electrical hazards and equipment damage, and enhancing the safety of the entire test system.

[0062] In some embodiments, since the interlock detection circuit is used to detect the electrical connections between multiple test boards, it can also be used to detect the three corners of the test board. Since the test board is generally a regular quadrilateral, when the three corners are tested and the connection is normal, the connection of the fourth corner is generally normal. The interlock circuit can also be connected in series via the first output terminal Interlock+ to the two detection points of the three corners of the test boards TIB, THB, and DIB, and then connected back to the first input terminal Interlock- to form a closed-loop first detection circuit (interlock detection circuit). This is used to detect whether the electrical connections of the three test boards TIB, THB, and DIB are normal by detecting the connection of the three corners. The specific connection method of the interlock detection circuit is (not shown in the figure): F12V → R1 → K1 → Interlock+ → TIB pinA1 → THB pinA1 → DIB pinA1 → DIB pinA2 → THB pinA2 → TIB pinA2 → TIB pinB1 → THB pinB1 → DIB pinB1 → DIB pinB2 → THB pinB2 → TIB pinB2 → TIB pinC1 → THB pinC1 → DIB pinC1 → DIB pinC2 → THB pinC2 → TIB pinC2 → Interlock- → Handler → Tester → Cabinet → FGND. Based on this, the interlock circuit can detect the electrical connection status of the three test boards (TIB, THB, and DIB) based on whether the interlock detection circuit is conductive.

[0063] In some embodiments, an explosion-proof housing is typically installed on top of the test board of the test device to protect the test board and its internal components from potential hazards in the external environment and to prevent hazards to operators and nearby equipment in the event of an abnormal situation such as a pipe explosion during testing. During manual testing, after each device is tested, the explosion-proof housing must be manually opened to replace the device, and testing must be resumed immediately after replacement. If the detection points of the explosion-proof housing are connected in series to the interlock detection circuit, each opening of the explosion-proof housing will cause the interlock detection circuit to disconnect, thereby disconnecting the system power supply. Re-powering the system requires time, thus affecting test efficiency. Therefore, for manual testing scenarios, additional detection points can be set on each test board. By connecting these additional detection points on each test board in series with the detection points of the explosion-proof housing to form a second detection circuit (Cover detection circuit), the second detection circuit is isolated from the interlock detection circuit and prevents the interlock detection circuit from being disconnected when the explosion-proof housing is opened. Specifically, two detection points can be set at two opposite corners of the test boards TIB, THB, and DIB, respectively, namely pinA3 and pinA4, and pinC3 and pinC4. The isolated power supply F12V is connected to the second output terminal Cover+ of the interlock circuit via the resistor R2 and the driver chip K2 , and the isolated ground FGND is connected to the second input terminal Cover− of the interlock circuit.

[0064] Reference Figure 2 and Figure 3As shown, the interlock circuit can connect two detection points at two corners of the test boards TIB, THB, and DIB in series through its second output terminal Cover+, and then connect back to the second input terminal Cover- to form a closed second detection circuit (Cover detection circuit) for detecting the cover status of the explosion-proof shell and whether the electrical connections of the three test boards TIB, THB, and DIB are normal. The specific connection method of the Cover detection circuit is F12V→R2→K2→Cover+→pinA3 of TIB→pinA3 of THB→pinA3 of DIB→explosion-proof shell→pinA4 of DIB→pinA4 of THB→pinA4 of TIB→pinA4 of TIB→pinC3 of TIB→pinC3 of THB→pinC3 of DIB→explosion-proof shell→pinC4 of DIB→pinC4 of THB→pinC4 of TIB→Cover-→FGND. Based on this, the interlock circuit can detect the cover status of the explosion-proof shell and the electrical connection status of the three test boards TIB, THB, and DIB based on whether the cover detection circuit is conductive. The second input terminal Cover- is connected to the power control circuit of at least one test board via a trigger circuit. When it is detected that the explosion-proof shell is not properly covered, the cover detection circuit is disconnected, and the system can control the power control circuit of the test board to disconnect through the trigger circuit, thereby cutting off the power supply to the test board. The trigger circuit in this embodiment can be flexibly connected to different test boards, thereby cutting off the power supply to a specific test board according to test requirements without cutting off the power supply to the entire system, thereby preventing potential dangers or test errors caused by the explosion-proof shell not being properly covered.

[0065] In some embodiments, a detection point can be set at each of the four corners of the test board TIB, THB, or DIB to detect the electrical connection status. Figure 4As shown, the detection points at the four corners of each test board are pinA1, pinB1, pinC1, and pinD1. The interlock circuit can connect one detection point at the four corners of the test boards TIB, THB, and DIB in series through its first output terminal Interlock+, and then connect back to the first input terminal Interlock- to form a closed-loop interlock detection circuit. The specific connection method of the interlock detection circuit is F12V→R1→K1→Interlock+→TIB pinA1→THB pinA1→DIB pinA1→DIB pinB1→THB pinB1→TIB pinB1→TIB pinC1→THB pinC1→DIB pinC1→DIB pinD1→THB pinD1→TIB pinD1→Interlock-→Handler→Tester→Cabinet→FGND. Based on this, the interlock circuit can detect the electrical connection status of the three test boards TIB, THB, and DIB based on whether the interlock detection circuit is conductive.

[0066] Similarly, a detection point can be set at two opposite corners of the test boards TIB, THB, and DIB, namely pinA2 and pinC2. The interlock circuit can connect a detection point of the two corners of the test boards TIB, THB, and DIB in series through its second output terminal Cover+ and then connect it back to the second input terminal Cover- to form a closed-loop Cover detection circuit, which is used to detect the covering state of the explosion-proof shell and whether the electrical connection of the three test boards TIB, THB, and DIB is normal. The specific connection method of the Cover detection circuit is F12V→R2→K2→Cover+→pinA2 of TIB→pinA2 of THB→pinA2 of DIB→explosion-proof shell→pinC2 of DIB→pinC2 of THB→pinC2 of TIB→Cover-→FGND. Based on this, the interlock circuit can detect the covering state of the explosion-proof shell and the electrical connection state of the three test boards TIB, THB, and DIB according to whether the Cover detection circuit is conductive.

[0067] In some application scenarios, the introduction of the interlock circuit will affect the convenience of debugging and manual testing, such as Figure 2As shown, this embodiment connects a first shielding switch circuit in parallel to the first output terminal Interlock+ and the first input terminal Interlock- of the interlock circuit to implement short-circuit control of the interlock detection loop. It also connects a second shielding switch circuit in parallel to the second output terminal Cover+ and the second input terminal Cover- of the interlock circuit to implement short-circuit control of the cover detection loop. These first and second shielding switch circuits allow users to temporarily disable the interlock circuit's detection function during debugging or special testing scenarios by short-circuiting the interlock detection loop and the cover detection loop, avoiding unnecessary triggering of the interlock circuit's protection mechanism and thus improving debugging and testing convenience.

[0068] The shielding switch circuit of this embodiment can be implemented by hardware switch or by logic control, so that users can select the shielding mode according to the debugging requirements, which greatly improves the convenience of debugging and manual testing. Figure 2 As shown, the first shielding switch circuit can be implemented using a first switch with two normally open contacts, such as a relay switch MAINT with two normally open contacts. Specifically, one normally open contact of the relay switch MAINT is used to implement short-circuit control of the interlock detection circuit, while the other normally open contact is used to output the switch state of the relay switch MAINT to the microprocessor MCU. The first shielding switch circuit can also implement short-circuit control of the interlock detection circuit via a control signal Interlock_Bypass output by the microprocessor MCU, so that the system can obtain the switch state of the relay switch MAINT stored in the microprocessor MCU or the control signal Interlock_Bypass output by it at any time, and perform corresponding logical control based on the switch state or control signal, ensuring the accuracy and safety of the test process. The second shielding switch circuit can implement short-circuit control of the cover detection circuit via a second switch COVER or a control signal Cover_Bypass output by the microprocessor MCU. The system can also obtain the control signal Cover_Bypass output by the microprocessor MCU at any time and perform corresponding logical control based on the control signal. The second switch here can be a relay switch, a rotary switch, a push button switch, a mechanical switch, etc., and this embodiment is not limited to this.

[0069] like Figure 5As shown, in one implementation, the microprocessor MCU can implement short-circuit control of the interlock detection loop via a first shielding switch circuit. The first shielding switch circuit includes a first drive circuit and a first isolation circuit. Specifically, for example, the first drive circuit is a MOS transistor, and the first isolation circuit is a T10 photocoupler U32. The gate of the MOS transistor T10 receives the control signal Interlock_Bypass output by the microprocessor MCU via a resistor R342, and the drain is connected to the power supply terminal 3.3VD via a resistor R143, and the source is connected to the ground DGND. The gate and source of the MOS transistor T10 are also connected in parallel to a voltage stabilization circuit consisting of a Zener diode D44 and a resistor R347. The drain of the MOS transistor T10 is connected to the light-emitting side output terminal of the photocoupler U32, and the light-emitting side input terminal of the photocoupler U32 is connected to the power supply terminal 3.3VD via a resistor R144. The light-sensing side of the photocoupler U32 is connected in parallel to the first output terminal Interlock+ of the interlock circuit and the isolation ground FGND. The microprocessor MCU outputs a high-level control signal, Interlock_Bypass, to turn on the MOS transistor T10, thereby pulling down the level of the light-emitting output terminal of the optocoupler U32. This in turn drives the optocoupler U32 to conduct, connecting the first output terminal Interlock+ to the isolation ground FGND, thereby short-circuiting the interlock detection circuit and disabling the interlock detection function. It will be appreciated that the first drive circuit and the first isolation circuit of this embodiment can be implemented in a variety of ways. The above implementation is merely illustrative and is not intended to limit this embodiment.

[0070] Similarly, in one implementation, if Figure 6As shown, the microprocessor MCU can implement short-circuit control of the Cover detection loop through a second shielding switch circuit, which includes a second drive circuit and a second isolation circuit. Specifically, for example, the second drive circuit is a MOS transistor T9, and the second isolation circuit is a photocoupler U33. The gate of the MOS transistor T9 receives the control signal Cover_Bypass output by the microprocessor MCU through a resistor R341, the drain is connected to the power supply terminal 3.3VD through a resistor R148, and the source is grounded DGND. The gate and source of the MOS transistor T9 are also connected in parallel to a voltage stabilization circuit consisting of a voltage regulator diode D43 and a resistor R346. The drain of the MOS transistor T9 is connected to the light-emitting side output terminal of the photocoupler U33, the light-emitting side input terminal of the photocoupler U33 is connected to the power supply terminal 3.3VD through a resistor R149, and the light-sensitive side of the photocoupler U33 is connected in parallel to the second output terminal Cover+ of the interlock circuit and the isolation ground FGND. The microprocessor MCU outputs a high-level control signal, Cover_Bypass, to turn on MOS transistor T9, thereby pulling down the level of the light-emitting output terminal of the optocoupler U33. This in turn drives optocoupler U33 to conduct, connecting the second output terminal Cover+ to the isolation ground FGND, thereby short-circuiting the Cover detection circuit and disabling the Cover detection function. It will be appreciated that the second drive circuit and the second isolation circuit of this embodiment can be implemented in a variety of ways. The above implementation is merely an example and is not intended to limit this embodiment.

[0071] In some embodiments, the microprocessor MCU can obtain the switching state of the relay switch MAINT through an isolation circuit, where the isolation circuit can be a first optical coupler circuit. Figure 7As shown, the first optocoupler circuit includes a photocoupler U31. The light-side input of the photocoupler U31 is connected to the power supply terminal 12V through parallel resistors R162 and R163. The light-side output of the photocoupler U31 is connected to the normally open contact Main_Interlock of the relay switch MAINT. The light-sensitive input of the photocoupler U31 is connected to the power supply terminal 3.3VD through a resistor R147. The light-sensitive output of the photocoupler U31 is grounded to DGND. The light-sensitive input is also connected to the microprocessor MCU and outputs a level signal Main_Interlock_State to the microprocessor MCU. When the relay switch MAINT is off, the photocoupler U31 is non-conductive, and its light-sensitive input output outputs a high-level signal Main_Interlock_State to the microprocessor MCU. When the relay switch MAINT is closed, the normally open contact Main_Interlock is connected to AGND, the light-side output of the photocoupler U31 is pulled low, the photocoupler U31 is turned on, and the level signal Main_Interlock_State at its light-sensitive input is pulled low. Based on this, the microprocessor can identify and store the switch state of the relay switch MAINT based on the high and low level signals Main_Interlock_State at the light-sensitive input terminal. When the relay switch MAINT is closed, the interlock detection circuit is short-circuited, and the interlock detection function is disabled. Before starting the test, the system software can read the interlock switch state stored in the microprocessor MCU. If the interlock circuit is found to be triggered or short-circuited, the system software can actively display a pop-up window to prevent the test from proceeding.

[0072] In some embodiments, the second input terminal Cover- of the Interlock circuit is connected to the power control circuit of at least one test board through a trigger circuit. When it is detected that the explosion-proof shell is not covered properly, the Cover detection circuit is not conductive, and the system can control the power control circuit of the test board to be disconnected through the trigger circuit, thereby cutting off the power supply of the test board. Figure 8 or Figure 9 As shown, the trigger circuit can be realized by optocoupler U39A or U39B. Figure 8For example, the light-emitting input terminal of the optocoupler U39A is connected to the 24V power supply terminal through parallel resistors R374 and R207. The light-emitting output terminal Cover_Interlock is connected to the second input terminal Cover- of the interlock circuit (when the output of Cover- is high, the Cover_Interlock signal is also high; when the output of Cover- is low, the Cover_Interlock signal is also low, and the high and low states of the Cover_Interlock signal are controlled by Cover-). The light-sensing side of the optocoupler U39A outputs a control signal to the CBIT board, which controls the conduction or disconnection of the power control circuit of each test board through the CBIT board. When the explosion-proof shell is opened and the Cover detection circuit is not conducting, no current flows through its second input terminal Cover-. At this time, the optocoupler U39A is not conducting, and the CBIT board can disconnect the power control circuit of each test board (such as THB and DIB) respectively, cutting off the system's power supply to each test board. When the explosion-proof shell is closed, the Cover detection circuit is turned on, and its second input terminal Cover- is at a low level. Then the optocoupler U39A is turned on, its photosensitive side is turned on and outputs a control signal to the CBIT board. The CBIT board can close the power control circuit of the test board according to the control signal and restore the system's power supply to the test board.

[0073] Similarly, if Figure 9 As shown, the photosensitive side of the photocoupler U39B can output a control signal to the INF board to control the conduction or disconnection of the power control circuit of each test board through the INF board. When the explosion-proof shell is opened and the Cover detection circuit is not conducting, no current flows through its second input terminal Cover-. At this time, the photocoupler U39B is not conducting, and the INF board can disconnect the power control circuit of the test board (such as THB and DIB) respectively, cutting off the system's power supply to each test board. When the explosion-proof shell is closed, the Cover detection circuit is conducting, and its second input terminal Cover- is at a low level, then the photocoupler U39B is conducting, and its photosensitive side is conducting and outputs a control signal to the INF board. The INF board can close the power control circuit of the test board according to the control signal, and restore the system's power supply to the test board.

[0074] like Figure 10As shown, the microprocessor MCU can obtain the short-circuit state of the Interlock detection circuit through the isolation circuit. The isolation circuit here can be a second optocoupler circuit, which includes a photocoupler U46. The light-emitting side input end of the photocoupler U46 is connected to the power supply end 24V through parallel resistors R219 and R220, and the light-emitting side output end Main_Interlock is connected to the first input end Interlock- of the Interlock circuit (when the output of Interlock- is high, the Main_Interlock signal is also high; when the output of Interlock- is low, the Main_Interlock signal is also low, and the high and low states of the Main_Interlock signal are controlled by Interlock-). The photosensitive side input end of the photocoupler U46 is connected to the power supply end 3.3VD through a resistor R177, and the photosensitive side output end is grounded DGND. The photosensitive side input end is also connected to the microprocessor MCU and outputs a level signal Interlock_State to the microprocessor MCU. When the interlock detection circuit is short-circuited, the first input terminal Interlock- of the interlock detection circuit is at a low level, and the Main_Interlock signal at the light-emitting-side output terminal of the photocoupler U46 is at a low level. The photocoupler U46 is turned on and sends a low-level signal Interlock_State to the microprocessor MCU through its light-sensing-side input terminal. When the interlock detection circuit is not short-circuited and not conducting, no current flows through the first input terminal Interlock- of the interlock detection circuit, the photocoupler U46 is not conducting, and its light-sensing-side input terminal sends a high-level signal Interlock_State to the microprocessor. Based on this, the microprocessor MCU can identify the short-circuit state of the interlock detection circuit based on the level signal Interlock_State at the light-sensing-side input terminal of the photocoupler U46.

[0075] Similarly, if Figure 11As shown, the microprocessor MCU can obtain the short-circuit state of the Cover detection circuit through the isolation circuit. The isolation circuit here can be a third optocoupler circuit, which includes a photocoupler U47. The light-emitting side input end of the photocoupler U47 is connected to the power supply end 24V through parallel resistors R222 and R223, and the light-emitting side output end Cover_Interlock is connected to the second input end Cover- of the Interlock circuit (when the output of Cover- is high, the Cover_Interlock signal is also high; when the output of Cover- is low, the Cover_Interlock signal is also low, and the high and low states of the Cover_Interlock signal are controlled by Cover-). The photosensitive side input end of the photocoupler U47 is connected to the power supply end 3.3VD through a resistor R179, and the photosensitive side output end is grounded DGND. The photosensitive side input end is also connected to the microprocessor MCU and outputs a level signal Cover_Interlock_State to the microprocessor MCU. When the Cover detection circuit is short-circuited, the second input terminal Cover- of the Cover detection circuit is at a low level, and the Cover_Interlock signal at the light-emitting side output terminal of the photocoupler U47 is at a low level. The photocoupler U47 is turned on and sends a low-level signal Cover_Interlock_State to the microprocessor through its light-sensitive side input terminal. When the Cover detection circuit is not short-circuited and not turned on, no current flows through the second input terminal Cover- of the Cover detection circuit, the photocoupler U47 is not turned on, and its light-sensitive side input terminal sends a high-level signal Cover_Interlock_State to the microprocessor. Based on this, the microprocessor MCU can identify the short-circuit state of the Cover detection circuit based on the level signal Cover_Interlock_State at the light-sensitive side input terminal of the photocoupler U47.

[0076] The expansion of existing interlock circuits usually requires connecting the expansion circuit in series in the interlock circuit. However, this will increase the impedance of the entire detection loop, limit the number of expansions of the interlock circuit, and thus limit the use of test equipment, such as linkage with external third-party instruments, such as probers, handlers, etc. Based on this, the embodiment of the present application can use a driver chip to drive a relay to achieve the expansion of the interlock circuit, such as Figure 2 The driver chips K1 and K2 in the control board PMU can not only protect the interlock circuit, but also increase the number of interlock circuits to dozens. Figure 12As shown, the main interlock circuit of this embodiment controls the conduction of the relay U1 through the driver chip K1, and other extended interlock circuits can be connected in parallel to the contact end of the relay U1. Therefore, the number of extended interlock circuits is determined by the load capacity of the relay U1. The load capacity of the relay U1 selected in this embodiment is approximately 500mA, and the current driving a single driver chip is within 10mA. Theoretically, a single relay can drive more than 50 driver chips, which makes this embodiment more flexible and scalable, and can connect and manage multiple external devices or subsystems as needed.

[0077] Reference Figure 12 As shown, when the main interlock detection circuit is conducting, driver chip K1 turns on, which in turn turns on relay U1, closing the contacts. This then turns on the parallel-connected driver chips K3, K4, K5, ..., KN, connecting MCU+ and MCU-, Power Cabinet+ and Power Cabinet-, EXT0+ and EXT0-, ..., EXTN+ and EXTN-, allowing the controller, power cabinet, and other system-related input devices to operate normally. When the interlock detection circuit is disconnected, driver chip K1 turns off, turning off relay U1, opening the contacts. This disconnects the parallel-connected driver chips K2, K3, K4, ..., KN, disconnecting MCU+ and MCU-, Power Cabinet+ and Power Cabinet-, EXT0+ and EXT0-, ..., EXTN+ and EXTN-, thereby enabling the main interlock circuit to control the states of all expansion circuits, cutting off the dangerous voltages outputted to the test head by the power cabinet and other system-related input devices, thus preventing operator hazards and device damage.

[0078] It can be understood that the driver chip described in the above embodiments of the present application can be an isolated driver chip.

[0079] In summary, the embodiment of the present application provides a test device with an interlock circuit, arranges the interlock circuit and the microprocessor on the control board, sets at least one detection point at at least three corners of each test board, and connects the interlock circuit in series with the detection points of each test board to form a closed-loop detection circuit, which can detect the electrical connection status between several test boards in real time, and the driver chip in the interlock circuit controls the power switch of the system according to the detection result of the detection circuit. If an abnormal connection between the test boards is detected, the system can automatically cut off the power supply, thereby avoiding misjudgment in cases such as single point contact of the test board or warping of the board surface, avoiding potential electrical hazards and equipment damage, and enhancing the safety of the entire test system. The embodiment of the present application also reduces the impact of electrical interference on the detection circuit by using an isolated power supply and an isolated ground separately, and avoids misjudgment caused by a short circuit between the detection circuit and other ground terminals. In addition, the embodiment of the present application also controls the switch for shielding the interlock circuit function through software or hardware, and the shielding method can be selected according to the debugging requirements, thereby increasing the convenience of debugging and manual testing. The embodiment of the present application uses the functions of real-time monitoring and automatic power cut-off to enable the test device to respond quickly when a fault occurs, reducing equipment damage and downtime caused by the expansion of the fault. The embodiment of the present application also adopts an interlock circuit parallel expansion method, which has high flexibility and scalability. The number of instruments and meters connected to the interlock circuit can be increased or decreased according to actual needs to adapt to different test scenarios and needs.

[0080] like Figure 13 As shown, an embodiment of the present application provides an ATE test system, including a host computer system 210, a power supply system 220, and a test device 230 with an interlock circuit.

[0081] Among them, the host computer system 210 performs logical control of the test board in the test device 230 with an interlock circuit according to the detection results of the test device 230 with an interlock circuit; the power supply system 220 performs power supply control of the test board in the test device 230 with an interlock circuit according to the detection results of the test device 230 with an interlock circuit.

[0082] It should be understood that the processing details of the test device with interlock circuit in the embodiment of the present application can be referred to Figures 1-12 The related descriptions of the illustrated embodiment and related extended embodiments will not be repeated in the embodiments of this application.

[0083] It should be noted that the embodiments described in this application are only a part of the embodiments of this application, rather than all of the embodiments. The components of the embodiments of the present application generally described and shown in the accompanying drawings can be arranged and designed in various different configurations. Therefore, the above detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the application for protection, but merely represents selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of this application.

[0084] The words "first, second, third, etc." or module A, module B, module C and other similar terms in the specification and claims are only used to distinguish similar objects and do not represent a specific ordering of the objects. It is understandable that the specific order or sequence can be interchanged where permitted so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0085] In the above description, the numbers representing the steps involved do not necessarily mean that the steps must be executed. Intermediate steps may also be included or replaced by other steps. If permitted, the order of the previous and next steps may be interchanged or executed simultaneously.

[0086] The term "comprising" as used in the specification and claims should not be construed as limiting to what is listed thereafter; it does not exclude other elements or steps. Thus, it should be interpreted as specifying the presence of the features, integers, steps, or components mentioned, but not excluding the presence or addition of one or more other features, integers, steps, or components, or groups thereof. Thus, the expression "a device comprising means A and B" should not be limited to a device consisting solely of components A and B.

[0087] The term "one embodiment" or "an embodiment" mentioned in this specification means that the specific features, structures, or characteristics described in conjunction with the embodiment are included in at least one embodiment of the present application. Therefore, the phrases "in one embodiment" or "in an embodiment" appearing in various places in this specification do not necessarily refer to the same embodiment, but may refer to the same embodiment. In addition, in the various embodiments of the present application, unless otherwise specified or there is a logical conflict, the terms and / or descriptions between different embodiments are consistent and can be referenced to each other. The technical features in different embodiments can be combined to form new embodiments based on their inherent logical relationships.

[0088] Note that the above are only preferred embodiments of the present application and the technical principles employed. Those skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, and substitutions can be made by those skilled in the art without departing from the scope of protection of the present application. Therefore, although the present application has been described in more detail through the above embodiments, the present application is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the scope of protection of the present application, all of which fall within the scope of protection of the present application.

Claims

1. A test device with an interlock circuit, characterized in that: It includes a control board and several electrically connected test boards, wherein the control board is provided with an interlock circuit, and at least three corners of each test board are respectively provided with at least one first detection point; The interlock circuit includes an isolated power supply and an isolated ground. The isolated power supply is connected to the first output terminal through a first driver chip, and the isolated ground is connected to the first input terminal. The interlock circuit is connected in series with the first detection points of the plurality of test boards through the first output terminal and then connected back to the first input terminal to form a closed first detection circuit for detecting whether the electrical connections of the plurality of test boards are normal. The driving end of the first driving chip is connected to the power switch of the system, and drives the power switch to be turned on or off according to the detection result of the first detection circuit, so as to control the power supply of the system to the test board.

2. The device according to claim 1, characterized in that The output side of the first driver chip of the interlock circuit is connected in parallel with at least one switch module, and the output end of the switch module is connected in parallel with several extended interlock circuits. The first driver chip realizes interlock control of several extended interlock circuits by controlling the conduction or disconnection of the switch module.

3. The device according to claim 1, characterized in that The first output terminal and the first input terminal of the interlock circuit are connected in parallel with a first shielding switch circuit for realizing short-circuit control of the first detection loop.

4. The device according to claim 3, characterized in that The control board is also provided with a microprocessor, which is used to store the switch state of the first shielding switch circuit and / or the detection result or short-circuit state of the first detection loop, so that the system can perform logical control of the test board according to the switch state and / or detection result or short-circuit state.

5. The device according to claim 4, characterized in that The first shielding switch circuit includes a first switch with two normally open contacts connected in parallel to the first output end and the first input end of the interlock circuit, wherein one normally open contact is used to implement short-circuit control of the first detection circuit, and the other normally open contact is used to output the switching state of the first switch to the microprocessor.

6. The device according to claim 4, characterized in that The first shielding switch circuit includes a first driving circuit and a first isolation circuit; The input end of the first driving circuit is connected to the output end of the microprocessor, the output end of the first driving circuit is connected to the input end of the first isolation circuit, and the output end of the first isolation circuit is connected to the first output end of the interlock circuit and the isolation ground respectively; The microprocessor controls the first drive circuit to be turned on, so as to turn on the first isolation circuit, thereby achieving short-circuit control of the first detection loop.

7. The device according to claim 1, characterized in that It also includes an explosion-proof shell disposed on top of the plurality of test boards, wherein at least one second detection point is respectively disposed on at least two opposite corners of the explosion-proof shell and each test board; The isolated power supply of the interlock circuit is connected to the second output terminal through the second driver chip and is isolatedly connected to the second input terminal. The interlock circuit is connected in series with several test boards and the second detection point of the explosion-proof shell through the second output terminal and then connected back to the second input terminal to form a closed second detection circuit for detecting whether the explosion-proof shell is properly covered; The second input terminal is connected to the power control circuit of at least one of the test boards through a trigger circuit, and the trigger circuit controls the switching state of the power control circuit of the test board according to the high and low levels output by the second output terminal.

8. The device according to claim 7, characterized in that The second output terminal and the second input terminal of the interlock circuit are connected in parallel with a second shielding switch circuit for implementing short-circuit control of the second detection loop.

9. The device according to claim 8, characterized in that The control board is also provided with a microprocessor, which is used to store the switch state of the second shielding switch circuit and / or the detection result or short-circuit state of the second detection loop, so that the system performs logical control of the test board according to the switch state and / or detection result or short-circuit state.

10. The device according to claim 8, characterized in that The second shielding switch circuit includes a second switch connected in parallel to the second output terminal and the second input terminal of the interlock circuit, and the second switch is used to implement short-circuit control of the second detection loop.

11. The device according to claim 9, characterized in that The second shielding switch circuit includes a second driving circuit and a second isolation circuit; The input end of the second driving circuit is connected to the output end of the microprocessor, the output end of the second driving circuit is connected to the input end of the second isolation circuit, and the output end of the second isolation circuit is connected to the second output end of the interlock circuit and the isolation ground respectively; The microprocessor controls the second driving circuit to be turned on, so as to turn on the second isolation circuit, thereby achieving short-circuit control of the second detection loop.

12. The device according to claim 1, characterized in that A plurality of switch modules are further connected in series between the first input terminal of the interlock circuit and the isolation ground. The plurality of switch modules are used to connect at least one external device to implement interlocking control between the interlock circuit and the external device.

13. An ATE test system, characterized in that: A test device comprising a host computer system, a power supply system, and a test device with an interlock circuit according to any one of claims 1 to 12; The host computer system performs logic control on the test board in the test device with the interlock circuit according to the detection result of the test device with the interlock circuit; The power supply system controls power supply to a test board in the test device with the interlock circuit according to a detection result of the test device with the interlock circuit.

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