Stacked chip packaging structure

Abstract

The utility model provides a stacked chip packaging structure. According to the stacked chip packaging structure, a groove is formed in the top face of a substrate, a first chip is installed in the groove, the first chip is a flip chip and is provided with a front face and a back face which are opposite, the front face of the first chip faces the substrate, a second chip is installed on the back face of the first chip in a stacked mode, and the width of the first chip and the width of the second chip are both smaller than the width of the groove. The plastic package body is located on the top surface of the substrate and wraps the first chip and the second chip, and the groove is filled with the plastic package body. Therefore, the height of the stacked chip packaging structure can be reduced, and the packaging reliability of the stacked chip packaging structure can be improved.

Description

Technical Field

[0001] The utility model relates to the technical field of packaging, in particular to a stacked chip packaging structure. Background Art

[0002] Currently, electronic devices are becoming increasingly miniaturized, placing higher demands on the miniaturization of each packaging module. To reduce the lateral width of the packaging structure, stacked die technology is commonly used, but this approach increases the vertical height of the packaging structure. Reducing the height of the stacked die packaging structure and improving its packaging reliability are urgent issues. Utility Model Content

[0003] One of the purposes of the present invention is to reduce the height of the stacked chip packaging structure and improve the packaging reliability of the stacked chip packaging structure.

[0004] In order to achieve the above-mentioned purpose, the present invention provides a stacked chip packaging structure including: a substrate, a top surface of which has a groove; a first chip, the first chip is installed in the groove, the first chip is a flip chip and has a relative front and back surface, and the front surface of the first chip faces the substrate; a second chip, the second chip is stacked and installed on the back surface of the first chip, the width of the first chip and the second chip are both smaller than the width of the groove; and a plastic package, the plastic package is located on the top surface of the substrate and wraps the first chip and the second chip, and the plastic package also fills the groove.

[0005] Optionally, the bottom surface of the groove has a first pad, the front surface of the first chip has a first bump, and the first bump is welded on the first pad.

[0006] Optionally, the stacked chip packaging structure further includes a bottom filler, which fills the gap between the first chip and the bottom surface of the groove, and the top surface of the bottom filler is lower than the back surface of the first chip and lower than the top surface of the substrate.

[0007] Optionally, the front side of the first chip has a plurality of first bumps, the spacing between the centers of two adjacent first bumps is greater than or equal to 100 μm, and the width of the first bump is less than or equal to 50 μm; the bottom filler includes filling particles, and the width of the filling particles is less than or equal to 40 μm.

[0008] Optionally, the second chip is a wire bonding type chip; the top surface of the substrate has a second pad, and the second pad is located outside the groove; the surface of the second chip away from the first chip is connected to the second pad through a bonding wire.

[0009] Optionally, the stacked chip packaging structure includes a plurality of second chips, and the plurality of second chips are stacked from bottom to top and mounted on the back side of the first chip, and the widths of the plurality of second chips decrease sequentially from bottom to top.

[0010] Optionally, for two adjacent second chips, on the same side of the stacked chip packaging structure, a distance between an edge of the second chip in the upper layer and an edge of the second chip in the lower layer is greater than or equal to 250 μm.

[0011] Optionally, the first chip has a silicon through-hole via that passes through the first chip; the second chip is a flip chip, the second chip is mounted on the back side of the first chip, and the front side of the second chip has a second bump, and the second bump is in contact with the silicon through-hole via of the first chip.

[0012] Optionally, the stacked chip packaging structure includes a plurality of second chips stacked in sequence on the back side of the first chip, each of the second chips having a through silicon via running through the chip and each of the second chips having a second bump on the front side, and for two adjacent second chips, the second bump of the upper second chip contacts the through silicon via of the lower second chip.

[0013] Optionally, the stacked chip packaging structure includes a plurality of the first chips, and the plurality of the first chips are all mounted in the groove and in contact with the bottom surface of the groove.

[0014] In the stacked chip packaging structure provided by the present invention, a groove is provided on the top surface of the substrate, and a first chip is installed in the groove. The first chip is a flip chip and has a relative front and back surface. The front surface of the first chip faces the substrate, and the second chip is stacked and installed on the back surface of the first chip. The widths of the first chip and the second chip are both smaller than the width of the groove. The plastic package is located on the top surface of the substrate and wraps the first chip and the second chip. The plastic package also fills the groove. In this way, installing the first chip in the groove of the substrate can reduce the height of the stacked chip packaging structure, and the plastic package starts to plastic-seal the first chip and the second chip from the groove, which helps to improve the packaging reliability of the stacked chip packaging structure.

[0015] Furthermore, the stacked chip packaging structure also includes a bottom filler, which fills the gap between the first chip and the bottom surface of the groove. The top surface of the bottom filler is lower than the back surface of the first chip and lower than the top surface of the substrate. The provision of the bottom filler can prevent the first chip from tipping over or tilting when bonding on a second chip of the wire bonding type, thereby improving the reliability of the connection between the first chip and the substrate, or preventing the bumps of the first chip from being oxidized when the second chip of the flip-chip type is mounted. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a cross-sectional schematic diagram of the stacked chip packaging structure provided in Example 1 of the present invention.

[0017] Figures 2 to 4 This is a schematic diagram of the packaging process structure of the stacked chip packaging structure provided in Example 1 of the present invention.

[0018] Figure 5 This is a cross-sectional schematic diagram of the stacked chip packaging structure provided in the second embodiment of the present invention.

[0019] Figures 6 and 7 This is a schematic diagram of the packaging process structure of the stacked chip packaging structure provided in the second embodiment of the present invention.

[0020] Figure 8 This is a cross-sectional schematic diagram of the stacked chip packaging structure provided in the third embodiment of the present invention.

[0021] Figures 9 and 10 This is a schematic diagram of the packaging process structure of the stacked chip packaging structure provided in Example 3 of the present utility model.

[0022] Figure 11 This is a cross-sectional schematic diagram of the stacked chip packaging structure provided in Example 4 of the present utility model.

[0023] Explanation of the reference numerals: 10 - substrate; 101 - first pad; 102 - second pad; 103 - third pad; 104 - internal routing; 105 - isolation medium; 106 - solder resist layer; 107 - groove; 21 - first chip; 211 - first bump; 22 - second chip; 221 - second bump; 200 - through silicon via; 30 - bonding wire; 40 - plastic package; 50 - bottom filler. DETAILED DESCRIPTION

[0024] In order to reduce the height of the stacked chip packaging structure and improve the packaging reliability of the stacked chip packaging structure, in the stacked chip packaging structure proposed by the present invention, the top surface of the substrate has a groove, the first chip which is a flip chip is installed in the groove, and the second chip is stacked and installed on the first chip. In this way, the height of the stacked chip packaging structure can be reduced, and the widths of the first chip and the second chip are both smaller than the width of the groove, so that the plastic package can be filled in the groove, and the plastic package can start to plastic-encapsulate the first chip and the second chip from the groove, which helps to improve the packaging reliability of the stacked chip packaging structure.

[0025] The stacked chip package structure proposed by the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present invention.

[0026] It should be noted that, in the description of the present application, the terms "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "top", "bottom", "inside", "outside", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the structure referred to must have a specific orientation or be constructed in a specific orientation. Therefore, it cannot be understood as a limitation on the present application. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more features. In the description of the present application, "multiple" means two or more, and at least one means one, two or more, unless otherwise clearly and specifically defined.

[0027] Example 1

[0028] Figure 1 This is a cross-sectional diagram of a stacked chip packaging structure provided by the first embodiment of the present invention. Figure 1 As shown, the stacked chip package structure includes a substrate 10, a first chip 21, a second chip 22, and a plastic package 40. The top surface of the substrate 10 has a groove 107. The first chip 21 is mounted in the groove 107. The first chip 21 is a flip chip and has opposite front and back surfaces, with the front surface of the first chip 21 facing the substrate 10. The second chip 22 is stacked and mounted on the back surface of the first chip 21. The widths of the first chip 21 and the second chip 22 are both smaller than the width of the groove 107. The plastic package 40 is located on the top surface of the substrate 10 and encapsulates the first chip 21 and the second chip 22. The plastic package 40 also fills the groove 107.

[0029] Specifically, refer to Figure 1As shown, a first solder pad 101 and a second solder pad 102 can be formed on the top surface of the substrate 10, the first solder pad 101 is located on the bottom surface of the groove 107, and the second solder pad 102 is located outside the groove 107. A third solder pad 103 can be formed on the bottom surface of the substrate 10. The interior of the substrate 10 has an internal routing 104, and the number of layers of the internal routing 104 can be single-layer or multi-layer. The multi-layer internal routing 104 can be interconnected through conductive holes, and the internal routing 104 is also electrically connected to the first solder pad 101, the second solder pad 102 and the third solder pad 103. The substrate 10 also includes an isolation medium 105, which isolates adjacent internal routings 104 and covers at least part of the top internal routing and part of the bottom internal routing. The top and bottom surfaces of the substrate 10 can be formed with a solder resist layer 106, and the solder pads on the top and bottom surfaces of the substrate 10 are exposed from the solder resist layer 106.

[0030] In this embodiment, the number of the first pad 101 , the second pad 102 and the third pad 103 can be multiple.

[0031] refer to Figure 1 As shown, the first chip 21 is a flip chip (FC) having opposite front and back sides, with the front side of the first chip 21 facing the substrate 10. The front side of the first chip 21 has a first bump 211, which is soldered to the first pad 101.

[0032] In this embodiment, the front surface of the first chip 21 has a plurality of first bumps 211, and the bottom surface of the groove 107 has a plurality of first pads 101, and the first bumps 211 are welded to the corresponding first pads 101. Figure 1 As shown, due to the support of the first bumps 211, there is a gap between the first chip 21 and the bottom surface of the groove 107. Exemplarily, the first bumps 211 can be solder balls or copper pillars.

[0033] refer to Figure 1 As shown, in this embodiment, the second chip 22 is a wire bonding (WB) type chip, and the back surface of the second chip 22 is adhered to the back surface of the first chip 21. The width of the first chip 21 and the second chip 22 are both smaller than the width of the groove 107, which facilitates the filling of the molding compound of the molding body 40 into the groove 107.

[0034] In this embodiment, the surface of the second chip 22 away from the first chip 21 (i.e., the front surface of the second chip 22) is connected to the second pad 102 on the top surface of the substrate 10 via a bonding wire 30. Specifically, the front surface of the second chip 22 may have a chip pad (not shown in the figure), and the chip pad is electrically connected to the second pad 102 via the bonding wire 30.

[0035] Taking the second chip 22 as a rectangular chip as an example, chip pads can be provided on all four sides of the front surface of the second chip 22, and multiple second pads 102 can be arranged around the groove 107, so as to facilitate the bonding wires 30 to connect the chip pads of the second chip 22 to the corresponding second pads 102. In some embodiments, chip pads can also be arranged on one side, two sides, or three sides of the front surface of the second chip 22, and the multiple second pads 102 are distributed according to the arrangement of the chip pads.

[0036] For example, the bonding wire 30 may be a gold wire, a silver wire, a copper wire, an aluminum wire, or the like.

[0037] In some embodiments of the present application, the stacked chip packaging structure includes a plurality of second chips 22, all of which are wire-bonded type chips, and the plurality of second chips 22 are stacked from bottom to top on the back of the first chip 21; for two adjacent second chips 22, the back of the upper second chip 22 can be adhered to the front of the lower second chip using resin glue or the like, wherein the width of the plurality of second chips 22 decreases from bottom to top so as to expose the bonding area of ​​each second chip 22. Exemplarily, for two adjacent second chips 22, on the same side of the stacked chip packaging structure, the spacing between the edge of the upper second chip 22 and the edge of the lower second chip 22 is greater than or equal to 250μm, so that a sufficiently wide bonding area can be reserved for the lower second chip, and the resin glue can be prevented from contaminating the chip pads used for bonding of the lower second chip, thereby reducing the problem of poor bonding.

[0038] It should be noted that the number of second chips 22 stacked on the first chip 21 can be selected according to actual needs and is not limited in this application.

[0039] refer to Figure 1 As shown, the plastic package 40 is located on the top surface of the substrate 10 and wraps the first chip 21 and the second chip 22. The plastic package 40 also fills the groove 107. In this embodiment, the plastic package 40 fills the gap between the first chip 21 and the bottom surface of the groove 107, covers the first chip 21 and the second chip 22, and also covers the bonding wires 30 above the second chip 22.

[0040] In this embodiment, Figure 1 As shown, the stacked chip package structure includes a first chip 21. However, in other embodiments, the stacked chip package structure may include multiple first chips 21, each of which is mounted in the groove 107 and contacts the bottom surface of the groove 107, and each of the first chips 21 may be stacked with a second chip 22 as needed.

[0041] In this embodiment, the stacked chip package structure may further include other electronic components (not shown in the figure), which may be mounted on the top surface of the substrate 10 and outside the recess 107. The other electronic components may include passive devices and / or chips, and the passive devices may include but are not limited to resistors and capacitors.

[0042] This embodiment also provides a method for manufacturing the stacked chip packaging structure. Figures 2 to 4 This is a schematic diagram of the packaging process of the stacked chip packaging structure provided by the first embodiment of the present invention. Figure 1 、 Figures 2 to 4 The manufacturing method of the stacked chip packaging structure provided in this embodiment is described.

[0043] Specifically, the manufacturing method of the stacked chip packaging structure may include: Figure 2 As shown, a substrate 10 is provided, and the top surface of the substrate 10 has a groove 107; Figure 3 As shown, the first chip 21 is mounted face down in the groove 107; Figure 4 As shown, the second chip 22 is mounted on the back of the first chip 21, wherein the back of the second chip 22 can be attached to the back of the first chip 21; a wire bonding process is performed to form a plurality of bonding wires 30, and the plurality of bonding wires 30 connect the second chip 22 and the corresponding second pads 102 on the top surface of the substrate 10; Figure 1 As shown, a plastic package 40 is formed on the top surface of the substrate 10 . The plastic package 40 fills the groove 107 and wraps the first chip 21 and the second chip 22 starting from the bottom of the first chip 21 .

[0044] It should be noted that when the stacked chip packaging structure includes multiple second chips 22 , after the first chip 21 is installed in the groove 107 , the multiple second chips 22 can be stacked and installed on the first chip 21 in sequence to form a plastic package 40 .

[0045] Example 2

[0046] Figure 5 This is a cross-sectional diagram of a stacked chip packaging structure provided by the second embodiment of the present invention. Figure 5 As shown, the stacked chip packaging structure provided by the second embodiment is different from that of the first embodiment in that the bottom of the first chip 21 has an underfill 50. For the similarities between the second embodiment and the first embodiment, reference can be made to the first embodiment.

[0047] Specifically, such as Figure 5 As shown, the stacked chip packaging structure includes a substrate 10 , a first chip 21 , a second chip 22 , a plastic package 40 and an underfill 50 .

[0048] The top surface of the substrate 10 has a groove 107 .

[0049] The first chip 21 is mounted in the groove 107 . The first chip 21 is a flip chip and has a front side and a back side facing each other. The front side of the first chip 21 faces the substrate 10 .

[0050] The second chip 22 is stacked and mounted on the back side of the first chip 21 . The widths of the first chip 21 and the second chip 22 are both smaller than the width of the groove 107 .

[0051] The plastic package body 40 is located on the top surface of the substrate 10 and wraps the first chip 21 and the second chip 22 . The plastic package body 40 also fills the groove 107 .

[0052] The underfill 50 fills the gap between the first chip 21 and the bottom surface of the groove 107 . The top surface of the underfill 50 is lower than the back surface of the first chip 21 and lower than the top surface of the substrate 10 .

[0053] In this embodiment, Figure 5 As shown, the underfill 50 completely covers the bottom surface of the groove 107, and the plastic encapsulation body 40 is located above the underfill 50. In other embodiments, the underfill 50 fills the gap between the first chip 21 and the bottom surface of the groove 107 but does not completely cover the bottom surface of the groove 107. There may also be a gap between the underfill 50 and the sidewalls of the groove 107, and the plastic encapsulation body 40 may cover the sidewalls of the underfill 50.

[0054] Exemplary, reference Figure 5 As shown, the front surface of the first chip 21 may have a plurality of first bumps 211 , the distance between the centers of two adjacent first bumps 211 (ie, the pitch of the first bumps 211 ) is greater than or equal to 100 μm, and the width of the first bumps 211 is less than or equal to 50 μm.

[0055] In this embodiment, the main component of the underfill 50 may be epoxy resin. The underfill 50 may further include filler particles. The width of the filler particles may be smaller than the spacing between the first bumps 211. For example, the width of the filler particles may be less than or equal to 40 μm. This facilitates the underfill 50 to flow smoothly into the gaps between the first bumps 211 and completely fill the gap between the first chip 21 and the bottom surface of the groove 107. This helps improve the reliability of the stacked chip packaging structure.

[0056] In this embodiment, the width of the filling particles in the underfill 50 is smaller than the width of the filling particles in the plastic package 40 .

[0057] In this embodiment, the second chip 22 is a wire bonding type chip. Since a large bonding pressure needs to be applied when bonding the second chip 22, the bottom filler 50 is filled at the bottom of the first chip 21. This can prevent the first chip 21 from tipping over or tilting when bonding the second chip 22, and avoid the solder joints between the first chip 21 and the bottom surface of the groove 107 from cracking or even breaking, thereby improving the reliability of the connection between the first chip 21 and the substrate 10.

[0058] Figures 6 and 7 The packaging process structure diagram of the stacked chip packaging structure provided by the second embodiment of the present invention. The packaging structure of the stacked chip packaging structure of the second embodiment includes: Figure 6 As shown, a substrate 10 is provided, and a groove 107 is formed on the top surface of the substrate 10; a first chip 21 is mounted face down in the groove 107; an underfill 50 is filled at the bottom of the first chip 21, and the underfill 50 fills the gap between the first chip 21 and the bottom surface of the groove 107, wherein the underfill 50 can be formed by, but not limited to, dispensing; Figure 7 As shown, the second chip 22 is mounted on the back of the first chip 21, wherein the back of the second chip 22 can be attached to the back of the first chip 21; a wire bonding process is performed to form a plurality of bonding wires 30, and the plurality of bonding wires 30 connect the front of the second chip 22 and the corresponding second pads 102 on the top surface of the substrate 10; Figure 5 As shown, a plastic package 40 is formed on the top surface of the substrate 10 . The plastic package 40 fills the groove 107 and wraps the first chip 21 and the second chip 22 .

[0059] Example 3

[0060] The stacked chip packaging structure provided by the third embodiment is different from that of the first embodiment in that the second chip is a flip chip. The differences with the first embodiment can be referred to in the first embodiment.

[0061] Figure 8 This is a cross-sectional diagram of a stacked chip packaging structure provided by the third embodiment of the present invention. Figure 8 As shown, in this embodiment, the second chip 22 is a flip chip, and the front side of the second chip 22 is mounted on the back side of the first chip 21 with the front side facing down. The first chip 21 has a through-silicon via 200 that passes through the first chip 21, and the front side of the second chip 22 has a second bump 221. The second bump 221 is in contact with the through-silicon via 200 of the first chip 21, so that the second chip 22 can realize electrical signal interconnection between the second chip 22 and the first chip 21 and electrical signal interconnection between the second chip 22 and the substrate 10 through the second bump 221 and the through-silicon via in the first chip 21.

[0062] Exemplarily, the first chip 21 has a plurality of through-silicon vias 200 passing through the first chip 21 , and each through-silicon via 200 is connected to a first bump 211 on the front surface of the first chip 21 at an end portion on the front surface of the first chip 21 .

[0063] In some embodiments, the stacked chip packaging structure may include a plurality of second chips 22 stacked in sequence on the back side of a first chip 21, each second chip 22 having a through silicon via 200 running through the chip and each second chip 22 having a second bump 221 on the front side. For two adjacent second chips 22, the second bump 221 of the upper second chip 22 contacts the through silicon via 200 of the lower second chip 22, so that electrical signal interconnection between the stacked chips can be achieved through the through silicon via.

[0064] Figures 9 and 10 The packaging process structure diagram of the stacked chip packaging structure provided by the third embodiment of the present invention. The packaging structure of the stacked chip packaging structure of the third embodiment includes: Figure 9 As shown, a substrate 10 is provided, and a groove 107 is formed on the top surface of the substrate 10; the first chip 21 is mounted face down in the groove 107; Figure 10 As shown, the second chip 22 is mounted on the back of the first chip 21, wherein the second chip 22 can be mounted on the back of the first chip 21 by surface mounting technology (SMT); Figure 8 As shown, a plastic package 40 is formed on the top surface of the substrate 10 . The plastic package 40 fills the groove 107 and wraps the first chip 21 and the second chip 22 starting from the bottom of the first chip 21 .

[0065] It should be noted that when the stacked chip packaging structure includes multiple second chips 22 , after the first chip 21 is installed in the groove 107 , the multiple second chips 22 can be stacked and installed on the first chip 21 in sequence to form a plastic package 40 .

[0066] Example 4

[0067] The stacked chip packaging structure provided by the fourth embodiment is different from that of the third embodiment in that a bottom filler is formed at the bottom of the first chip. The similarities between the fourth embodiment and the first to third embodiments can be found in the above description.

[0068] Figure 11 This is a cross-sectional diagram of a stacked chip packaging structure provided by the fourth embodiment of the present invention. Figure 11As shown, the stacked chip packaging structure provided in this embodiment includes a bottom filler 50, which fills the gap between the first chip 21 and the bottom surface of the groove 107. The top surface of the bottom filler 50 is lower than the back surface of the first chip 21 and lower than the top surface of the substrate 10.

[0069] In this embodiment, Figure 11 As shown, the underfill 50 completely covers the bottom surface of the groove 107, and the plastic encapsulation body 40 is located above the underfill 50. In other embodiments, the underfill 50 fills the gap between the first chip 21 and the bottom surface of the groove 107 but does not completely cover the bottom surface of the groove 107. There may also be a gap between the underfill 50 and the sidewalls of the groove 107, and the plastic encapsulation body 40 may cover the sidewalls of the underfill 50.

[0070] In this embodiment, Figure 11 As shown, the second chip 22 is a flip chip, and the second chip 22 can be soldered to the back of the first chip 21 using surface mounting technology. Specifically, when installing the second chip 22, solder paste is first printed on the back of the first chip 21, and then the second chip 22 is aligned and placed on the back of the first chip 21. Then, a reflow process is performed so that the second bumps 221 on the front of the second chip 22 are soldered to the back of the first chip 21. It should be noted that in this embodiment, filling the bottom of the first chip 21 with an underfill 50 before installing the second chip 22 can prevent the first bumps 211 of the first chip 21 from oxidizing when the flip-chip second chip 22 is mounted. It can also prevent the first bumps 211 of the first chip 21 from melting again when the flip-chip second chip 22 is mounted, thereby preventing interconnect short circuits.

[0071] The above description is only a description of the preferred embodiment of the present invention, and does not limit the scope of rights of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the scope of protection of the technical solution of the present invention.

Claims

1. A stacked chip packaging structure, characterized in that: include: a substrate, wherein a top surface of the substrate has a groove; a first chip, the first chip being mounted in the groove, the first chip being a flip chip and having opposite front and back surfaces, the front surface of the first chip facing the substrate; a second chip, the second chip being stacked and mounted on the back side of the first chip, wherein the widths of the first chip and the second chip are both smaller than the width of the groove; as well as A plastic package is located on the top surface of the substrate and wraps the first chip and the second chip. The plastic package also fills the groove.

2. The stacked chip packaging structure according to claim 1, wherein: The bottom surface of the groove has a first pad, the front surface of the first chip has a first bump, and the first bump is welded on the first pad.

3. The stacked chip packaging structure according to claim 2, wherein: The invention further includes an underfill material, which fills a gap between the first chip and the bottom surface of the groove. The top surface of the underfill material is lower than the back surface of the first chip and lower than the top surface of the substrate.

4. The stacked chip packaging structure according to claim 3, wherein: The front of the first chip has multiple first bumps, the distance between the centers of two adjacent first bumps is greater than or equal to 100μm, and the width of the first bump is less than or equal to 50μm; the bottom filler includes filling particles, and the width of the filling particles is less than or equal to 40μm.

5. The stacked chip packaging structure according to claim 1, wherein: The second chip is a wire-bonded chip; the top surface of the substrate has a second pad, and the second pad is located outside the groove; the surface of the second chip away from the first chip is connected to the second pad via a bonding wire.

6. The stacked chip packaging structure according to claim 5, wherein: The stacked chip packaging structure includes a plurality of second chips, which are stacked from bottom to top and mounted on the back side of the first chip, and the widths of the plurality of second chips decrease sequentially from bottom to top.

7. The stacked chip packaging structure according to claim 6, wherein: For two adjacent second chips, on the same side of the stacked chip packaging structure, a distance between an edge of the second chip in the upper layer and an edge of the second chip in the lower layer is greater than or equal to 250 μm.

8. The stacked chip packaging structure according to claim 1, wherein: The first chip has a through-silicon via that passes through the first chip; the second chip is a flip chip, the second chip is mounted on the back side of the first chip, and the front side of the second chip has a second bump that contacts the through-silicon via of the first chip.

9. The stacked chip packaging structure according to claim 8, wherein: The stacked chip packaging structure includes a plurality of second chips stacked in sequence on the back side of the first chip, each of the second chips has a through silicon via running through the chip and each of the second chips has a second bump on the front side, and for two adjacent second chips, the second bump of the upper second chip contacts the through silicon via of the lower second chip.

10. The stacked chip package structure according to claim 1, wherein: The stacked chip packaging structure includes a plurality of the first chips, and the plurality of the first chips are all mounted in the groove and in contact with the bottom surface of the groove.

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