Power MOS packaging structure

Abstract

The utility model provides a power MOS packaging structure. The power MOS packaging structure comprises a chip; a source pin, a gate pin and a drain pin; the packaging framework is wrapped outside the chip, the source electrode pin, the grid electrode pin and the drain electrode pin; the first bonding wire is connected with the drain electrode pin and the chip; the packaging frame is internally provided with an independent cavity, and at least one part of the bonding wire is located in the cavity. According to the MOS packaging structure provided by the utility model, because the bonding wire is located in the independent cavity, enough space is provided for accommodating the fused bonding wire, the phenomenon that the bonding wire is electrically connected again after being fused is avoided, and the safety of electric connection of the MOS packaging structure is integrally improved.

Description

Technical Field

[0001] The present invention relates to a power semiconductor product, in particular to a power MOS packaging structure. Background Art

[0002] MOS transistors (MOSFETs), short for Metal Oxide Semiconductor Field Effect Transistor, are commonly used in high-power switching circuits to control the on / off state of the circuit. However, in practice, they can fail due to breakdown. This often causes an internal short-circuit, resulting in excessive short-circuit current and sustained, intense heating, leading to burnout. In severe cases, they can even cause flames, posing a safety hazard. This is especially true when MOS transistors are installed on a printed circuit board (PCB) and form a complete circuit system with other components. A MOS transistor's combustion could potentially cause other components in the system to ignite, paralyzing the entire system.

[0003] In the new energy industry, power MOS transistors (MOSs) are commonly used as switch controls in the main circuit, with two MOS transistors connected in series to control the battery's charging and discharging processes, respectively. During the power MOS manufacturing process, after wire bonding, the MOS chip and bonding wires must be encapsulated to protect the chip structure from external impact.

[0004] Currently, the market primarily utilizes a molding process to encapsulate MOS chips. This process utilizes epoxy molding compound, a mixture of thermosetting resin and various inorganic materials. This material is then encapsulated around components such as the chip and leads to protect them from external physical and chemical damage. The package can be customized to the desired size or shape based on actual needs. However, in existing technologies, the bonding wires are completely encapsulated within the epoxy resin. While epoxy encapsulation provides adequate protection for the chip and bonding wires within the MOS, the bonding wires are susceptible to cooling after a MOS short circuit and subsequent melting. This can lead to the bonding wires reconnecting electrically, potentially preventing the main circuit within the MOS from being fully disconnected. This poses a risk of short circuiting the MOS and further impacting the safety performance of the entire battery. Utility Model Content

[0005] In order to solve the problem in the prior art that the bonding wires in the MOS packaging structure are easily reconnected after melting and cannot disconnect the main circuit, the utility model provides a power MOS packaging structure, including:

[0006] A chip; a source pin, a gate pin, and a drain pin; a packaging frame wrapped around the chip and the source pin, the gate pin, and the drain pin; a first bonding wire connecting the drain pin and the chip; an independent cavity is provided in the packaging frame, and at least a portion of the bonding wire is located in the cavity.

[0007] Furthermore, the first bonding wires are configured as a plurality of wires.

[0008] Furthermore, a second bonding wire is provided, and the second bonding wire connects the gate pin and the chip.

[0009] Furthermore, at least a portion of the second bonding wire is also located in the cavity.

[0010] Furthermore, most of the bonding wire is located in the cavity.

[0011] Furthermore, the number of the chips is set to 2.

[0012] Furthermore, the chip and the source pin are electrically connected via a copper sheet.

[0013] Furthermore, a plurality of source pins are provided, and the plurality of source pins are provided on the same side.

[0014] Furthermore, the packaging frame is made of epoxy resin.

[0015] Furthermore, a plurality of cavities are provided.

[0016] Since the bonding wires of the MOS packaging structure of the present invention are located in an independent cavity, there is enough space to accommodate the bond wires after they are fused. The bonding wires will not be electrically reconnected after being fused, thereby improving the safety of the electrical connection of the MOS packaging structure as a whole. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is an external schematic diagram of the power MOS packaging structure of the utility model;

[0018] Figure 2 This is a schematic diagram of the internal cross-section of the power MOS packaging structure of the present invention;

[0019] Figure 3 A schematic cross-sectional view of the power MOS package structure of the present invention from another angle;

[0020] Figure 4 This is a schematic diagram of the internal structure of the power MOS packaging structure of the utility model. DETAILED DESCRIPTION

[0021] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0022] like Figure 1-4 As shown, an embodiment of the present invention provides a power MOS package structure, including a first chip 201, a second chip 202, a first source pin 7 and a second source pin 8 of the first chip 201; a gate pin 1 of the first chip 201, a drain pin 2 of the first chip 201; a first source pin 5 and a second source pin 6 of the second chip 202, and a gate pin 4 and a drain pin 3 of the second chip 202. The MOS package structure also includes a package frame 10 disposed outside the first chip 201 and the second chip 202. The package frame 10 encapsulates a portion of a plurality of source pins (5, 6, 7, 8), a plurality of gate pins (1, 4), and a plurality of drain pins (2, 3) within the package frame 10. At the same time, a portion of the gate pins, the drain pins, and the source pins are exposed outside the package frame 10 to facilitate electrical connection with external components when the MOS package structure is installed in a specific circuit. Inside the MOS package structure, the drain pin 2 of the first chip 201 is connected to the first chip 201 via multiple first bonding wires 301, and the first chip 201 is connected to the gate pin 1 of the first chip via a second bonding wire 302. The first chip 201 is connected to the source pins (7, 8) of the first chip via a copper sheet. The drain pin 3 of the second chip 202 is connected to the second chip 202 via multiple first bonding wires 301; the gate pin 4 of the second chip 202 is connected to the second chip 202 via a second bonding wire 302. The second chip 202 is connected to the source pins (7, 8) of the second chip via a copper sheet.

[0023] like Figure 2As shown, in this embodiment, during the process of packaging the chips, pins, and other components within the MOS to form a MOS package structure, the first chip 201, the second chip 202, and each pin are encapsulated within a package structure made of epoxy resin. However, an independent cavity 101 is provided within the package structure 101 to accommodate the first and second bonding wires 301 and 302. After the power MOS is packaged, if the MOS fails due to overcurrent or other reasons, the first bonding wire 301 or the second bonding wire 302 will first fuse. Since the first and second bonding wires are located in an independent cavity, there is sufficient space to accommodate the bond wires after the fuse. After the fuse, the bond wires are disconnected first, thereby disconnecting the circuit and achieving the circuit protection function. The bond wires will not be squeezed due to limited space and reconnected at their original locations, which may cause the main circuit to be unable to disconnect and cause a short circuit. In this embodiment, since the bonding wire is first located in the cavity and a packaging structure is provided outside the cavity, the bonding wire is first supported by the packaging frame 10 after being blown and will not be displaced after being blown, thereby avoiding the problem of bonding wire misalignment.

[0024] In this embodiment, the number of first bonding wires is preferably set to 4, and the number of bonding wires is used to control the current threshold that can flow through the MOS. At the same time, the first bonding wire 301 and the second bonding wire 302 are simultaneously located in the same independent cavity, thereby simplifying the molding process of the MOS packaging structure. Optionally, in order to better ensure the stability of each bonding wire in the MOS packaging structure, two independent cavities can also be provided in the MOS packaging structure to accommodate the first bonding wire 301 and the second bonding wire 302 respectively. The first bonding wire and the second bonding wire can all be arranged in an independent cavity, or only most of the bonding wires can be located in the independent cavity, and the other small part can be located outside the cavity.

[0025] In this embodiment, two chips are provided. However, alternatively, only one, three, or even more chips may be provided. The number of chips is not limited. In this embodiment, the package frame is preferably made of epoxy resin, which has a simple molding process and low cost. However, optionally, in order to further improve the safety performance of the packaged MOS package structure and its performance under other extreme conditions such as high temperature, the package frame can also be made of ceramic material.

[0026] The above embodiments of the present invention are merely examples for the purpose of clearly illustrating the present invention and are not intended to limit the implementation methods of the present invention. A person skilled in the art will be able to make other variations or modifications based on the above description. It is not necessary and impossible to enumerate all implementation methods here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the claims of the present invention.

Claims

1. A power MOS packaging structure, comprising: chip; Source pin, gate pin and drain pin; A packaging frame, wrapping around the chip and the source pin, the gate pin, and the drain pin; A first bonding wire connects the drain pin and the chip; wherein an independent cavity is provided in the packaging frame, and at least a portion of the bonding wire is located in the cavity.

2. The MOS package structure according to claim 1, wherein: The first bonding wires are configured as a plurality of wires.

3. The MOS package structure according to claim 1, wherein: A second bonding wire is also provided, and the second bonding wire connects the gate pin and the chip.

4. The MOS package structure according to claim 3, wherein: At least a portion of the second bond wire is also located within the cavity.

5. The MOS package structure according to claim 1, wherein: A majority of the bond wire is located within the cavity.

6. The MOS package structure according to claim 1, wherein: The number of the chips is set to 2.

7. The MOS package structure according to claim 1, wherein: The chip is electrically connected to the source pin via a copper sheet.

8. The MOS package structure according to claim 1, wherein: There are multiple source pins, and the multiple source pins are arranged on the same side.

9. The MOS package structure according to claim 1, wherein: The packaging frame is made of epoxy resin.

10. The MOS package structure according to claim 1, wherein: There are multiple cavities.

Images