Substrate structure

Abstract

The present application discloses a substrate structure comprising: a core portion comprising a first through hole, the first through hole comprising an upper portion and a lower portion, a width of the upper portion tapering in a direction of the lower portion and a width of the lower portion tapering in a direction of the upper portion in a cross-sectional view; the dielectric layer covers the core part and extends to the inner side walls of the upper part and the lower part of the first through hole, and the thermal expansion coefficient of the core part is smaller than that of the dielectric layer; and the circuit layer is formed on the dielectric layer in the first through hole. The technical scheme at least provides a substrate structure which is provided with improved CTE and can be provided with a circuit layer of a thin circuit at the same time.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to a substrate structure. Background Art

[0002] In existing substrate structures, materials that have advantages in certain aspects have not been widely used because these materials may not be able to be used to form fine circuits. For example, ceramic substrates available on the market have the advantages of good heat dissipation, low CTE (coefficient of thermal expansion), strong rigidity and hardness based on the characteristics of ceramics. However, the problem that ceramic substrates have not been widely used is that the ceramic surface is relatively rough and it is impossible to make fine circuits smaller than L / S (line width / line spacing) = 36 / 40 microns. In particular, the metal of the through hole cannot be copper-plated when making the circuit pattern (because the surface is rough and the seed layer cannot be plated). Generally, the upper and lower layers are connected by filling with copper paste and then solder paste. Therefore, the filling may have incomplete coverage or hole-filling problems.

[0003] Currently, there is no way to improve the roughness of ceramic surfaces. The fundamental properties of the raw materials have limited the progress of circuit capabilities over the years, failing to meet market demand. Furthermore, the Dk / Df ratio of the material is much higher than that of currently available materials, resulting in design limitations that cannot keep up with market demand, ultimately inhibiting the application of ceramics. Utility Model Content

[0004] In response to the above problems, the present application proposes a substrate structure having an improved CTE and a circuit layer with fine circuits.

[0005] The technical solution of this application is achieved as follows:

[0006] According to one aspect of the present application, a substrate structure is provided, comprising: a core portion, comprising a first through hole, the first through hole comprising an upper portion and a lower portion, wherein, from a cross-sectional perspective, the width of the upper portion gradually decreases toward the lower portion, and the width of the lower portion gradually decreases toward the upper portion; a dielectric layer, covering the core portion and extending to the inner side walls of the upper portion and the lower portion of the first through hole, wherein the thermal expansion coefficient of the core portion is smaller than the thermal expansion coefficient of the dielectric layer; and a circuit layer, formed on the dielectric layer in the first through hole.

[0007] In some embodiments, the dielectric layer has a first surface roughness and the core has a second surface roughness, wherein the first surface roughness is less than the second surface roughness.

[0008] In some embodiments, the hardness of the core is greater than the hardness of the circuit layer.

[0009] In some embodiments, the core has a greater rigidity than the circuit layer.

[0010] In some embodiments, the dielectric layer extending to the inner side walls of the upper and lower portions of the first through hole defines an X-shaped second through hole, the width of the upper portion of the second through hole tapers toward the lower portion, and the width of the lower portion of the second through hole tapers toward the upper portion, and from a cross-sectional perspective, the second through hole has a first surface and a second surface relative to each other above the upper portion of the first through hole, wherein the first surface is not parallel to the second surface.

[0011] In some embodiments, the distance between the first surface and the second surface in the horizontal direction gradually decreases toward the lower portion.

[0012] In some embodiments, in a cross-sectional view, the second through hole has a third surface and a fourth surface opposite to each other below a lower portion of the first through hole, wherein the third surface is non-parallel to the fourth surface.

[0013] In some embodiments, in a cross-sectional perspective, relative to a center line of the second through hole, an inclination angle of the first surface is smaller than an inclination angle of the second surface.

[0014] In some embodiments, the circuit layer located in the first through hole defines a conductive through hole, and the upper and lower surfaces of the conductive through hole respectively have recesses.

[0015] In some embodiments, the circuit layer further extends onto the dielectric layer outside the first through hole.

[0016] In the above technical solution, for a core portion unsuitable for forming fine circuits, a dielectric layer is formed on the surface of the core portion and the inner sidewalls of the first through-hole, and then a circuit layer is formed on the dielectric layer. This solves the problem of not being able to directly form fine circuits on the core portion and the inner sidewalls of the first through-hole. When a material with a low CTE is used for the core portion of the substrate structure, fine circuits can also be formed on the substrate structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 FIG. 4 is a schematic cross-sectional view of a substrate structure according to an embodiment of the present application.

[0019] Figures 2A to 2H Schematic cross-sectional views of the method for forming a substrate structure of the present application at multiple stages.

[0020] Figure 3A and Figure 3Bis a schematic cross-sectional view of a first through hole in a core portion of a substrate structure according to another embodiment.

[0021] Figure 4A and Figure 4B 4 is a cross-sectional schematic diagram of a substrate structure during formation according to another embodiment of the present application.

[0022] Figures 5 to 7 It is a cross-sectional schematic diagram of a substrate structure according to another embodiment of the present application.

[0023] Figures 8A to 8L 1 is a schematic cross-sectional view of a method for forming a substrate structure according to another embodiment at multiple stages.

[0024] Figure 9 It is a cross-sectional schematic diagram of a substrate structure according to another embodiment of the present application. DETAILED DESCRIPTION

[0025] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of this application.

[0026] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements will be described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are in direct contact, and may also include an embodiment in which an additional component is formed between the first component and the second component so that the first component and the second component may not be in direct contact. Moreover, the present invention may repeatedly refer to numbers and / or letters in various examples. This repetition is merely for simplicity and clarity and does not in itself represent a relationship between the various embodiments and / or configurations discussed.

[0027] An embodiment of the present application provides a substrate structure. Figure 1 FIG is a schematic cross-sectional view of a substrate structure 100 according to an embodiment of the present application. Figure 1 As shown, substrate structure 100 may include a core 120 and a dielectric layer 140 covering core 120. The CTE of core 120 may be lower than the CTE of dielectric layer 140. Core 120 may include a first through hole 125, and dielectric layer 140 may extend to the inner sidewall of first through hole 125. Dielectric layer 140 may be made of any suitable material suitable for forming circuits thereon.

[0028] Specifically, the first through hole 125 may include an upper portion 125t and a lower portion 125b. Figure 1 In the cross-sectional view shown, the width of the upper portion 125t tapers toward the lower portion 125b, and the width of the lower portion 125b tapers toward the upper portion 125t. This results in the width of the middle portion of the first through-hole 125 being smaller than the widths at the upper and lower ends. Thus, at the junction of the upper portion 125t and the lower portion 125b of the first through-hole 125, the core 120 forms a pointed corner protruding into the first through-hole 125. The dielectric layer 140 extends onto the inner sidewalls of the upper portion 125t and the lower portion 125b of the first through-hole 125. The substrate structure 100 also includes a circuit layer 230 formed on the dielectric layer 140 within the first through-hole 125. The circuit layer 230 may also extend onto the dielectric layer 140 outside the first through-hole 125.

[0029] In the above technical solution, the core 120, which is unsuitable for forming fine circuits, is addressed by forming a dielectric layer 140 on the surface of the core 120 and the inner sidewalls of the first through-hole 125, and then forming a circuit layer 230 on the dielectric layer 140. This solves the problem of being unable to directly form fine circuits on the surface of the core 120 and the inner sidewalls of the first through-hole 125. When a material with a low CTE is used for the core 120 of the substrate structure 100, fine circuits with an L / S ratio of less than 36 / 40 microns can be formed on the substrate structure 100. In some embodiments, the circuit layer 230 on the dielectric layer 140 outside the first through-hole 125 can achieve an L / S ratio of less than or equal to 12 microns / 12 microns.

[0030] In some embodiments, the dielectric layer 140 has a first surface roughness, and the core 120 has a second surface roughness. The first surface roughness of the dielectric layer 140 is less than the second surface roughness of the core 120, that is, the surface of the core 120 is rougher, and the surface of the dielectric layer 140 is smoother. The core 120, with its relatively rough surface, is not suitable for directly plating copper on its surface to form fine circuits. By forming the dielectric layer 140 on the surface of the core 120 and the inner sidewall surface of the first through-hole 125, and then forming the circuit layer 230 on the dielectric layer 140, a material with a relatively rough surface can be used as the core 120 of the substrate structure 100, while also forming fine circuits on the substrate structure 100.

[0031] In some embodiments, the hardness of the core 120 is greater than the hardness of the circuit layer 230. In some embodiments, the rigidity of the core 120 is greater than the rigidity of the circuit layer 230. For a core 120 with relatively high hardness / rigidity, it may not be suitable to directly plate copper on its surface to form fine circuits. However, by forming a dielectric layer 140 on the surface of the core 120 and the inner sidewall surface of the first through-hole 125, and then forming the circuit layer 230 on the dielectric layer 140, a material with relatively high hardness / rigidity can be used as the core 120 of the substrate structure 100, while also forming fine circuits on the substrate structure 100.

[0032] In some embodiments, the core 120 is a ceramic material core 120. The ceramic material core 120 may have the advantages of good heat dissipation, small CTE, strong rigidity and hardness. In addition, the glass transition temperature (Tg) of the ceramic material is also relatively high, so it can withstand higher temperatures without easily causing warping. In this embodiment, the problem that the ceramic material with good heat dissipation, small CTE, strong rigidity and hardness is not suitable for directly plating copper on its surface to form fine circuits is solved by forming a dielectric layer 140 on the surface of the core 120 and the inner wall surface of the first through hole 125, and then forming a circuit layer 230 on the dielectric layer 140. This solves the problem that the surface of the traditional ceramic substrate and the inner wall of the first through hole 125 cannot be directly electroplated to form fine circuits due to their roughness. Fine circuits with an L / S of less than 36 / 40 microns, for example, less than or equal to 12 microns / 12 microns, can be formed on the substrate.

[0033] Continue to refer Figure 1 As shown, the dielectric layer 140 extending onto the inner sidewalls of the upper portion 125t and the lower portion 125b of the first through hole 125 defines an X-shaped second through hole 145. Specifically, the second through hole 145 includes an upper portion 145t and a lower portion 145b. The width of the upper portion 145t of the second through hole 145 gradually decreases toward the lower portion 145b, and the width of the lower portion 145b of the second through hole 145 gradually decreases toward the upper portion 145t.

[0034] exist Figure 1 In the cross-sectional view shown, the second through hole 145 has a first surface S1 and a second surface S2 relative to each other above the upper portion 125t of the first through hole 125. The second surface S2 contacts the inner side wall of the upper portion 125t of the first through hole 125. The second through hole 145 has a third surface S3 and a fourth surface S4 relative to each other below the lower portion 125b of the first through hole 125. The first surface S1 of the second through hole 145 is connected to the third surface S3. The fourth surface S4 contacts the inner side wall of the lower portion 125b of the first through hole 125. In the direction from bottom to top, the first surface S1 gradually tilts outward, and the third surface S3 gradually tilts inward. Figure 1 In the illustrated embodiment, the first surface S1 and the second surface S2 may be substantially parallel.

[0035] The wiring layer 230 located within the first through-hole 125 defines a conductive through-hole 231. Specifically, the conductive through-hole 231 is in surface contact with the first surface S1 and the third surface S3 of the dielectric layer 140. Therefore, the shape of the conductive through-hole 231 can be defined by the second through-hole 145 of the dielectric layer 140. The width of the upper portion of the conductive through-hole 231 (corresponding to the upper portion 145t of the second through-hole 145) gradually decreases toward the lower portion of the conductive through-hole 231 (corresponding to the lower portion 145b of the second through-hole 145), and the width of the lower portion of the conductive through-hole 231 gradually decreases toward the upper portion of the conductive through-hole 231. This structure of the first through-hole 125 being narrow in the middle and wide at the top and bottom can enhance the locking strength between the conductive through-hole 231 and the stacked core 120 and dielectric layer 140.

[0036] The embodiments of the present application also provide a method for forming the substrate structure 100 . Figures 2A to 2H 1 is a schematic cross-sectional view of a method for forming the substrate structure 100 of the present application at multiple stages.

[0037] refer to Figure 2A As shown, a core 120 is provided, for example, a ceramic core. Then, a double-sided laser drilling process is performed on the core 120 at the upper and lower sides of the core 120 to form a first through hole 125 passing through the core 120. Due to the double-sided laser drilling process, the formed first through hole 125 includes an upper portion 125t and a lower portion 125b, and the width of the upper portion 125t gradually decreases toward the lower portion 125b, and the width of the lower portion 125b gradually decreases toward the upper portion 125t. In other embodiments, first through holes 125 of other structures can also be formed in the core 120. For example, referring to Figure 3A As shown, a first through hole 125' with a vertical sidewall can be formed in the core 120. In this embodiment, the first through hole 125' can be used to form a PTH (Plated Through Hole). Figure 3B As shown, a single-side laser drilling process can be performed to form Figure 3B The first through hole 125" is shown in FIG. 1 , wherein the width of the first through hole 125" increases from bottom to top. Figure 2A The structure of the first through hole 125 is described below.

[0038] refer to Figure 2B As shown, dielectric layers 140 are laminated on the upper and lower sides of the core 120, and the dielectric layers 140 fill the first through holes 125. The dielectric layer 140 may be, for example, an ABF (Ajinomoto built-up film) layer or a BT (bismaleimide triazine resin) layer.

[0039] refer to Figure 2CAs shown, a double-sided laser drilling process is performed on the upper and lower sides of the core 120 to form a second through hole 145 passing through the dielectric layer 140 and the first through hole 125. Due to the double-sided laser drilling process, the width of the upper portion 145t of the formed second through hole 145 gradually decreases toward the lower portion 145b, and the width of the lower portion 145b gradually decreases toward the upper portion 145t.

[0040] Then refer to Figure 2D As shown, a seed layer 266 is plated on the surface of the dielectric layer 140. The seed layer 266 can be formed, for example, by an electroless plating (E'less) process. The seed layer 266 can cover the entire surface of the dielectric layer 140. Figure 2E As shown, a patterned mask layer 228 , such as a dry film layer, is formed on the seed layer 266 . The patterned mask 228 may be formed on the upper and lower surfaces of the seed layer 266 outside the second through hole 145 .

[0041] Then, an electroplating process is performed to form a conductive material on the seed layer 266. The conductive material and the material of the seed layer 266 can be the same, refer to Figure 2F The formed conductive material and the seed layer 266 together form a conductive material layer 270 . The conductive material layer 270 fills the second through hole 145 .

[0042] refer to Figure 2G As shown, peel Figure 2F The patterned mask layer 228 in FIG. Figure 2H As shown, an etching process is performed to remove the seed layer 266 previously formed under the patterned mask layer 228 (see FIG. Figure 2E In this way, a circuit layer 230 is formed. The circuit layer 230 includes a conductive via 231 formed in the second through hole 145 .

[0043] In some embodiments, Figure 2F During the formation of the conductive material layer, after the conductive material is filled into the second through hole 145 by the electroplating process to form the conductive material layer 270, as shown in FIG. Figure 4A As shown, a depression 272 may be formed on the upper surface and the lower surface of the conductive material layer 270 at the second through hole 145. A hole 274 may also be formed in the conductive material layer 270. The depression 272 and the hole 274 may be generated by filling the conductive material into the second through hole 145 having a certain depth. Then refer to Figure 4B As shown, after removing the patterned mask 228 and the seed layer thereunder, the conductive via 231 of the formed circuit layer 230 has recesses 272 on the upper and lower surfaces thereof, and a hole 274 is formed in the conductive via 231 .

[0044] Figure 5is a schematic cross-sectional view of a substrate structure 200 according to another embodiment of the present application. Figure 5 The illustrated embodiment can be compared with the above-mentioned Figures 1 to 4B Similar to the description, the following mainly describes Figure 5 The differences from the embodiment shown.

[0045] refer to Figure 5 As shown, the first surface S1 and the second surface S2 may not be parallel. Figure 5 In the figure, the extension lines of the first surface S1 and the second surface S2 are shown in dotted lines to clearly show that the first surface S1 and the second surface S2 are not parallel. The horizontal distance between the first surface S1 and the second surface S2 gradually decreases toward the lower portion 145b of the second through hole 145. Figure 5 In the cross-sectional view shown, the inclination angle of the first surface S1 relative to the centerline C1 of the second through-hole 145 is smaller than the inclination angle of the second surface S2. Furthermore, similar to the first surface S1 and the second surface S2, the third surface S3 and the fourth surface S4 may not be parallel. The horizontal distance between the third surface S3 and the fourth surface S4 gradually decreases toward the upper portion 145t. The inclination angle of the third surface S3 relative to the centerline C1 of the second through-hole 145 is smaller than the inclination angle of the fourth surface S4.

[0046] Figure 6 is a schematic cross-sectional view of a substrate structure according to another embodiment of the present application. Figure 6 The illustrated embodiment can be compared with the above-mentioned Figures 1 to 4B Similar to the description, the following mainly describes Figure 6 The differences from the embodiment shown.

[0047] refer to Figure 6 As shown, the first surface S1 and the second surface S2 are not parallel. The third surface S3 and the fourth surface S4 are not parallel. The horizontal distance between the first surface S1 and the second surface S2 gradually increases toward the lower portion 145b of the second through hole 145. The horizontal distance between the third surface S3 and the fourth surface S4 gradually increases toward the upper portion 145t of the second through hole 145.

[0048] Figure 7 is a schematic cross-sectional view of a substrate structure 400 according to another embodiment of the present application. Figure 7 The illustrated embodiment can be compared with the above-mentioned Figures 1 to 4B The description is similar, except that the first through hole 125 of the core 120 may have vertical sides, and the width of the first through hole 125 is constant in the vertical direction.

[0049] The present application also provides a substrate structure and a method for forming the same according to another embodiment. Figures 8A to 8L1 is a schematic cross-sectional view of a method for forming a substrate structure according to another embodiment at multiple stages.

[0050] First reference Figure 8A As shown, a carrier 802 is provided, and the lower surface of the carrier 802 is covered by a copper foil 866. A patterned mask layer 828 is formed on the lower surface of the copper foil 866.

[0051] refer to Figure 8B As shown, a conductive material layer 870 is formed on the copper foil 866 by, for example, an electroplating process. Then, the patterned mask layer 828 is removed, and an opening 805 is formed at the position where the patterned mask layer 828 is removed. Figure 8C , a ceramic material is coated on the conductive material layer 870. The ceramic material is filled into the opening 805, thereby forming the core 820 by the ceramic material.

[0052] refer to Figure 8D As shown, a first through hole 825 is formed through the core 820, and the conductive material layer 870 is exposed by the first through hole 825. Figure 8E As shown, in Figure 8D The structure is shown with the underside covered by a dielectric layer 840. Figure 8F As shown, a second through hole 845 is formed in the dielectric layer 840 passing through the first through hole 825 , and the second through hole 845 exposes the conductive material layer 870 .

[0053] refer to Figure 8G As shown, in Figure 8F The structure shown is coated with a seed layer 868 on the bottom side, and a patterned mask layer 829 is formed on the surface of the seed layer 868. Figure 8H ,exist Figure 8G The bottom side of the structure is plated with a conductive material to form a conductive material layer 872. The conductive material layer 872 fills the second through hole 845.

[0054] refer to Figure 8I , removing the patterned mask layer 829, and removing the seed layer 868 previously covered by the patterned mask layer 829. Figure 8J , remove the carrier 802. Figure 8K , remove copper foil 866.

[0055] refer to Figure 8L ,exist Figure 8KA patterned dielectric layer 890 is formed on the upper and lower sides of the structure shown. Thus, a substrate structure 500 is formed. In the substrate structure 500, the core 820 includes a first through-hole 825, and the dielectric layer 840 includes a second through-hole 845. The sidewalls of the first through-hole 825 and the sidewalls of the second through-hole 845 are inclined, and the widths of the first through-hole 825 and the second through-hole 845 gradually increase from top to bottom. In this embodiment, the sidewalls of the first through-hole 825 and the sidewalls of the second through-hole 845 may not be parallel to each other. The sidewalls of the first through-hole 825 and the sidewalls of the second through-hole 845 are inclined outward from top to bottom, and the sidewalls of the first through-hole 825 may be more inclined than the sidewalls of the second through-hole 845.

[0056] Figure 9 FIG. 6 is a schematic cross-sectional view of a substrate structure 600 according to another embodiment of the present application. Figure 9 The illustrated embodiment can be compared with the above-mentioned Figure 8L The description is similar, except that the sidewalls of the first through-hole and the sidewalls of the second through-hole may be substantially parallel.

[0057] In summary, the present invention leverages ceramic's advantages of excellent heat dissipation, low CTE, and strong rigidity. It then coats the ceramic with another dielectric material, then processes it and applies it to a specific layer of the substrate structure. The other dielectric layers are still primarily made of common dielectric materials. This substrate structure leverages the advantages of ceramic, with the core composed of ceramic material. This not only leverages the advantages of ceramic but also solves the problem of ceramic's inability to directly form fine circuits.

[0058] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A substrate structure, characterized in that: include: The core comprises a first through hole, wherein the first through hole comprises an upper portion and a lower portion, wherein in a cross-sectional view, a width of the upper portion gradually decreases toward the lower portion, and a width of the lower portion gradually decreases toward the upper portion; a dielectric layer covering the core and extending onto inner sidewalls of the upper portion and the lower portion of the first through hole, wherein a thermal expansion coefficient of the core is smaller than a thermal expansion coefficient of the dielectric layer; as well as A circuit layer is formed on the dielectric layer in the first through hole.

2. The substrate structure according to claim 1, wherein: The dielectric layer has a first surface roughness and the core has a second surface roughness, wherein the first surface roughness is less than the second surface roughness.

3. The substrate structure according to claim 1, wherein: The hardness of the core is greater than the hardness of the circuit layer.

4. The substrate structure according to claim 1, wherein: The rigidity of the core is greater than the rigidity of the circuit layer.

5. The substrate structure according to claim 1, wherein: The dielectric layer extending to the inner sidewalls of the upper portion and the lower portion of the first through hole defines an X-shaped second through hole, the width of the upper portion of the second through hole gradually decreases toward the lower portion of the second through hole, and the width of the lower portion of the second through hole gradually decreases toward the upper portion of the second through hole, In a cross-sectional view, the second through hole has a first surface and a second surface opposite to each other above the upper portion of the first through hole, wherein the first surface is not parallel to the second surface.

6. The substrate structure according to claim 5, characterized in that: A distance between the first surface and the second surface in a horizontal direction gradually decreases toward the lower portion of the second through hole.

7. The substrate structure according to claim 5, wherein: In a cross-sectional view, the second through hole has a third surface and a fourth surface facing each other below the lower portion of the first through hole, wherein the third surface is non-parallel to the fourth surface.

8. The substrate structure according to claim 5, wherein: In a cross-sectional perspective, relative to a center line of the second through hole, an inclination angle of the first surface is smaller than an inclination angle of the second surface.

9. The substrate structure according to claim 1, wherein: The circuit layer located in the first through hole defines a conductive through hole, and the upper and lower surfaces opposite to each other of the conductive through hole have recesses.

10. The substrate structure according to claim 1, wherein: The circuit layer further extends onto the dielectric layer outside the first through hole.

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