Up-converter and satellite communication system
By designing an upconverter including an intermediate frequency signal frequency conversion module, a reference clock processing module, a logic control module and a phase-locking loop in the satellite communication system, flexible adaptation and adaptive switching of reference clock signals of different frequencies is achieved, and the problem of low flexibility in reference clock adaptation in traditional satellite communication systems is solved, reducing system costs and improving system performance.
Patent Information
- Application Number
- CN202422557923.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-22
- Publication Date
- 2025-08-26
- Estimated Expiration
- 2034-10-22
AI Technical Summary
In traditional satellite communication systems, the flexibility of reference clock adaptation is low, resulting in increased system cost and increased complexity, and it is impossible to adapt to the switching of different reference clock signals.
An upconverter is designed, including an intermediate frequency signal frequency conversion module, a reference clock processing module, a logic control module, a radio frequency switch and a phase-locking loop module. It detects and adapts reference clock signals of different frequencies through multiple detection branches, and controls the radio frequency switch switching channel through the logic control module to generate the corresponding local oscillator frequency.
It realizes flexible adaptation and adaptive switching of multiple reference clock signals with different frequencies, improves system flexibility, reduces system costs, and can identify and monitor reference signal quality, preventing adverse signals from affecting system performance.
Smart Images
Figure CN223274085U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of radio frequency communication technology, and in particular to an up-converter and a satellite communication system. Background Art
[0002] Traditional satellite communication systems consist of a modem, an upconverter (BUC), a low-noise block (LNB), a power supply, and an antenna system. The modem and upconverter are connected via an IF cable. The modem provides the upconverter with a transmit IF signal and a reference clock. The upconverter filters the transmit IF signal, amplifies it, and mixes it to generate the desired RF frequency. After filtering, it undergoes multi-stage power amplification. The reference clock serves as the reference clock for the phase-locked loop (PLL) to generate the corresponding local oscillator frequency.
[0003] In real-world applications, different modems use different reference clocks depending on the system design, such as a 10MHz reference clock signal and a 50MHz reference clock signal. Even within the same system, the reference clock may switch between different signals. Traditionally, a separate upconverter has been designed for each reference clock signal. However, this design reduces system flexibility and requires the production of multiple upconverters to accommodate reference clock variations, further increasing system costs. Utility Model Content
[0004] The present application provides an upconverter and a satellite communication system, which solves the problem of low reference clock adaptation flexibility of the satellite communication system in the related art. The present application can meet the application requirements of different reference clocks and different systems, has high flexibility, and can identify and monitor the quality of the reference signal to prevent poor reference clocks from affecting the system signal quality.
[0005] In a first aspect, the present application provides an up-converter, which is connected to a modem to receive an output signal provided by the modem. The up-converter includes an intermediate frequency signal conversion module, a reference clock processing module, a logic control module, a radio frequency switch and a phase-locked loop module.
[0006] The input end of the intermediate frequency signal conversion module is connected to the output signal provided by the modem, and the intermediate frequency signal conversion module is used to amplify and mix the intermediate frequency signal using the local oscillator frequency;
[0007] Multiple input terminals of the reference clock processing module are connected to the output signal provided by the modem, and each input terminal of the reference clock processing module corresponds to a detection branch. The reference clock processing module is used to detect and compare the frequency and power of the reference clock signal in the output signal provided by the modem through the multiple detection branches to determine the frequency of the reference clock and output a frequency comparison signal;
[0008] The input end of the logic control module is connected to the detection output end of the reference clock processing module, and the logic control module is used to determine the output control signal based on the frequency comparison signal output by the detection output end of the reference clock processing module;
[0009] The RF switch includes a control terminal, an output terminal, and multiple input terminals. The control terminal of the RF switch is connected to the control output terminal of the logic control module. The multiple input terminals of the RF switch are respectively connected to the multiple output terminals of the reference clock processing module in a one-to-one correspondence. The RF switch is used to select the reference clock signal connected to the target input terminal of the RF switch according to the control signal received by the control terminal of the RF switch and output it through the output terminal of the RF switch.
[0010] The reference input terminal of the phase-locked loop module is connected to the output terminal of the radio frequency switch. The phase-locked loop module is used to generate a local oscillator frequency provided to the intermediate frequency signal frequency conversion module according to the reference clock signal output by the radio frequency switch.
[0011] In a second aspect, the present application also provides a satellite communication system, which includes the above-mentioned up-converter.
[0012] The upconverter of this application uses multiple detection branches in the reference clock processing module to detect and adapt to multiple reference clock signals of different frequencies. Therefore, when a corresponding reference clock signal is connected, the upconverter can control the RF switch through the logic control module to conduct the corresponding channel, so that the phase-locked loop module can output the corresponding local oscillator frequency. Furthermore, the reference clock processing module can also be used for adaptation when switching reference clock signals, making the upconverter more flexible and enabling highly flexible adaptive switching of reference clock signals. BRIEF DESCRIPTION OF THE DRAWINGS
[0013] Figure 1 A schematic structural diagram of an up-converter provided in one embodiment of the present application;
[0014] Figure 2 A schematic diagram of the structure of a reference clock processing module provided in one embodiment of the present application;
[0015] Figure 3 A schematic diagram of the structure of a logic control module provided in one embodiment of the present application;
[0016] Figure 4A schematic structural diagram of a logic control module provided in another embodiment of the present application;
[0017] Figure 5 A schematic structural diagram of an up-converter provided in another embodiment of the present application. DETAILED DESCRIPTION
[0018] The embodiments of the present application are further described in detail below in conjunction with the accompanying drawings and examples. It will be understood that the specific embodiments described herein are merely used to explain the embodiments of the present application, rather than to limit the embodiments of the present application. It should also be noted that, for ease of description, only portions related to the embodiments of the present application, rather than all structures, are shown in the accompanying drawings. After reading this specification, those skilled in the art should be able to understand that, as long as the technical features do not contradict each other, any combination of the technical features may constitute an optional embodiment.
[0019] The terms "first", "second", etc. in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of the same type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims means at least one of the connected objects, and the character " / " generally indicates that the objects associated before and after are in an "or" relationship. In the description of this application, "multiple" means two or more, and "several" means one or more.
[0020] A traditional satellite communication system consists of a modem, an upconverter, a low-noise downconverter, a power supply, and an antenna system. The modem is responsible for digital signal processing, providing an intermediate frequency (IF) signal and a reference clock for the upconverter, or providing a reference clock for the low-noise downconverter and processing the IF signal output from the downconverter. The upconverter converts the transmitted IF signal to the required RF frequency and amplifies the signal. The low-noise downconverter converts the received RF signal to an IF frequency that the modem can demodulate and provides sufficient receive gain. The power supply system is responsible for powering equipment (such as the BUC, LNB, and others). The antenna system, including the antenna, polarizer, filter, and turntable, is responsible for transmitting and receiving signals to and from the satellite.
[0021] In real-world applications, different modems use different reference clocks depending on the system design, such as a 10MHz reference clock signal and a 50MHz reference clock signal. Even within the same system, the reference clock may switch between different signals. Traditionally, a separate upconverter has been designed for each reference clock signal. However, this approach limits system flexibility, requiring multiple upconverters to accommodate reference clock variations, further increasing system cost and complexity.
[0022] In this regard, the present application provides an upconverter and a satellite communication system. The satellite communication system includes the upconverter of the present application as well as a modem, a low-noise downconverter, a power supply system and an antenna feed system. However, compared with the related art, the upconverter of the present application is provided with a corresponding detection branch to adapt to the reference clock signal, which improves the flexibility of the system and effectively reduces the system cost.
[0023] Figure 1 This is a structural diagram of an up-converter provided in one embodiment of the present application. The up-converter is connected to a modem and receives an output signal provided by the modem. Figure 1 As shown, the up-converter includes an intermediate frequency signal conversion module 110 , a reference clock processing module 120 , a logic control module 130 , a radio frequency switch 140 and a phase-locked loop module 150 .
[0024] The input of the intermediate frequency signal conversion module 110 is connected to the output signal provided by the modem. The intermediate frequency signal conversion module 110 can amplify and mix the intermediate frequency signal using the local oscillator frequency. The multiple inputs of the reference clock processing module 120 are connected to the output signal provided by the modem. Each input of the reference clock processing module 120 corresponds to a detection branch. The reference clock processing module 120 is used to detect and compare the frequency and power of the reference clock signal in the output signal provided by the modem through the multiple detection branches to determine the frequency of the reference clock and output a frequency comparison signal.
[0025] Furthermore, the input of logic control module 130 is connected to the detection output of reference clock processing module 120. Logic control module 130 is configured to determine an output control signal based on the frequency comparison signal output by the detection output of reference clock processing module 120. RF switch 140 includes a control terminal, an output terminal, and multiple input terminals. The control terminal of RF switch 140 is connected to the control output of logic control module 130, and the multiple input terminals of RF switch 140 are connected one-to-one to the multiple output terminals of reference clock processing module 120. It is conceivable that RF switch 140 is a multi-input, single-output device, thereby providing multiple signal channels. These channels are configured to select a reference clock signal connected to a target input terminal of RF switch 140 based on a control signal received by the control terminal of RF switch 140, and output the signal through the output terminal of RF switch 140. Furthermore, the reference input of phase-locked loop module 150 is connected to the output of RF switch 140. Phase-locked loop module 150 is configured to generate a local oscillator frequency for intermediate frequency signal conversion module 110 based on the reference clock signal output by RF switch 140.
[0026] It is understood that the upconverter provides multiple detection branches through its reference clock processing module 120 to extract the reference clock signal from the input signal. When the logic control module 130 determines that the corresponding detection branch has received the corresponding reference clock signal, it controls the RF switch 140 to open the signal channel corresponding to the detection branch, allowing the phase-locked loop module 150 to generate a local oscillator frequency based on the corresponding reference clock signal. The intermediate frequency signal in the output signal is processed by the intermediate frequency signal conversion module 110 of the upconverter and mixed with the local oscillator frequency provided by the phase-locked loop module 150 to provide the corresponding radio frequency for the satellite communication system.
[0027] For example, when a 10MHz or 50MHz reference clock signal is used in a satellite communication process, the reference clock processing module of the up-converter includes detection branches corresponding to 10MHz and 50MHz, so that when a 10MHz or 50MHz reference clock signal is doped in the output signal provided by the modem, the up-converter can detect through the reference clock processing module whether the frequency corresponding to the reference clock signal is 10MHz or 50MHz, and pass the reference clock signal to the phase-locked loop module after processing, so as to realize the output of the local oscillator frequency according to the corresponding phase-locked loop configuration, thereby providing the satellite communication system with a radio frequency adapted to the reference clock signal.
[0028] Therefore, the upconverter uses multiple detection branches in the reference clock processing module to detect and adapt to multiple reference clock signals of different frequencies. When a corresponding reference clock signal is connected, the upconverter controls the RF switch via the logic control module to conduct the corresponding channel, allowing the phase-locked loop module to output the corresponding local oscillator frequency. Furthermore, the reference clock processing module can also be used to adapt when switching reference clock signals, making the upconverter more flexible and enabling highly adaptive switching of reference clock signals.
[0029] In one embodiment, the reference clock processing module includes at least two detection branches, each corresponding to a different frequency band to adapt to the corresponding reference clock signal. For example, based on the above example, the reference clock processing module includes detection branches corresponding to a 10 MHz reference clock signal and a 50 MHz reference clock signal. When the corresponding reference clock is connected, the module can provide corresponding channels for processing the reference clock signals, allowing the phase-locked loop module to provide a local oscillator frequency based on the reference clock information.
[0030] Specifically, the detection branch includes a first bandpass filter, a first amplifier, a power splitter, and a logarithmic detector. The input of the first bandpass filter serves as the input of the detection branch, the output of the first bandpass filter is connected to the input of the first amplifier, the output of the first amplifier is connected to the input of the power splitter, the first output of the power splitter serves as the output of the detection branch, the second output of the power splitter is connected to the logarithmic detector, the power splitter is used to split the signal power into two paths, and the logarithmic detector is used to detect the power intensity of the reference signal.
[0031] It can be imagined that the first bandpass filter, as the device for accessing the reference clock signal in the detection branch, corresponds to a different frequency band in each detection branch and adapts to the corresponding reference clock signal, so that different detection branches adapt to the same reference clock signal. The reference clock signal corresponding to the detection branch can then be accessed through the first bandpass filter and amplified by the first amplifier. The power divider can then split the amplified reference clock signal, providing one signal to the RF switch and the other to the logarithmic detector.
[0032] Figure 2 A schematic diagram of the structure of a reference clock processing module provided in an embodiment of the present application is shown in FIG. Figure 2As shown, two detection branches are provided in the reference clock processing module. Each detection branch corresponds to a different reference clock signal frequency, and each detection branch includes a bandpass filter, a first amplifier, a power divider, and a logarithmic detector connected in sequence. Specifically, the dashed boxes in the figure indicate each detection branch, where the output of bandpass filter BPF1 in the first detection branch is connected to the input of amplifier A1, the output of amplifier A1 is connected to the input of power divider PD1, the first output of power divider PD1 is connected to an input of an RF switch, and the second output of power divider PD1 is connected to the input of logarithmic detector LD1.
[0033] In the second detection branch, the output of bandpass filter BPF2 is connected to the input of amplifier A2, the output of amplifier A2 is connected to the input of power divider PD2, the first output of power divider PD2 is connected to another input of the RF switch, and the second output of power divider PD2 is connected to the input of logarithmic detector LD2. It is conceivable that the outputs of logarithmic detectors LD1 and LD2 are connected to different inputs of the frequency comparison unit, respectively. This allows the frequency comparison unit to compare the voltage values output by each logarithmic detector and provide a corresponding comparison result to the logic control module for controlling the RF switch.
[0034] Exemplarily, when the reference clock processing module includes a first detection branch corresponding to a 10MHz reference clock signal and a second detection branch corresponding to a 50MHz reference clock signal, when the output signal provided by the modem carries a corresponding 10MHz reference clock signal, the first detection branch can extract the reference clock signal from the output signal via a bandpass filter BPF1. After amplification by amplifier A1, power divider PD1 provides a signal to logarithmic detector LD1, which generates a voltage signal corresponding to the frequency of the reference clock signal. Similarly, in the second detection branch, since there is no corresponding 50MHz reference clock signal connected, the voltage signal provided by logarithmic detector LD2 is relatively small. In response, the frequency comparison unit can output a corresponding comparison result based on the connected voltage signal. Furthermore, the logic control module can output a corresponding control signal based on the set functional mode and the comparison result to control the RF switch. Therefore, through the corresponding detection branch, the upconverter can adapt to the switching of reference clocks of multiple different frequencies, making the generation of RF signals more simple and efficient, and helping to improve the flexibility of the upconverter.
[0035] In some embodiments, the reference clock processing module further includes a frequency comparison unit, which includes multiple input terminals. Each input terminal of the frequency comparison unit is connected to the output terminal of a logarithmic detector in a different detection branch. The output terminal of the frequency comparison unit serves as the detection output terminal of the reference clock processing module. The frequency comparison unit is configured to determine the voltage levels of the outputs of all logarithmic detectors to output a frequency comparison signal. It is contemplated that, based on the aforementioned configuration of two detection branches, the frequency comparison unit is connected to the voltages output by the logarithmic detectors in the two detection branches, thereby comparing the corresponding voltage levels and transmitting the comparison result to the logic control module, for the logic control module to output a corresponding control signal.
[0036] In one embodiment, when there are two detection branches, the frequency comparison unit includes a first hysteresis comparator, wherein the non-inverting input of the first hysteresis comparator is connected to the output of the logarithmic detector in one detection branch, and the inverting input of the first hysteresis comparator is connected to the output of the logarithmic detector in the other detection branch. Figure 2 ,based on Figure 2 In the structure shown, the non-inverting input terminal of the first hysteresis comparator can be connected to the voltage signal provided by the logarithmic detector LD1, and the inverting input terminal of the first hysteresis comparator can be connected to the voltage signal provided by the logarithmic detector LD2, so that the first hysteresis comparator can represent different comparison results by outputting corresponding high-level signals or low-level signals.
[0037] In another embodiment, when there are three detection branches, the frequency comparison unit includes an adder, a second hysteresis comparator, and a third hysteresis comparator. The output of the logarithmic detector of the first detection branch and the output of the logarithmic detector of the second detection branch are respectively connected to two inputs of the adder, the output of the adder is connected to the non-inverting input of the second hysteresis comparator, and the output of the logarithmic detector of the third detection branch is connected to the inverting input of the second hysteresis comparator.
[0038] In addition, the output end of the logarithmic detector of the first detection branch is also connected to the non-inverting input end of the third hysteresis comparator, and the output end of the logarithmic detector of the second detection branch is also connected to the inverting input end of the third hysteresis comparator. The output end of the third hysteresis comparator and the output end of the second hysteresis comparator both serve as the output end of the frequency comparison unit.
[0039] It can be understood that the voltage signal output by the logarithmic detector on the first detection branch and the second detection branch is compared through the third hysteresis comparator, and for the third detection branch, the signal connected to the third detection branch is determined by comparing it with the sum of the voltage signals provided by the first detection branch and the second detection branch, that is, the frequency comparison unit can provide two comparison results for the logic control module.
[0040] The logarithmic detector has a fast response speed in performing power detection on the reference clock signal. Therefore, the up-converter uses a frequency comparison unit to compare the voltage values output by the logarithmic detector in each detection branch. This can quickly provide the corresponding comparison results to the logic control module, facilitating faster switching control of the RF switch and helping to improve the system's response speed.
[0041] In one embodiment, the logic control module includes a multiplexing unit and a microcontroller unit, wherein a first input of the multiplexing unit is connected to an output of the reference clock processing module, and an output of the multiplexing unit is connected to a control terminal of a radio frequency switch. The first input of the multiplexing unit is also connected to a first control interface of the microcontroller unit. A second control interface of the microcontroller unit is connected to a second input of the multiplexing unit, and a third control interface of the microcontroller unit is connected to the control terminal of the multiplexing unit. The microcontroller unit is configured to determine, based on a frequency comparison signal, a signal output through the first control interface and a signal output through the third control interface to control the radio frequency switch to activate corresponding channels.
[0042] Figure 3 This is a structural diagram of a logic control module provided in an embodiment of the present application, as shown in FIG. Figure 3 As shown, in the case where there are two detection branches, the multiplexing unit includes a multiplexer U1, and the multiplexer U1 includes two input interfaces. Specifically, the first input interface of the multiplexer U1 is connected to the detection output end of the reference clock processing module and the first control interface of the micro control unit U2, the second input interface of the multiplexer U1 is also connected to the second control interface of the micro control unit U2, and the control interface of the multiplexer U1 is connected to the third control interface of the micro control unit U2. The multiplexer U1 is used to select the input signal connected to the corresponding input interface according to the selection signal output by the third control interface of the micro control unit U2, and control the RF switch to open the corresponding channel according to the input signal.
[0043] It can be understood that the first input interface of the multiplexer U1 is connected to the signal provided by the detection output of the reference clock processing module. For example, the first input interface of the multiplexer U1 is connected to the output of the frequency comparison unit to receive the electrical signal corresponding to the comparison result (denoted as Vop). The second input interface of the multiplexer U1 is connected to the signal provided by the micro-control unit U2 (denoted as Vom). In addition, the control interface of the multiplexer U1 is connected to the third control interface of the micro-control unit U2, so that the micro-control unit U2 provides a corresponding selection signal (denoted as Venc) so that the multiplexer U1 outputs one of the received signals (denoted as Vc_SW).
[0044] Figure 4A structural diagram of a logic control module provided in another embodiment of the present application is shown as follows: Figure 4 As shown, in one embodiment, when there are three detection branches, the multiplexing unit includes two multiplexers, each of which includes two input interfaces. Specifically, the multiplexer unit includes a first multiplexer U1 and a second multiplexer U3.
[0045] The first input interface of the first multiplexer U1 is connected to a detection output terminal of the reference clock processing module and is also connected to a first control interface of the micro-control unit U2. The signal received by the first input interface of the first multiplexer U1 is denoted as Vop1. The second input interface of the first multiplexer U1 is connected to a second control interface of the micro-control unit U2. The signal received by the second input interface of the first multiplexer U1 is denoted as Vom1. The control interface of the first multiplexer U1 is connected to a third control interface of the micro-control unit U2. The signal received by the control interface of the first multiplexer U1 is denoted as Venc1.
[0046] The first input interface of the second multiplexer U3 is connected to another detection output terminal of the reference clock processing module and is also connected to another first control interface of the micro-control unit U2. The signal received by the first input interface of the second multiplexer U3 is recorded as Vop2. The second input interface of the second multiplexer U3 is connected to another second control interface of the micro-control unit U2. The signal received by the second input interface of the second multiplexer U3 is recorded as Vom2. The control interface of the second multiplexer U3 is connected to another third control interface of the micro-control unit U2. The signal received by the control interface of the second multiplexer U3 is recorded as Venc2.
[0047] To this end, the microcontroller unit U2 provides a corresponding input signal to the second input interface of each multiplexer, and also controls the multiplexer through the corresponding third control interface to select the corresponding input signal for output to the RF switch, so as to control the RF switch to open the corresponding channel according to the two input signals. It is conceivable that when there are two input signals, when selecting the three channels in the RF switch, different high and low levels can be used to correspond to different channels. For example, if both selection signals are low-level signals, the RF switch can select and open the first channel; if both selection signals are high-level signals, the RF switch can select and open the second channel; if the two selection signals include one high-level signal and one low-level signal, the RF switch can select and open the third channel.
[0048] In some embodiments, the microcontroller is configured with functional modes, such as a comparator mode, an ADC (Analog to Digital Converter) comparison mode, a first forced mode, and a second forced mode. For selecting the aforementioned functional modes, the user can configure different operating modes and use different reference switching modes according to application needs. The microcontroller can output corresponding electrical signals to the aforementioned functional modules via its second and third control interfaces.
[0049] Specifically, in the comparator mode, the configuration parameter register information of two corresponding phase-locked loop modules compiled in advance is set in the micro control unit, and the high-speed I / O pin of the micro control unit is used to select the corresponding configuration parameter information according to the comparator frequency comparison signal and configure the phase-locked loop module.
[0050] In the ADC comparison mode, the ADC detection interface of the microcontroller unit is respectively connected to the signal voltage of each detection branch. The microcontroller unit is used to determine the power according to a preset calibration table, and output a target control signal in the presence of a target reference clock signal with the maximum power and a power greater than a threshold, so that the RF switch selects the channel corresponding to the target reference clock signal. The calibration table includes each voltage at multiple preset clock frequencies and the power corresponding to each voltage.
[0051] In the first forced mode, the microcontroller outputs a first control signal, which is used to cause the RF switch to select the channel corresponding to the first reference clock signal. In the second forced mode, the microcontroller outputs a second control signal, which is used to cause the RF switch to select the channel corresponding to the second reference clock signal.
[0052] Therefore, by providing multiple functional modes, the satellite communication system can adapt to different reference clock frequencies more flexibly. At the same time, with greater flexibility, it can also configure corresponding modes to identify and monitor the quality of the reference clock signal, preventing poor reference clocks from affecting the system signal quality.
[0053] In one embodiment, the intermediate frequency signal conversion module includes a high-pass filter, a second amplifier, a mixer, a second band-pass filter, and a third amplifier connected in sequence. The high-pass filter has a frequency band corresponding to the intermediate frequency signal, and the mixer is configured to mix the intermediate frequency signal amplified by the second amplifier using a local oscillator frequency generated based on a reference clock signal, and output the mixed signal to the band-pass filter. It is understood that after the output signal of the modem passes through the high-pass filter, the intermediate frequency signal conversion module extracts the intermediate frequency signal therefrom. After amplification by the second amplifier, the intermediate frequency signal amplified by the second amplifier is mixed with the local oscillator frequency received by the mixer, and then transmitted to the second band-pass filter for amplification by the third amplifier to generate the corresponding radio frequency.
[0054] Figure 5 This is a schematic diagram of the structure of an upconverter provided in another embodiment of the present application. The figure takes as an example a reference clock including a reference clock signal corresponding to 10 MHz or a reference clock signal corresponding to 50 MHz. For this purpose, two detection branches are provided in the reference clock processing module. Specifically, the output signal provided by the modem is respectively connected to a bandpass filter BPF1, a bandpass filter BPF2, and a high-pass filter HPF1. The output of the bandpass filter BPF1 is connected to the input of the amplifier A1, the output of the amplifier A1 is connected to the input of the power divider PD1, the first output of the power divider PD1 is connected to an input of the radio frequency switch SW1, and the second output of the power divider PD1 is connected to the input of the logarithmic detector LD1.
[0055] The output end of the bandpass filter BPF2 is connected to the input end of the amplifier A2, the output end of the amplifier A2 is connected to the input end of the power divider PD2, the first output end of the power divider PD2 is connected to the other input end of the RF switch SW1, and the second output end of the power divider PD2 is connected to the input end of the logarithmic detector LD2.
[0056] In addition, the output of logarithmic detector LD1 and the output of logarithmic detector LD2 are both connected to hysteresis comparator Com1. Specifically, the output of logarithmic detector LD1 is connected to the non-inverting input of hysteresis comparator Com1, and the output of logarithmic detector LD2 is connected to the inverting input of hysteresis comparator Com1. The output of hysteresis comparator Com1 is connected to the first input interface of the multiplexer.
[0057] Furthermore, the first input interface of multiplexer U1 is also connected to the first control interface of microcontroller U2, the second input interface of multiplexer U1 is connected to the second control interface of microcontroller U2, and the control interface of multiplexer U1 is connected to the third control interface of microcontroller U2. Multiplexer U1 is used to select the input signal connected to the corresponding input interface based on the selection signal output by the third control interface of microcontroller U2, and control RF switch SW1 to open the corresponding channel according to the input signal. The output end of RF switch SW1 is connected to the phase-locked loop module to provide a reference clock signal for the phase-locked loop module.
[0058] The IF signal conversion module includes a high-pass filter (HPF1), amplifier (A3), mixer (Mix1), bandpass filter (BPF3), and amplifier (A4), all connected in sequence. It's conceivable that the frequency band of the high-pass filter (HPF1) corresponds to the IF signal frequency. Therefore, after receiving the output signal from the modem, the high-pass filter (HPF1) selects the IF signal frequency, amplifies it through amplifier (A3), and then feeds it into mixer (Mix1). Mixer (Mix1) mixes the IF signal amplified by amplifier (A3) with the received local oscillator (LO) frequency and outputs it to bandpass filter (BPF3). Amplifier (A4) then amplifies it to generate the corresponding RF frequency. The LO frequency is filtered by bandpass filter (BPF4) before feeding it into mixer (Mix1).
[0059] For example, taking an up-converter of a satellite transmitter operating at 29-30 GHz as an example, the intermediate frequency range of its transmission is 0.95-1.95 GHz, the transmission local oscillator frequency is 28.05 GHz, and the external input reference clock frequency may be 10 MHz or 50 MHz.
[0060] Based on this, in comparator mode, the software firmware in the microcontroller unit pre-compiles the corresponding configuration parameter information, which can be stored in the form of an internal configuration table of the product. After determining the corresponding solution, the corresponding registers of the phase-locked loop are configured according to the parameters in the table to generate the corresponding local oscillator frequency. An example of the corresponding internal configuration table of the product is as follows:
[0061]
[0062] From the above table, we can see that the local oscillator frequency F out With external reference frequency F ref The relationship is as follows:
[0063]
[0064] It can be imagined that, through the corresponding configuration scheme, after determining the reference clock frequency, the up-converter can select the corresponding configuration scheme to configure the register of the phase-locked loop, thereby generating the corresponding local oscillator frequency. The first input interface of the multiplexer U1 is connected to the output end of the hysteresis comparator Com1 to access the electrical signal corresponding to the comparison result (denoted as Vop). The second input interface of the multiplexer U1 is the signal provided by the connected micro-control unit U2 (denoted as Vom). In addition, the control interface of the multiplexer U1 is the third control interface of the connected micro-control unit U2, so that the micro-control unit U2 provides a corresponding selection signal (denoted as Vc_SW) so that the multiplexer U1 outputs one of the connected signals. For example, when the reference clock signal frequency is 10MHz, the voltage value detected by logarithmic detector LD1 is greater than the voltage value detected by logarithmic detector LD2. In response, hysteresis comparator Com1 outputs a high-level signal, that is, Vop is high. Correspondingly, Venc output by microcontroller U2 is low, so that multiplexer U1 outputs the signal connected to its first input interface, so that the RF switch turns on the channel corresponding to the 10MHz reference clock. At this time, Vom output by microcontroller U2 is in a high-impedance state. Microcontroller U2 monitors the level of Vop in real time through high-speed I / O pins. Based on the high and low levels of Vop, it configures the corresponding register parameter information for the phase-locked loop, only configuring the different parts of the phase-locked loop register.
[0065] Based on this, in comparator mode, the mode response speed is very fast. Referring to the response time of the reference logarithmic detector of 10ns, the microcontroller interrupt processing + register configuration time is about 15us, and the phase-locked loop re-locking time is about 150us, so the overall switching time is less than 200us.
[0066] In the ADC comparison mode, this mode is stable and reliable and is not easily affected by interference caused by instantaneous mutations of the reference. The microcontroller unit is provided with a calibration table, which includes various voltages at multiple preset clock frequencies and the power corresponding to each voltage. It is conceivable that different reference clock input powers are calibrated, such as using a logarithmic detector to perform power detection on the reference clock. The advantage of the logarithmic detector is that the response speed is very fast, about 10ns, and it is the fastest power detector among various detectors. For example, the reference power corresponding to the detection voltage of the 10 / 50MHz reference clock is calibrated respectively, and the signal source is used to simulate the reference input, and the output power of the signal source is adjusted so that the reference input power is adjusted in 1dB steps from -25dBm to +10dBm. The ADC inside the MCU records the corresponding voltage value to complete the calibration of the two reference powers, as shown in the following table (only part is shown):
[0067]
[0068]
[0069] The detection interface of the microcontroller unit is respectively connected to the signal voltages of the two detection paths mentioned above, namely the voltage V1 output by the logarithmic detector LD1 and the voltage V2 output by the logarithmic detector LD2. It can be understood that in the ADC comparison mode, the microcontroller unit detects the above voltage V1 and voltage V2, and can determine the corresponding input power P1 and input power P2 according to the calibration ratio table, and then the microcontroller unit compares the power of the input power P1 and the input power P2, and takes the input power that is greater than the threshold and has a larger power as the current reference clock. Optionally, in one embodiment, if the power of both reference clock signals is too low and does not exceed the threshold, the microcontroller unit maintains the current state.
[0070] Microcontroller U2 outputs a high-level signal, Venc. In response, multiplexer U1 outputs the signal connected to its second input interface. This means that microcontroller U2 can reference the RF switch via the output signal Vom. For example, a low-level signal (Vom) causes the RF switch to conduct the channel corresponding to the 10MHz reference clock, while a high-level signal (Vom) causes the RF switch to conduct the channel corresponding to the 50MHz reference clock. When configuring the phase-locked loop (PLL), the microcontroller can configure the corresponding register parameters for the PLL according to the aforementioned product internal configuration table.
[0071] In addition, the microcontroller unit U2 is also provided with a mode for forcing the use of the corresponding reference clock, such as the first forced mode and the second forced mode. In the first forced mode, the microcontroller unit outputs a first control signal, and in response to this, after receiving the first control signal, the radio frequency switch SW1 turns on the channel corresponding to the 10MHz reference clock; in the second forced mode, the microcontroller unit outputs a second control signal, and in response to this, after receiving the second control signal, the radio frequency switch SW1 turns on the channel corresponding to the 50MHz reference clock. It can be understood that in the first forced mode or the second forced mode, the system cannot perform soft switching, which can be used to locate the problem of reference clock failure, and can continue to work even when the logarithmic detector, hysteresis comparator, or system error design configures two reference clocks at the same time.
[0072] An embodiment of the present application also provides a satellite communication system, which includes the up-converter provided by the above embodiment. In this regard, the satellite communication system can adapt to the frequency switching of different reference clocks without the need to design corresponding up-converter structures for different reference clocks, thereby improving the flexibility of the system.
[0073] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.
[0074] Note that the above are only preferred embodiments of the present application and the technical principles employed. Those skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, and substitutions can be made by those skilled in the art without departing from the scope of protection of the present application. Therefore, although the present application has been described in more detail through the above embodiments, the present application is not limited to the above embodiments and may include many other equivalent embodiments without departing from the scope of the present application. The scope of the present application is determined by the scope of the appended claims.
Claims
1. An upconverter, characterized in that: connected to a modem to receive an output signal provided by the modem, the up-converter comprising: An intermediate frequency signal frequency conversion module, wherein the input end of the intermediate frequency signal frequency conversion module is connected to the output signal provided by the modem, and the intermediate frequency signal frequency conversion module is used to amplify and mix the intermediate frequency signal using the local oscillator frequency; a reference clock processing module, wherein multiple input terminals of the reference clock processing module are connected to the output signal provided by the modem, each input terminal of the reference clock processing module corresponds to a detection branch, and the reference clock processing module is configured to detect and compare the frequency and power of the reference clock signal in the output signal provided by the modem through the multiple detection branches to determine the frequency of the reference clock and output a frequency comparison signal; a logic control module, wherein an input end of the logic control module is connected to the detection output end of the reference clock processing module, and the logic control module is used to determine an output control signal based on a frequency comparison signal output by the detection output end of the reference clock processing module; A radio frequency switch, the radio frequency switch comprising a control end, an output end, and multiple input ends, the control end of the radio frequency switch being connected to the control output end of the logic control module, the multiple input ends of the radio frequency switch being connected one-to-one to the multiple output ends of the reference clock processing module, the radio frequency switch being configured to select a reference clock signal connected to a target input end of the radio frequency switch according to the control signal received by the control end of the radio frequency switch and output the reference clock signal through the output end of the radio frequency switch; A phase-locked loop module, wherein the reference input end of the phase-locked loop module is connected to the output end of the radio frequency switch, and the phase-locked loop module is used to generate a local oscillator frequency provided to the intermediate frequency signal frequency conversion module according to the reference clock signal output by the radio frequency switch.
2. The up-converter according to claim 1, wherein: The reference clock processing module includes at least two detection branches, each of which includes a first bandpass filter, a first amplifier, a power divider, and a logarithmic detector; The input end of the first band-pass filter serves as the input end of the detection branch, the output end of the first band-pass filter is connected to the input end of the first amplifier, the output end of the first amplifier is connected to the input end of the power divider, the first output end of the power divider serves as the output end of the detection branch, the second output end of the power divider is connected to the logarithmic detector, the power divider is used to split the signal power into two paths, and the logarithmic detector is used to detect the power intensity of the signal; The first band-pass filters in different detection branches correspond to different frequency bands.
3. The up-converter according to claim 2, wherein: The reference clock processing module also includes a frequency comparison unit, which includes multiple input terminals. Each input terminal of the frequency comparison unit is respectively connected to the output terminal of the logarithmic detector in a different detection branch. The output terminal of the frequency comparison unit serves as the detection output terminal of the reference clock processing module. The frequency comparison unit is used to determine the voltage output by all logarithmic detectors to output a frequency comparison signal.
4. The up-converter according to claim 3, wherein: In the case where there are two detection branches, the frequency comparison unit includes a first hysteresis comparator, a non-inverting input terminal of the first hysteresis comparator is connected to the output terminal of the logarithmic detector in one detection branch, and an inverting input terminal of the first hysteresis comparator is connected to the output terminal of the logarithmic detector in the other detection branch; or, In the case where there are three detection branches, the frequency comparison unit includes an adder, a second hysteresis comparator and a third hysteresis comparator; The output end of the logarithmic detector of the first detection branch and the output end of the logarithmic detector of the second detection branch are respectively connected to the two input ends of the adder, the output end of the adder is connected to the non-inverting input end of the second hysteresis comparator, and the output end of the logarithmic detector of the third detection branch is connected to the inverting input end of the second hysteresis comparator; The output end of the logarithmic detector of the first detection branch is also connected to the non-inverting input end of the third hysteresis comparator, and the output end of the logarithmic detector of the second detection branch is also connected to the inverting input end of the third hysteresis comparator. The output end of the third hysteresis comparator and the output end of the second hysteresis comparator both serve as the output end of the frequency comparison unit.
5. The up-converter according to claim 1, wherein: The logic control module includes a multiplexing unit and a micro control unit; The first input end of the multiplexing unit is connected to the output end of the reference clock processing module, and the output end of the multiplexing unit is connected to the control end of the radio frequency switch, and the first input end of the multiplexing unit is also connected to the first control interface of the micro control unit; The second control interface of the microcontroller unit is connected to the second input end of the multiplexing unit, and the third control interface of the microcontroller unit is connected to the control end of the multiplexing unit. The microcontroller unit is used to determine the signal output through the first control interface and the signal output through the third control interface according to the frequency comparison signal to control the radio frequency switch to open the corresponding channel.
6. The up-converter according to claim 5, characterized in that: In the case where there are two detection branches, the multiplexing unit includes a multiplexer, and the multiplexer includes two input interfaces; Among them, the first input interface of the multiplexer is connected to the detection output end of the reference clock processing module and the first control interface of the micro control unit, the second input interface of the multiplexer is also connected to the second control interface of the micro control unit, and the control interface of the multiplexer is connected to the third control interface of the micro control unit. The multiplexer is used to select the input signal connected to the corresponding input interface according to the selection signal output by the third control interface of the micro control unit, so as to control the radio frequency switch to open the corresponding channel according to the input signal.
7. The up-converter according to claim 5, characterized in that: In the case where there are three detection branches, the multiplexing unit includes two multiplexers, and each of the multiplexers includes two input interfaces; Among them, the first input interface of each of the multiplexers is correspondingly connected to different detection output ends on the reference clock processing module and different first control interfaces on the micro control unit, the second input interface of each of the multiplexers is correspondingly connected to different second control interfaces on the micro control unit, and the control interface of each of the multiplexers is correspondingly connected to different third control interfaces on the micro control unit. The two multiplexers are used to select the input signals connected to the corresponding two input interfaces according to the two selection signals output by different third control interfaces on the micro control unit, so as to control the RF switch to open the corresponding channel according to the two input signals.
8. The up-converter according to claim 5, characterized in that: The micro control unit is provided with a comparator mode, an ADC comparison mode, a first forced mode and a second forced mode; In the comparator mode, the microcontroller is provided with configuration parameter information of two corresponding phase-locked loop modules, and the microcontroller is used to select the corresponding configuration parameter information according to the frequency comparison signal and configure the phase-locked loop module; In the ADC comparison mode, the detection interface of the microcontroller is respectively connected to the signal voltage of each detection branch. The microcontroller is used to determine the power according to a preset calibration table, and output a target control signal in the presence of a target reference clock signal with maximum power and power greater than a threshold, so that the radio frequency switch selects the channel corresponding to the target reference clock signal. The calibration table includes each voltage at a plurality of preset clock frequencies and the power corresponding to each voltage. In the first forced mode, the micro control unit outputs a first control signal, where the first control signal is used to enable the radio frequency switch to select a channel corresponding to the first reference clock signal; In the second forced mode, the micro control unit outputs a second control signal, where the second control signal is used to enable the radio frequency switch to select a channel corresponding to the second reference clock signal.
9. The up-converter according to any one of claims 1 to 8, characterized in that: The intermediate frequency signal frequency conversion module includes a high-pass filter, a second amplifier, a mixer, a second band-pass filter and a third amplifier connected in sequence, wherein the mixer is used to use the received local oscillator frequency generated based on the reference clock signal to mix the intermediate frequency signal amplified by the second amplifier and output it to the second band-pass filter.
10. A satellite communication system, characterized in that: The device comprises an up-converter as claimed in any one of claims 1 to 9.