Peak current detection circuit based on general comparator

Abstract

The utility model relates to the technical field of peak current detection, in particular to a peak current detection circuit based on a general comparator, which comprises a PWM (Pulse Width Modulation) controller, an MOS (Metal Oxide Semiconductor) tube, a current detection circuit and a filter circuit, a driving waveform output end of the PWM controller is connected with a G pin of the MOS tube, a D pin of the MOS tube is connected with current input, an S pin of the MOS tube is connected to the current detection circuit, a comparator is arranged in the current detection circuit, an output end of the comparator outputs a CS signal through the filter circuit, and the PWM controller is configured to stop sending a driving waveform to the MOS tube when the received CS signal exceeds a set range. According to the utility model, the general comparator is adopted to detect peak current, the cost is lower, the layout is simpler, the PCB layout difficulty is greatly reduced, and the circuit has the advantages of sensitive response, high measurement precision and small temperature excursion; according to the utility model, the DC step blanking circuit is added in the circuit to absorb the negative voltage in the CS signal, so that the safety of the circuit can be ensured.

Description

Technical Field

[0001] The utility model relates to the technical field of peak current detection, in particular to a peak current detection circuit based on a universal comparator. Background Art

[0002] In the field of electronics, peak current detection is necessary to control output current and protect power devices. Peak current detection is a commonly used technology in monitoring and protection. Accurately measuring and monitoring peak current in power systems can help identify faults and anomalies, and assess system load and stability. This technology is crucial for ensuring the safe operation of power systems.

[0003] Peak current detection technology has a wide range of applications in modern industry, including power management systems, overcurrent protection circuits, programmable current sources, linear and switch-mode power supplies, and battery chargers. With the continuous advancement of science and technology, the requirements for signal measurement and processing are becoming increasingly stringent. Peak detection circuits, as an important signal processing technology, have a positive impact on the development of electronic technology. Through the research and application of peak detection circuits, the accuracy and efficiency of signal processing can be continuously improved, thereby promoting the development of the entire field of electronic technology.

[0004] Chinese invention patent publication number CN112595880A provides a low-energy consumption sampling resistor-free peak current detection circuit, and Chinese invention patent publication number CN112180143A provides a power supply modulation circuit with peak current detection function. Both of the above-mentioned existing technologies use operational amplifiers for current detection. In addition, transformers are also commonly used for current detection. However, transformers and operational amplifiers are expensive, resulting in high current detection costs. Utility Model Content

[0005] The purpose of this utility model is to provide a peak current detection circuit based on a universal comparator. The comparator is used for current detection. Compared with mutual inductors and operational amplifiers, it is inexpensive and can completely replace their functions to solve the problem of high cost of existing current detection.

[0006] The embodiment of the utility model is realized by the following technical solution: a peak current detection circuit based on a universal comparator, comprising a PWM controller, a MOS tube Q2, a current detection circuit and a filter circuit;

[0007] The drive waveform output terminal of the PWM controller is connected to the G pin of the MOS transistor, the D pin of the MOS transistor Q2 is connected to the current input, and the S pin of the MOS transistor Q2 is connected to the current detection circuit. The current detection circuit has a built-in comparator, and the output terminal of the comparator outputs a CS signal through a filtering circuit. The PWM controller is configured to stop sending the drive waveform to the MOS transistor Q2 when the received CS signal exceeds a set range.

[0008] According to a preferred embodiment, the current detection circuit is composed of a current detection resistor R7, a comparator U1 and a pull-up resistor R1;

[0009] The S pin of the MOS transistor Q2 is connected to the 1 pin of the comparator U1 via the first end of the current-sense resistor R7. The second end of the current-sense resistor R7 is grounded. The 4 pins of the comparator U1 are respectively connected to the filter circuit and the first end of the pull-up resistor R1. The 2 pin of the comparator U1 is grounded. The 5 pin of the comparator U1 and the second end of the pull-up resistor R1 are both connected to the current positive analog input V5P. The comparator U1 is configured to compare the peak current sampled by the current-sense resistor R7 with a reference voltage and output a CS signal to the filter circuit via the 4 pin.

[0010] According to a preferred embodiment, the current detection circuit also includes a gain adjustment resistor R5 and a gain adjustment resistor R6, and pin 3 of the comparator U1 is respectively connected to the first ends of the gain adjustment resistor R5 and the gain adjustment resistor R6, the second end of the gain adjustment resistor R5 is grounded, and the second end of the gain adjustment resistor R6 is connected between the first end of the pull-up resistor R1 and pin 4 of the comparator U1.

[0011] According to a preferred embodiment, the filter circuit is composed of a capacitor C1, a capacitor C2, a resistor R2 and a resistor R3;

[0012] Among them, the first end of the capacitor C1 is connected to the 4th pin of the comparator U1, the second end of the capacitor C2 is respectively connected to the DC step blanking circuit, the first end of the resistor R3 and the first end of the resistor R2, the second ends of the capacitor C2 and the resistor R2 are both connected to the CS signal output port, and the second ends of the resistor R3 and the capacitor C2 are both grounded.

[0013] According to a preferred embodiment, a DC step blanking circuit is further included. The DC step blanking circuit has a built-in transistor, which is connected to the drive waveform output end of the PWM controller. The transistor is also connected to the filter circuit. The DC step blanking circuit is configured to absorb the negative voltage of the CS signal.

[0014] According to a preferred embodiment, the DC step blanking circuit is composed of a transistor Q1, a capacitor C3, a diode D1 and a resistor R4;

[0015] Among them, the first end of the capacitor C3 is connected to the driving waveform output end of the PWM controller, and the second end of the capacitor C3 is connected to the b pin of the transistor Q1 via the diode D1 and the first end of the resistor R4 in sequence. The second ends of the diode D1, the resistor R4 and the c pin of the transistor Q1 are all grounded. The e pin of the transistor Q1 is connected to the filter circuit. The transistor Q1 is configured to pull down the b pin when the driving waveform issued by the PWM controller is at a low level, and the transistor Q1 is turned on and forms a charging circuit with the capacitor C3, the diode D1 and the resistor R4.

[0016] The technical solution of a peak current detection circuit based on a universal comparator provided by the present invention has at least the following advantages and beneficial effects: (1) The present invention adopts a universal comparator to detect peak current instead of the traditional current detection by a transformer and an operational amplifier, which has lower cost and simpler layout, greatly reduces the difficulty of PCB layout, and has the advantages of sensitive response, high measurement accuracy and small temperature drift, and can perfectly replace the traditional current detection method; (2) A DC step blanking circuit is added to the circuit to absorb the negative voltage in the CS signal, thereby ensuring the safety of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A simplified structural diagram of a peak current detection circuit based on a universal comparator provided in Example 1 of the present utility model;

[0018] Figure 2 A simplified structural diagram of a peak current detection circuit based on a universal comparator provided in Example 2 of the present utility model;

[0019] Figure 3 This is a schematic diagram of the overall structure of a peak current detection circuit based on a universal comparator provided in Example 3 of the present utility model;

[0020] Figure 4 This is a schematic diagram of the overall structure of a peak current detection circuit based on a universal comparator provided in Example 4 of the present utility model;

[0021] Figure 5 This is a schematic diagram of the overall structure of a peak current detection circuit based on a universal comparator provided in Example 5 of the present utility model. DETAILED DESCRIPTION

[0022] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0023] Example 1

[0024] Figure 1 This is a simplified structural diagram of a peak current detection circuit based on a universal comparator provided by an embodiment of the present utility model. Figure 1 As shown, the peak current detection circuit includes a PWM controller, a MOS tube Q2, a current detection circuit and a filter circuit.

[0025] More specifically, the D pin of the MOS transistor Q2 is connected to a current input, the drive waveform output end of the PWM controller is connected to the G pin of the MOS transistor (i.e., the gate of the MOS transistor), and the S pin of the MOS transistor Q2 is connected to a current detection circuit. In this embodiment, the MOS transistor acts as a switch for controlling current. A voltage is applied to the MOS transistor by a drive waveform to control the conduction state between the source (i.e., the S pin of the MOS transistor) and the drain (i.e., the D pin of the MOS transistor).

[0026] In this embodiment, the current-sensing circuit incorporates a built-in comparator, replacing traditional current-sensing methods using transformers and operational amplifiers. This reduces cost, simplifies layout, and significantly reduces the complexity of PCB layout. Specifically, the comparator compares the peak current collected by the pre-processor components with a reference voltage to generate an output CS signal. Preferably, the output of the comparator outputs the CS signal through a filtering circuit that feeds it back to the PWM controller. The filtering circuit absorbs interference glitches on the CS signal, resulting in a smoother CS signal.

[0027] Specifically, the PWM controller is configured to stop sending the driving waveform to the MOS transistor Q2 when the received CS signal exceeds a set range, thereby protecting the circuit.

[0028] Example 2

[0029] This embodiment is based on the technical solution provided in Example 1, and further improves the technical solution. The improvements are described in detail below:

[0030] See also Figure 2 As shown, in this embodiment, the peak current detection circuit further includes a DC step blanking circuit;

[0031] In one possible implementation, the DC step blanking circuit has a built-in transistor; the transistor is connected to the drive waveform output end of the PWM controller, and the transistor is also connected to the filter circuit. The DC step blanking circuit is configured to absorb the negative voltage of the CS signal, which is crucial to circuit safety and can protect the PWM controller and ensure circuit safety.

[0032] Example 3

[0033] This embodiment further explains the current detection circuit based on the technical solution provided in Example 1:

[0034] See also Figure 3 As shown, in this embodiment, the current detection circuit is composed of a current detection resistor R7, a comparator U1 and a pull-up resistor R1.

[0035] The S pin of the MOS transistor Q2 is connected to the 1 pin of the comparator U1 via the first end of the current-sense resistor R7. The second end of the current-sense resistor R7 is grounded. The 4 pins of the comparator U1 are respectively connected to the filter circuit and the first end of the pull-up resistor R1. The 2 pin of the comparator U1 is grounded. The 5 pin of the comparator U1 and the second end of the pull-up resistor R1 are both connected to the current positive analog input V5P. The comparator U1 is configured to compare the peak current sampled by the current-sense resistor R7 with a reference voltage and output a CS signal to the filter circuit via the 4 pin.

[0036] Furthermore, in this embodiment, the current detection circuit also includes a gain adjustment resistor R5 and a gain adjustment resistor R6, and pin 3 of the comparator U1 is respectively connected to the first ends of the gain adjustment resistor R5 and the gain adjustment resistor R6, the second end of the gain adjustment resistor R5 is grounded, and the second end of the gain adjustment resistor R6 is connected between the first end of the pull-up resistor R1 and pin 4 of the comparator U1.

[0037] It should be noted that the general comparator has a sensitive and fast response speed, and the comparison threshold can be flexibly changed by adjusting the gain resistor. Therefore, the peak current detection circuit provided in this embodiment has the advantages of sensitive response, high measurement accuracy and small temperature drift, and can perfectly replace the traditional current detection method.

[0038] Example 4

[0039] This embodiment further explains the filtering circuit based on the technical solution provided in Example 3:

[0040] See also Figure 4 As shown, in this embodiment, the filter circuit is composed of a capacitor C1, a capacitor C2, a resistor R2 and a resistor R3.

[0041] Among them, the first end of the capacitor C1 is connected to the 4th pin of the comparator U1, the second end of the capacitor C2 is respectively connected to the DC step blanking circuit, the first end of the resistor R3 and the first end of the resistor R2, the second ends of the capacitor C2 and the resistor R2 are both connected to the CS signal output port, and the second ends of the resistor R3 and the capacitor C2 are both grounded.

[0042] Example 5

[0043] This embodiment further describes the DC step blanking circuit based on the technical solution provided in Example 4:

[0044] See also Figure 5 As shown, in this embodiment, the DC step blanking circuit is composed of a transistor Q1, a capacitor C3, a diode D1 and a resistor R4.

[0045] The first end of the capacitor C3 is connected to the drive waveform output end of the PWM controller, and the second end of the capacitor C3 is connected to the b pin of the transistor Q1 via the diode D1 and the first end of the resistor R4 in sequence. The second ends of the diode D1, the resistor R4, and the c pin of the transistor Q1 are all grounded. The e pin of the transistor Q1 is connected to the filter circuit. The transistor Q1 is configured to pull the b pin low when the drive waveform issued by the PWM controller is at a low level. The transistor Q1 is turned on and forms a charging circuit with the capacitor C3, the diode D1, and the resistor R4 to absorb the negative voltage of the CS signal.

[0046] In addition, it is worth mentioning that the technical solution provided in this embodiment is applicable to various single power tube topologies, such as BUCK, BOOST, flyback, forward, etc., and has a wide range of applications.

[0047] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Those skilled in the art will readily appreciate that the present invention is susceptible to various modifications and variations. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A peak current detection circuit based on a universal comparator, characterized in that: Including PWM controller, MOS tube Q2, current detection circuit and filter circuit; The drive waveform output terminal of the PWM controller is connected to the G pin of the MOS transistor, the D pin of the MOS transistor Q2 is connected to the current input, and the S pin of the MOS transistor Q2 is connected to the current detection circuit. The current detection circuit has a built-in comparator, and the output terminal of the comparator outputs a CS signal through a filtering circuit. The PWM controller is configured to stop sending the drive waveform to the MOS transistor Q2 when the received CS signal exceeds a set range.

2. The peak current detection circuit based on a universal comparator according to claim 1, characterized in that: The current detection circuit is composed of a current detection resistor R7, a comparator U1 and a pull-up resistor R1; The S pin of the MOS transistor Q2 is connected to the 1 pin of the comparator U1 via the first end of the current-sense resistor R7. The second end of the current-sense resistor R7 is grounded. The 4 pins of the comparator U1 are respectively connected to the filter circuit and the first end of the pull-up resistor R1. The 2 pin of the comparator U1 is grounded. The 5 pin of the comparator U1 and the second end of the pull-up resistor R1 are both connected to the current positive analog input V5P. The comparator U1 is configured to compare the peak current sampled by the current-sense resistor R7 with a reference voltage and output a CS signal to the filter circuit via the 4 pin.

3. The peak current detection circuit based on a universal comparator as claimed in claim 2, characterized in that: The current detection circuit also includes a gain adjustment resistor R5 and a gain adjustment resistor R6. Pin 3 of the comparator U1 is connected to the first ends of the gain adjustment resistor R5 and the gain adjustment resistor R6, respectively. The second end of the gain adjustment resistor R5 is grounded. The second end of the gain adjustment resistor R6 is connected between the first end of the pull-up resistor R1 and pin 4 of the comparator U1.

4. The peak current detection circuit based on a universal comparator according to claim 1, wherein: The filter circuit is composed of capacitor C1, capacitor C2, resistor R2 and resistor R3; Among them, the first end of the capacitor C1 is connected to the 4th pin of the comparator U1, the second end of the capacitor C2 is respectively connected to the DC step blanking circuit, the first end of the resistor R3 and the first end of the resistor R2, the second ends of the capacitor C2 and the resistor R2 are both connected to the CS signal output port, and the second ends of the resistor R3 and the capacitor C2 are both grounded.

5. The peak current detection circuit based on a universal comparator according to any one of claims 1 to 4, characterized in that: It also includes a DC step blanking circuit, which has a built-in triode. The triode is connected to the driving waveform output end of the PWM controller and is also connected to the filter circuit.

6. The peak current detection circuit based on a universal comparator as claimed in claim 5, characterized in that: The DC step blanking circuit is composed of a transistor Q1, a capacitor C3, a diode D1 and a resistor R4; Among them, the first end of the capacitor C3 is connected to the driving waveform output end of the PWM controller, and the second end of the capacitor C3 is connected to the b pin of the transistor Q1 via the diode D1 and the first end of the resistor R4 in sequence. The second end of the diode D1, the resistor R4 and the c pin of the transistor Q1 are all grounded, and the e pin of the transistor Q1 is connected to the filter circuit. The transistor Q1 is configured to pull the b pin low when the driving waveform issued by the PWM controller is at a low level.

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