Chip packaging structure

Abstract

The utility model discloses a chip packaging structure. The chip packaging structure comprises a photonic integrated circuit chip. The photonic integrated circuit chip comprises a dielectric structure, an optical detector, an optical modulator and a first waveguide structure in the dielectric structure. The photodetector and the light modulator are connected to the first waveguide structure. The chip package structure includes an electronic integrated circuit chip over a photonic integrated circuit chip. The chip package structure includes an optical transport chip over a photonic integrated circuit chip. The optical transmission chip comprises a substrate, a second waveguide structure and a first reflection structure.

Description

Technical Field

[0001] The utility model relates to a chip packaging structure, in particular to an optical engine packaging structure. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconducting layers on a semiconductor substrate and patterning the various material layers using photolithography and etching processes to form circuit elements and components thereon.

[0003] Many integrated circuits (ICs) are typically manufactured on semiconductor wafers. Technological advances in IC materials and design have resulted in generations of ICs. Each generation has smaller and more complex circuits than the previous one. Chips on a wafer can be processed and packaged at the wafer level, and various technologies have been developed for wafer-level packaging. Because a chip package structure may need to include multiple chips with multiple functions, how to form a reliable chip package structure using multiple chips is a challenge. Utility Model Content

[0004] The purpose of the present invention is to provide a chip packaging structure to solve at least one of the above problems.

[0005] Some embodiments of the present invention provide a chip packaging structure. The chip packaging structure includes a photonic integrated circuit chip, an electronic integrated circuit chip, and an optical transmission chip. The photonic integrated circuit chip includes a dielectric structure, a light detector, an optical modulator, and a first waveguide structure in the dielectric structure. The light detector and the optical modulator are connected to the first waveguide structure. The electronic integrated circuit chip is located above the photonic integrated circuit chip. The electronic integrated circuit chip includes a transistor. The optical transmission chip is located above the photonic integrated circuit chip. The optical transmission chip includes a substrate, a second waveguide structure, and a first reflective structure. The second waveguide structure and the first reflective structure are located between the substrate and the photonic integrated circuit chip, and a first angle between a first upper surface of the second waveguide structure and a first sidewall of the first reflective structure is greater than 90 degrees and less than 180 degrees, and the first sidewall is adjacent to the second waveguide structure.

[0006] According to one embodiment of the present invention, the invention further includes: a dielectric layer located in the first reflective structure.

[0007] According to one embodiment of the present invention, a width of the dielectric layer decreases toward the substrate of the light transmission chip.

[0008] According to one embodiment of the present invention, it further includes a third waveguide structure located above the substrate of the optical transmission chip; and a second reflective structure located above the substrate of the optical transmission chip, wherein a second angle between a second upper surface of the third waveguide structure and a second sidewall of the second reflective structure is greater than 0 degrees and less than 90 degrees, and the second sidewall is adjacent to the third waveguide structure.

[0009] Other embodiments of the present invention provide a chip packaging structure. The chip packaging structure includes a photonic integrated circuit chip, an electronic integrated circuit chip, and an optical transmission chip. The photonic integrated circuit chip includes a dielectric structure, a light detector, an optical modulator, and a first waveguide structure located in the dielectric structure. The light detector and the optical modulator are coupled to the first waveguide structure. The electronic integrated circuit chip is located above the photonic integrated circuit chip. The electronic integrated circuit chip includes a transistor. The optical transmission chip is located above the photonic integrated circuit chip. The optical transmission chip includes a substrate, a second waveguide structure, and a first reflective structure. The second waveguide structure and the first reflective structure are located between the substrate and the photonic integrated circuit chip, and the second waveguide structure and the first reflective structure are adjacent to each other. The first reflective structure has a first sidewall and a second sidewall opposite to the first sidewall, and a first distance between the first sidewall and the second sidewall decreases toward the substrate.

[0010] According to one embodiment of the present invention, it also includes: a second reflective structure located above the substrate of the optical transmission chip, wherein the second reflective structure has a third sidewall and a fourth sidewall opposite to the third sidewall, and a second distance between the third sidewall and the fourth sidewall decreases toward the substrate.

[0011] According to one embodiment of the present invention, the first sidewall of the first reflective structure overlaps with the fourth sidewall of the second reflective structure in a direction perpendicular to a lower surface of the substrate of the optical transmission chip.

[0012] Still other embodiments of the present invention provide a chip packaging structure. The chip packaging structure includes a photonic integrated circuit chip, an electronic integrated circuit chip, and an optical transmission chip. The photonic integrated circuit chip includes a dielectric structure, a light detector, an optical modulator, and a first waveguide structure located within the dielectric structure. The light detector and the optical modulator are coupled to the first waveguide structure. The electronic integrated circuit chip is located above the photonic integrated circuit chip. The electronic integrated circuit chip includes a transistor. The optical transmission chip is located above the photonic integrated circuit chip. The optical transmission chip includes a substrate and a second waveguide structure. The second waveguide structure is located between the substrate and the photonic integrated circuit chip. The substrate has a first convex surface facing the photonic integrated circuit chip, and the second waveguide structure is located between the first convex surface and the photonic integrated circuit chip.

[0013] According to one embodiment of the present invention, the device further comprises: a first reflective structure located between the first convex surface and the photonic integrated circuit chip and adjacent to the second waveguide structure. According to one embodiment of the present invention, the device further comprises: a support chip located above the electronic integrated circuit chip and the optical transmission chip, wherein the support chip has a second convex surface facing away from the optical transmission chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The following describes embodiments of the present invention in detail with reference to the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of various features may be arbitrarily enlarged or reduced for clarity of discussion.

[0015] Figure 1A is a cross-sectional view of a chip packaging structure according to some embodiments.

[0016] Figure 1B is a flowchart of a method for implementing a chip packaging structure according to some embodiments.

[0017] Figure 1C yes Figure 1A A top view of ends of two lowermost waveguide layers of a chip package structure according to some embodiments.

[0018] Figure 2 is a cross-sectional view of a chip packaging structure according to some embodiments.

[0019] Figure 3 is a cross-sectional view of a chip packaging structure according to some embodiments.

[0020] Figure 4 is a cross-sectional view of a chip packaging structure according to some embodiments.

[0021] Figure 5 is a cross-sectional view of a chip packaging structure according to some embodiments.

[0022] The reference numerals are as follows:

[0023] 10: Method

[0024] 11,12,13,14,15,16,17,18: Operation

[0025] 100, 200, 300, 400, 500: chip packaging structure

[0026] 101,105,106,108,112,122a,123,133,136,137,161,164,185,186a,186d,190,268,263a,263d,267a,267d,320: Dielectric layer

[0027] 102,115,115a: Waveguide layer

[0028] 102a, 102b, 102c, 131e, 181e: Part

[0029] 102c1,115a1: tapered end

[0030] 103; Photodetector

[0031] 104: Optical modulator

[0032] 109: Interconnection structure

[0033] 109a: wiring layer

[0034] 109b: conductive via

[0035] 110: Photonic integrated circuit chip

[0036] 110d: Dielectric structure

[0037] 113,138,124,269: Bonding pads

[0038] 114: conductive through hole

[0039] 120: Electronic integrated circuit chips

[0040] 120a, 265c: Top surface

[0041] 121,131,181,261,265a:Substrate

[0042] 121a: front surface

[0043] 122b: Transistor

[0044] 122: Device layer

[0045] 125,230: conductive vias

[0046] 130: Optical transmission chip

[0047] 131a: lower surface

[0048] 131b, 131c, 131d, 181b, 181d, 181f: convex surfaces

[0049] 132,150,183,184,262,266,310: Anti-reflective layer

[0050] 133a,131r,181r: groove

[0051] 134a, 162a, 181c: Upper surface

[0052] 135,163,186c,263c,267c: Reflective structures

[0053] 135a, 135b, 163a, 163b: Sidewall

[0054] 140: Molding layer

[0055] 160, 260, 263, 267, 186: Optical transmission structure

[0056] 170,182,264,265b: Bonding layer

[0057] 180:Support chip

[0058] 181a,101a,192,261a,261b,265a1: Surface

[0059] 210: Conductive plug

[0060] 220: Wiring layer

[0061] 240: Conductive pad

[0062] 250: conductive bump

[0063] 265: Virtual Chip

[0064] D135, D163: Distance

[0065] L, L1, L2: optical signal

[0066] V1: Direction

[0067] WG,134,162,186b,263b,267b: waveguide structure

[0068] W136, W164: Width

[0069] θ1,θ2: angle DETAILED DESCRIPTION

[0070] The following disclosure provides many different embodiments or examples for implementing different components of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these examples are merely examples and do not limit the present invention. For example, if the specification describes that a first component is formed above or on a second component, it means that it may include an embodiment in which the first component and the second component are in direct contact, and may also include an embodiment in which an additional component is formed between the first component and the second component, so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference element symbols and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself specify the relationship between the various embodiments and / or configurations discussed.

[0071] In addition, spatially relative terms are used. For example, "below," "beneath," "below," "above," "upper," and similar terms are used to facilitate describing the relationship between one element or component and another element or component in the drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the drawings. When the device is rotated 90 degrees or in other orientations, the spatially relative adjectives used therein will also be interpreted based on the rotated orientation.

[0072] Several embodiments of the present invention have been described. Additional operations may be provided before, during, and / or after the stages described in these embodiments. Some of the described stages may be replaced or eliminated for different embodiments. Additional features may be added to the semiconductor device structure. Some of the components described below may be replaced or eliminated for different embodiments. Although some embodiments discuss operations performed in a specific order, these operations may be performed in another logical order.

[0073] This method (for forming a chip package structure) incorporates an additional optical transmission chip within the optical engine package structure to alter the optical path, thereby reducing the optical path length and path loss of the optical signal. This method (for forming a chip package structure) also incorporates a convex lens within the optical engine package structure to focus the optical signal, thereby reducing path loss.

[0074] Figure 1A is a cross-sectional view of a chip packaging structure according to some embodiments. Figure 1B is a flowchart of a method for implementing a chip packaging structure according to some embodiments.

[0075] like Figure 1A and Figure 1BAs shown, according to some embodiments, method 10 begins at operation 11, providing a photonic integrated circuit chip 110. According to some embodiments, the photonic integrated circuit chip 110 may include a dielectric structure 110d, one or more photodetectors 103, one or more optical modulators 104, an interconnect structure 109, a bonding pad 113, a conductive via 114, and a waveguide structure WG. It is noted that for simplicity, Figure 1A Only one of the light modulators 104 and one of the photodetectors 103 are shown for illustration, but the present invention is not limited thereto.

[0076] According to some embodiments, the photodetector 103, the optical modulator 104, the interconnect structure 109, the bonding pad 113, the conductive via 114, and the waveguide structure WG are located in a dielectric structure 110d. Specifically, according to some embodiments, the dielectric structure 110d includes dielectric layers 101, 105, 106, 108, and 112. According to some embodiments, the dielectric layers 105, 106, 108, and 112 are stacked sequentially above the dielectric layer 101.

[0077] According to some embodiments, the waveguide structure WG includes waveguide layers 102 and 115. According to some embodiments, the waveguide layer 102 is formed above the dielectric layer 101. According to some embodiments, the waveguide layer 102 includes portions 102a, 102b, and 102c. According to some embodiments, the photodetector 103 and the optical modulator 104 are formed above the portions 102a and 102b, respectively. According to some embodiments, the photodetector 103 and the optical modulator 104 are coupled to (or connected to) the waveguide structure WG.

[0078] According to some embodiments, each photodetector 103 is configured to receive an optical signal transmitted through the waveguide structure WG and convert the optical signal into an electrical signal. According to some embodiments, each optical modulator 104 is configured to receive an electrical signal and convert the electrical signal into an optical signal.

[0079] According to some embodiments, in the photonic integrated circuit chip 110, optical signals are transmitted via the waveguide structure WG, and electrical signals are transmitted via the interconnect structure 109, the bonding pads 113, and the conductive vias 114. According to some embodiments, the waveguide layer 102 is made of a semiconductor material such as silicon.

[0080] According to some embodiments, each photodetector 103 has a left portion, a middle portion, and a right portion. According to some embodiments, the left portion is made of a semiconductor material (e.g., silicon) having a P-type dopant. According to some embodiments, the P-type dopant includes a Group IIIA element. The Group IIIA element includes boron or other suitable materials.

[0081] According to some embodiments, the middle portion is made of an alloy semiconductor material (e.g., silicon germanium). According to some embodiments, the right portion is made of a semiconductor material (e.g., silicon) having an N-type dopant. According to some embodiments, the N-type dopant includes a Group VA element. The Group VA element includes phosphorus (P), antimony (Sb), or another suitable Group VA material.

[0082] According to some embodiments, each optical modulator 104 has a left portion and a right portion. According to some embodiments, the left portion is made of a semiconductor material (e.g., silicon) having a P-type dopant. According to some embodiments, the P-type dopant includes a Group IIIA element. The Group IIIA element includes boron or other suitable materials.

[0083] According to some embodiments, the right portion is made of a semiconductor material (e.g., silicon) having an N-type dopant. According to some embodiments, the N-type dopant includes a Group VA element. The Group VA element includes phosphorus (P), antimony (Sb), or another suitable Group VA material.

[0084] According to some embodiments, dielectric layer 105 is formed over dielectric layer 101. According to some embodiments, waveguide layer 102, photodetector 103, and optical modulator 104 are located in dielectric layer 105. According to some embodiments, dielectric layer 106 is formed over dielectric layer 105, photodetector 103, and optical modulator 104.

[0085] According to some embodiments, interconnect structure 109 includes wiring layers 109a and conductive vias 109b. According to some embodiments, conductive vias 109b connect between wiring layers 109a, between the lowest wiring layer 109a and photodetector 103, and between the lowest wiring layer 109a and optical modulator 104.

[0086] According to some embodiments, some of the lowermost conductive vias 109 b pass through the dielectric layer 106 to electrically connect the lowermost wiring layer 109 a to the photodetector 103 , while other lowermost conductive vias 109 b pass through the dielectric layer 106 to electrically connect the lowermost wiring layer 109 a to the optical modulator 104 .

[0087] In accordance with some embodiments, dielectric layer 108 is formed over dielectric layer 106. In accordance with some embodiments, interconnect structure 109 is located in dielectric layer 108. In accordance with some embodiments, dielectric layer 112 is formed over dielectric layer 108 and interconnect structure 109.

[0088] According to some embodiments, dielectric layers 101, 105, 106, 108, and 112 are made of a dielectric material, such as an oxide-containing material (e.g., silicon oxide or tetraethyl orthosilicate (TEOS) oxide), a nitrogen-containing oxide material (e.g., silicon oxynitride), a glass material (e.g., borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or fluorinated silicate glass (FSG)), or a combination thereof. Alternatively, according to some embodiments, dielectric layers 101, 105, 106, 108, and 112 include a low-k material or a porous dielectric material having a k value lower than that of silicon oxide, or lower than approximately 3.0 or approximately 2.5.

[0089] The dielectric layers 101 , 105 , 106 , 108 and 112 are formed using a chemical vapor deposition (CVD) process, such as a low pressure chemical vapor deposition process, a plasma assisted chemical vapor deposition process, a high density plasma chemical vapor deposition process, an atomic layer deposition process, a spin coating process, a physical vapor deposition process, or other suitable processes.

[0090] According to some embodiments, interconnect structure 109 is made of a conductive material such as metal (eg, copper, aluminum, gold, silver, or tungsten) or alloys thereof.

[0091] According to some embodiments, bonding pad 113 and conductive via 114 are formed in dielectric layer 112. According to some embodiments, conductive via 114 connects bonding pad 113 and interconnect structure 109. According to some embodiments, bonding pad 113 and conductive via 114 are made of a conductive material such as metal (e.g., copper, aluminum, gold, silver, or tungsten) or alloys thereof.

[0092] According to some embodiments, waveguide layer 115 is formed in dielectric layers 106, 108, and 112. According to some embodiments, Figure 1C yes Figure 1A A top view of the ends of the two lowest waveguide layers of the chip packaging structure. Figure 1A and Figure 1C As shown, according to some embodiments, portion 102c of waveguide layer 102 has a tapered end 102c1, and a lowermost waveguide layer 115a of waveguide layer 115 has a tapered end 115a1. According to some embodiments, tapered end 115a1 overlaps tapered end 102c1.

[0093] In some embodiments, the tapered end portion 102c1 serves as an input port for receiving the optical signal L1. In some other embodiments, the tapered end portion 102c1 serves as an output port for outputting the optical signal L2.

[0094] In some embodiments, the tapered end portion 115a1 serves as an input port for receiving the optical signal L2. In some embodiments, the tapered end portion 115a1 serves as an output port for outputting the optical signal L1.

[0095] In some embodiments, optical signal L1 is transmitted from waveguide layer 115a to waveguide layer 102 via tapered end 115a1 and tapered end 102c1. In some other embodiments, optical signal L2 is transmitted from waveguide layer 102 to waveguide layer 115a via tapered end 102c1 and 115a1.

[0096] According to some embodiments, waveguide layer 115 is made of a nitride-containing material (eg, silicon nitride) or a lithium-containing material (eg, lithium nickelate (LiNiO 2 )). In some embodiments, waveguide layers 102 and 115 are made of different materials.

[0097] refer to Figure 1A and Figure 1B According to some embodiments, method 10 continues with operation 12 of bonding electronic integrated circuit chip 120 to photonic integrated circuit chip 110 . According to some embodiments, electronic integrated circuit chip 120 includes substrate 121 , device layer 122 , dielectric layer 123 , bonding pads 124 , and conductive vias 125 .

[0098] According to some embodiments, substrate 121 has a front surface 121a. Substrate 121 includes, for example, a semiconductor substrate. In some embodiments, substrate 121 is made of an elemental semiconductor material including silicon or germanium in a single crystal structure, a polycrystalline structure, or an amorphous structure. In some other embodiments, substrate 121 is made of a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, an alloy semiconductor, such as silicon germanium (SiGe) or gallium arsenic phosphide (GaAsP), or a combination thereof. Substrate 121 may also include a multilayer semiconductor, a semiconductor on insulator (SOI) (e.g., silicon on insulator or germanium on insulator), or a combination thereof.

[0099] In some embodiments, an active region and isolation features (not shown) are formed in substrate 121. The isolation features are used to surround the active region and electrically isolate various device elements formed in and / or above substrate 121 in the active region. In some embodiments, the isolation features include shallow trench isolation (STI) features, local oxidation of silicon (LOCOS) features, other suitable isolation features, or combinations thereof.

[0100] According to some embodiments, device layer 122 is formed over front surface 121a. According to some embodiments, device layer 122 includes dielectric layer 122a, various device elements, and interconnect structures (not shown) in dielectric layer 122a.

[0101] According to some embodiments, dielectric layer 122 a is made of a dielectric material, such as an oxide-containing material (e.g., silicon oxide or tetraethyl orthosilicate (TEOS) oxide), a nitrogen-containing oxide material (e.g., silicon oxynitride), a glass material (e.g., borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or fluorinated silicate glass (FSG)), or a combination thereof. Alternatively, according to some embodiments, dielectric layer 122 a includes a low-k material or a porous dielectric material having a k value lower than that of silicon oxide, or lower than approximately 3.0 or approximately 2.5.

[0102] The dielectric layer 122a is formed using a chemical vapor deposition (CVD) process, such as a low pressure chemical vapor deposition process, a plasma enhanced chemical vapor deposition process, a high density plasma chemical vapor deposition process, an atomic layer deposition process, a spin coating process, a physical vapor deposition process, or other suitable process.

[0103] According to some embodiments, device elements are formed in and / or on substrate 121. Examples of various device elements include active elements, passive elements, other suitable elements, or combinations thereof. Active elements may include elements formed on front surface 121a of substrate 121. Passive elements may include resistors, capacitors, or other suitable passive elements.

[0104] For example, the transistor 122b may be a metal oxide semiconductor field effect transistor (MOSFET), a complementary metal oxide semiconductor (CMOS) transistor, a bipolar junction transistor (BJT), a high voltage transistor, a high frequency transistor, a p-channel and / or n-channel field effect transistor (PFET / NFET), etc.

[0105] Various processes, such as front-end-of-the-line (FEOL) semiconductor processes, are performed to form various device elements. The front-end-of-the-line (FEOL) semiconductor processes may include deposition, etching, implantation, photolithography, annealing, planarization, one or more other suitable processes, or a combination thereof.

[0106] According to some embodiments, the interconnect structure electrically connects between various device elements, bond pads 124, and conductive vias 125. According to some embodiments, the interconnect structure includes a wiring layer and conductive vias.

[0107] According to some embodiments, conductive vias connect between wiring layers and between device elements and wiring layers. According to some embodiments, the interconnect structure is made of a conductive material such as metal (eg, copper, aluminum, gold, silver, or tungsten) or alloys thereof.

[0108] According to some embodiments, dielectric layer 123 is formed over device layer 122. According to some embodiments, dielectric layer 123 is directly bonded to dielectric layer 112 of photonic integrated circuit chip 110.

[0109] According to some embodiments, the dielectric layer 123 is made of a dielectric material, such as an oxide-containing material (e.g., silicon oxide or tetraethylorthosilicate (TEOS) oxide), a nitrogen-containing oxide material (e.g., silicon oxynitride), a glass material (e.g., borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or fluorinated silicate glass (FSG)), or a combination thereof.

[0110] Alternatively, according to some embodiments, dielectric layer 123 includes a low-k material or a porous dielectric material having a k value lower than that of silicon oxide, or lower than about 3.0 or about 2.5.

[0111] The dielectric layer 123 is formed using a chemical vapor deposition (CVD) process, such as a low pressure chemical vapor deposition process, a plasma enhanced chemical vapor deposition process, a high density plasma chemical vapor deposition process, an atomic layer deposition process, a spin coating process, a physical vapor deposition process, or other suitable processes.

[0112] According to some embodiments, bonding pads 124 and conductive vias 125 are formed in dielectric layer 123. According to some embodiments, conductive vias 125 connect between bonding pads 124 and the interconnect structure of device layer 122. According to some embodiments, bonding pads 124 are directly bonded to bonding pads 113 of photonic integrated circuit chip 110.

[0113] According to some embodiments, the bonding pads 124 and the conductive vias 125 are made of a conductive material, such as a metal (eg, copper, aluminum, gold, silver, or tungsten) or alloys thereof.

[0114] According to some embodiments, Figure 1A and Figure 1B As shown, method 10 proceeds to operation 13 of bonding an optical transmission chip 130 to the photonic integrated circuit chip 110. According to some embodiments, the optical transmission chip 130 includes a substrate 131, an anti-reflection layer 132, a dielectric layer 133, a waveguide structure 134, a reflective structure 135, a dielectric layer 136, a dielectric layer 137, and a bonding pad 138. According to some embodiments, the optical transmission chip 130 does not include active components (e.g., transistors) and / or passive components (e.g., resistors or capacitors).

[0115] According to some embodiments, substrate 131 has a lower surface 131a facing photonic integrated circuit chip 110. Substrate 131 comprises, for example, a semiconductor substrate. In some embodiments, substrate 131 is made of an elemental semiconductor material including silicon or germanium in a single crystal structure, a polycrystalline structure, or an amorphous structure.

[0116] In some other embodiments, the substrate 131 is made of a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, a semiconductor such as silicon germanium (SiGe) or gallium arsenic phosphide (GaAsP) alloy, or a combination thereof. The substrate 131 may also include a multilayer semiconductor, a semiconductor-on-insulator (SOI) (such as silicon-on-insulator or germanium-on-insulator), or a combination thereof.

[0117] According to some embodiments, an anti-reflection layer 132 is formed over the lower surface 131a. According to some embodiments, the anti-reflection layer 132 is made of a nitride-containing material (e.g., silicon nitride), an oxide-containing material (e.g., silicon dioxide (SiO2) or tantalum pentoxide (Ta2O5)), or other suitable materials with a high light transmittance greater than 99%.

[0118] According to some embodiments, dielectric layer 133 is formed over anti-reflective layer 132. According to some embodiments, dielectric layer 133 is made of a dielectric material, such as an oxide-containing material (e.g., silicon oxide or tetraethyl orthosilicate (TEOS) oxide), a nitrogen-containing oxide material (e.g., silicon oxynitride), a glass material (e.g., borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or fluorinated silicate glass (FSG)), or a combination thereof. Alternatively, according to some embodiments, dielectric layer 133 includes a low-k material or a porous dielectric material having a k value lower than that of silicon oxide, or lower than approximately 3.0 or approximately 2.5.

[0119] The dielectric layer 133 is formed using a chemical vapor deposition (CVD) process, such as a low pressure chemical vapor deposition process, a plasma enhanced chemical vapor deposition process, a high density plasma chemical vapor deposition process, an atomic layer deposition process, a spin coating process, a physical vapor deposition process, or other suitable process.

[0120] According to some embodiments, the waveguide structure 134 is formed in the dielectric layer 133. According to some embodiments, the waveguide structure 134 includes a waveguide layer. According to some embodiments, the waveguide structure WG overlaps with the waveguide structure 134 in a direction V1 perpendicular to the lower surface 131a of the substrate 131. According to some embodiments, the waveguide structure 134 is made of a nitride-containing material (e.g., silicon nitride) or a lithium-containing material (e.g., lithium nickelate (LiNiO2)).

[0121] According to some embodiments, the reflective structure 135 is formed in the dielectric layer 133. According to some embodiments, the reflective structure 135 has a trapezoidal shape. According to some embodiments, the reflective structure 135 has opposing sidewalls 135a and 135b.

[0122] According to some embodiments, the sidewalls 135a and 135b are inclined sidewalls. In some embodiments, a distance D135 between the sidewalls 135a and 135b decreases toward the substrate 131. According to some embodiments, the anti-reflection layer 132 is located between the reflective structure 135 and the substrate 131.

[0123] According to some embodiments, the waveguide structure 134 and the reflective structure 135 are located between the substrate 131 and the photonic integrated circuit chip 110. In some embodiments, an angle θ1 between the upper surface 134a of the waveguide structure 134 and the sidewall 135a of the reflective structure 135 is greater than 90 degrees and less than 180 degrees. According to some embodiments, the angle θ1 ranges from about 130 degrees to about 140 degrees. According to some embodiments, the sidewall 135a is adjacent to the waveguide structure 134.

[0124] According to some embodiments, the reflective structure 135 is made of metal (e.g., copper, aluminum, gold, silver or tungsten), alloys thereof, semiconductor materials (e.g., amorphous silicon), oxide-containing materials, dielectric materials or other suitable materials with high reflectivity having a reflectivity greater than 99%.

[0125] According to some embodiments, dielectric layer 136 is formed in reflective structure 135. According to some embodiments, dielectric layer 136 has a trapezoidal shape. According to some embodiments, a width W136 of dielectric layer 136 decreases toward substrate 131.

[0126] According to some embodiments, dielectric layer 136 is made of a dielectric material, such as an oxide-containing material (e.g., silicon oxide or tetraethylorthosilicate (TEOS) oxide), a nitrogen-containing oxide material (e.g., silicon oxynitride), a glass material (e.g., borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or fluorinated silicate glass (FSG)), or a combination thereof.

[0127] Alternatively, according to some embodiments, dielectric layer 136 includes a low-k material or a porous dielectric material having a k value lower than that of silicon oxide, or lower than about 3.0 or about 2.5. In some embodiments, dielectric layer 133 and dielectric layer 136 are made of the same material.

[0128] According to some embodiments, the method of forming the reflective structure 135 and the dielectric layer 136 includes: partially removing the dielectric layer 133 to form a groove 133a in the dielectric layer 133; conformally depositing a reflective material layer (not shown) above the dielectric layer 133 and in the groove 133a; depositing a dielectric material layer (not shown) above the reflective material layer and in the groove 133a; and removing the reflective material layer and the dielectric material layer outside the groove 133a.

[0129] According to some embodiments, the reflective material layer remaining in the groove 133a forms a reflective structure 135. According to some embodiments, the dielectric material layer remaining in the groove 133a forms a dielectric layer 136.

[0130] The deposition process may include a chemical vapor deposition (CVD) process, such as a low-pressure chemical vapor deposition process, a plasma-enhanced chemical vapor deposition process, a high-density plasma chemical vapor deposition process, an atomic layer deposition process, a physical vapor deposition process, or other suitable processes. According to some embodiments, the process for removing the reflective material layer and the dielectric material layer outside the groove 133a includes a planarization process, such as a chemical mechanical polishing process.

[0131] According to some embodiments, dielectric layer 137 is formed over dielectric layers 133 and 136 and reflective structure 135. According to some embodiments, dielectric layer 137 is directly bonded to dielectric layer 112 of photonic integrated circuit chip 110.

[0132] According to some embodiments, dielectric layer 137 is made of a dielectric material, such as an oxide-containing material (e.g., silicon oxide or tetraethylorthosilicate (TEOS) oxide), a nitrogen-containing oxide material (e.g., silicon oxynitride), a glass material (e.g., borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or fluorinated silicate glass (FSG)), or a combination thereof.

[0133] Alternatively, according to some embodiments, dielectric layer 137 includes a low-k material or a porous dielectric material having a k value lower than that of silicon oxide, or lower than about 3.0 or about 2.5.

[0134] The dielectric layer 137 is formed using a chemical vapor deposition (CVD) process, such as a low pressure chemical vapor deposition process, a plasma enhanced chemical vapor deposition process, a high density plasma chemical vapor deposition process, an atomic layer deposition process, a spin coating process, a physical vapor deposition process, or other suitable process.

[0135] According to some embodiments, bonding pads 138 are formed in dielectric layer 137. According to some embodiments, bonding pads 138 are directly bonded to bonding pads 113 of photonic integrated circuit chip 110. According to some embodiments, bonding pads 138 are made of a conductive material, such as a metal (e.g., copper, aluminum, gold, silver, or tungsten) or alloys thereof.

[0136] like Figure 1A and Figure 1B As shown, according to some embodiments, the method 10 proceeds to operation 14 of forming a molding layer 140 between the electronic integrated circuit chip 120 and the optical transmission chip 130. The molding layer 140 is made of a polymer material or other suitable insulating material.

[0137] The polymer material includes a thermosetting polymer, a thermoplastic polymer, or a mixture thereof. The polymer material includes, for example, plastic materials, epoxy resins, polyimide, polyethylene terephthalate (PET), polyvinyl chloride (PVC), polymethyl methacrylate (PMMA), polymers doped with fillers, such as fibers, clay, silica, glass, ceramics, inorganic particles, or combinations thereof.

[0138] like Figure 1A and Figure 1B As shown, the method 10 continues with operation 15 of forming an anti-reflection layer 150 over the electronic integrated circuit chip 120 , the optical transmission chip 130 , and the molding layer 140 , according to some embodiments.

[0139] According to some embodiments, the anti-reflection layer 150 is made of a nitride-containing material (eg, silicon nitride), an oxide-containing material (eg, silicon dioxide (SiO 2 ) or tantalum pentoxide (Ta 2 O 5 )), or other suitable materials with high light transmittance higher than 99%.

[0140] like Figure 1A and Figure 1B As shown, according to some embodiments, method 10 continues with operation 16 of forming a light transmitting structure 160 over the anti-reflection layer 150. According to some embodiments, the light transmitting structure 160 includes a dielectric layer 161, a waveguide structure 162, a reflective structure 163, and a dielectric layer 164.

[0141] According to some embodiments, dielectric layer 161 is formed over anti-reflective layer 150. According to some embodiments, dielectric layer 161 is made of a dielectric material, such as an oxide-containing material (e.g., silicon oxide or tetraethyl orthosilicate (TEOS) oxide), a nitrogen-containing oxide material (e.g., silicon oxynitride), a glass material (e.g., borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or fluorinated silicate glass (FSG)), or a combination thereof. Alternatively, according to some embodiments, dielectric layer 161 includes a low-k material or a porous dielectric material having a k value lower than that of silicon oxide, or lower than approximately 3.0 or approximately 2.5.

[0142] The dielectric layer 161 is formed using a chemical vapor deposition (CVD) process, such as a low pressure chemical vapor deposition process, a plasma enhanced chemical vapor deposition process, a high density plasma chemical vapor deposition process, an atomic layer deposition process, a spin coating process, a physical vapor deposition process, or other suitable process.

[0143] According to some embodiments, a waveguide structure 162 is formed in the dielectric layer 161. According to some embodiments, the waveguide structure 162 includes a waveguide layer. According to some embodiments, the waveguide structure 162 is made of a nitride-containing material (e.g., silicon nitride) or a lithium-containing material (e.g., lithium nickelate (LiNiO2)).

[0144] According to some embodiments, the reflective structure 163 is formed in the dielectric layer 161. According to some embodiments, the reflective structure 163 has a trapezoidal shape. According to some embodiments, the reflective structure 163 has opposing sidewalls 163a and 163b. According to some embodiments, a distance D163 between the sidewalls 163a and 163b decreases toward the substrate 131.

[0145] In some embodiments, an angle θ2 between the upper surface 162a of the waveguide structure 162 and the sidewall 163a of the reflective structure 163 is greater than 0 degrees and less than 90 degrees. According to some embodiments, the angle θ2 ranges from about 40 degrees to about 50 degrees. According to some embodiments, the sidewall 163a is adjacent to the waveguide structure 162.

[0146] According to some embodiments, sidewall 135a of reflective structure 135 overlaps sidewall 163a of reflective structure 163 in direction V1 perpendicular to lower surface 131a of substrate 131. According to some embodiments, anti-reflective layer 150 is located between reflective structure 163 and substrate 131.

[0147] According to some embodiments, the reflective structure 163 is made of metal (e.g., copper, aluminum, gold, silver or tungsten), alloys thereof, semiconductor materials (e.g., amorphous silicon), oxide-containing materials, dielectric materials or other suitable materials with high reflectivity having a reflectivity higher than 99%.

[0148] According to some embodiments, the dielectric layer 164 is formed in the reflective structure 163. According to some embodiments, the dielectric layer 164 has a trapezoidal shape. According to some embodiments, the width W164 of the dielectric layer 164 decreases toward the substrate 131 of the optical transmission chip 130.

[0149] According to some embodiments, dielectric layer 164 is made of a dielectric material, such as an oxide-containing material (e.g., silicon oxide or tetraethylorthosilicate (TEOS) oxide), a nitrogen-containing oxide material (e.g., silicon oxynitride), a glass material (e.g., borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or fluorinated silicate glass (FSG)), or a combination thereof).

[0150] Alternatively, according to some embodiments, dielectric layer 164 includes a low-k material or a porous dielectric material having a k value lower than that of silicon oxide, or lower than about 3.0 or about 2.5. In some embodiments, dielectric layers 133 and 164 are made of the same material.

[0151] like Figure 1A and Figure 1B As shown, according to some embodiments, method 10 proceeds to operation 17 of forming a bonding layer 170 over the light transmitting structure 160. According to some embodiments, the bonding layer 170 is made of a dielectric material, such as an oxide-containing material (e.g., silicon oxide or tetraethylorthosilicate (TEOS) oxide), a nitrogen-containing oxide material (e.g., silicon oxynitride), a glass material (e.g., borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or fluorinated silicate glass (FSG)), or a combination thereof.

[0152] Alternatively, according to some embodiments, bonding layer 170 includes a low-k material or a porous dielectric material having a k value lower than the k value of silicon oxide, or lower than about 3.0 or about 2.5.

[0153] The bonding layer 170 is formed using a chemical vapor deposition process, such as a low pressure chemical vapor deposition process, a plasma enhanced chemical vapor deposition process, a high density plasma chemical vapor deposition process, an atomic layer deposition process, a spin coating process, a physical vapor deposition process, or other suitable processes.

[0154] like Figure 1A and 1B As shown, according to some embodiments, method 10 proceeds to operation 18 by bonding a support chip 180 to bonding layer 170. According to some embodiments, support chip 180 includes a substrate 181 and a bonding layer 182. According to some embodiments, substrate 181 has a surface 181a. According to some embodiments, bonding layer 182 is formed above surface 181a. According to some embodiments, bonding layer 182 is directly bonded to bonding layer 170.

[0155] The substrate 181 includes, for example, a semiconductor substrate. In some embodiments, the substrate 181 is made of an elemental semiconductor material including silicon or germanium in a single crystal structure, a polycrystalline structure, or an amorphous structure.

[0156] In some other embodiments, the substrate 181 is made of a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, an alloy semiconductor such as silicon germanium (SiGe) or gallium arsenic phosphide (GaAsP), or a combination thereof. The substrate 181 may also include a multilayer semiconductor, a semiconductor-on-insulator (SOI) (such as silicon-on-insulator or germanium-on-insulator), or a combination thereof.

[0157] According to some embodiments, the bonding layer 182 is made of a dielectric material, such as an oxide-containing material (e.g., silicon oxide or tetraethylorthosilicate (TEOS) oxide), a nitrogen-containing oxide material (e.g., silicon oxynitride), a glass material (e.g., borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG) or fluorinated silicate glass (FSG)), or a combination thereof.

[0158] Alternatively, according to some embodiments, bonding layer 182 includes a low-k material or a porous dielectric material having a k value lower than the k value of silicon oxide, or lower than about 3.0 or about 2.5.

[0159] The bonding layer 182 is formed using a chemical vapor deposition (CVD) process, such as a low pressure chemical vapor deposition process, a plasma enhanced chemical vapor deposition process, a high density plasma chemical vapor deposition process, an atomic layer deposition process, a spin coating process, a physical vapor deposition process, or other suitable process.

[0160] like Figure 1A As shown, according to some embodiments, dielectric layer 190 is formed over surface 101a of dielectric layer 101. According to some embodiments, dielectric layer 190 is made of a dielectric material, such as an oxide-containing material (e.g., silicon oxide or tetraethylorthosilicate (TEOS) oxide), a nitrogen-containing oxide material (e.g., silicon oxynitride), a glass material (e.g., borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or fluorinated silicate glass (FSG)), or a combination thereof.

[0161] Alternatively, according to some embodiments, dielectric layer 190 includes a low-k material or a porous dielectric material having a k value lower than that of silicon oxide, or lower than about 3.0 or about 2.5.

[0162] The dielectric layer 190 is formed using a chemical vapor deposition (CVD) process, such as a low pressure chemical vapor deposition process, a plasma enhanced chemical vapor deposition process, a high density plasma chemical vapor deposition process, an atomic layer deposition process, a spin coating process, a physical vapor deposition process, or other suitable process.

[0163] like Figure 1A As shown, according to some embodiments, conductive plug 210 is formed in dielectric layers 101, 105, 106, and 190. According to some embodiments, conductive plug 210 is made of a conductive material, such as metal (eg, copper, aluminum, gold, silver, or tungsten) or alloys thereof.

[0164] like Figure 1AAs shown, according to some embodiments, wiring layer 220 is formed in dielectric layer 190. According to some embodiments, wiring layer 220 is made of a conductive material such as metal (eg, copper, aluminum, gold, silver, or tungsten) or alloys thereof.

[0165] like Figure 1A As shown, according to some embodiments, conductive via 230 is formed in dielectric layer 190 and conductive pad 240 is formed over surface 192 of dielectric layer 190. According to some embodiments, conductive via 230 connects between wiring layer 220 and conductive pad 240.

[0166] According to some embodiments, the conductive via 230 and the conductive pad 240 are made of a conductive material such as metal (eg, copper, aluminum, gold, silver, or tungsten) or alloys thereof.

[0167] like Figure 1A As shown, according to some embodiments, conductive bumps 250 are formed above the conductive pads 240. According to some embodiments, the conductive bumps 250 are made of a conductive material, such as a tin-based alloy. In this step, according to some embodiments, the chip package structure 100 is substantially formed. According to some embodiments, the chip package structure 100 is also referred to as an optical engine package structure.

[0168] like Figure 1A As shown, according to some embodiments, the optical signal L passes through the waveguide structure 134 , is reflected by the sidewall 135 a of the reflective structure 135 , passes through the substrate 131 , is reflected by the sidewall 163 a of the reflective structure 163 , and passes through the waveguide structure 162 .

[0169] In some common embodiments, an optical signal (not shown) from the photonic integrated circuit chip 110 passes through the molding layer 140 and the supporting chip 180. According to some embodiments, the optical path length of the optical signal L of the present invention is shorter than a common optical path length, which can reduce the path loss of the optical signal L.

[0170] According to some embodiments, since the optical transmission chip 130 and the optical transmission structure 160 reduce the optical path length of the optical signal L, the performance of the chip package structure 100 is improved.

[0171] According to some embodiments, since the coefficient of thermal expansion (CTE) of the optical transmission chip 130 and the optical transmission structure 160 is similar to the coefficient of thermal expansion of the photonic integrated circuit chip 110, the electronic integrated circuit chip 120 and the support chip 180, there is no additional coefficient of thermal expansion (CTE) matching problem.

[0172] Figure 2 FIG is a cross-sectional view of a chip package structure 200 according to some embodiments. Figure 2 As shown, according to some embodiments, the chip package structure 200 and Figure 1A The chip package structure 100 is similar to the chip package structure 100, except that the chip package structure 200 has a light transmission structure 260 to replace the Figure 1A The optical transmission chip 130 of the chip package structure 100 is shown in FIG. In addition, according to some embodiments, the chip package structure 200 does not include Figure 1A The anti-reflection layer 150 and the light transmission structure 160 of the chip package structure 100 are shown.

[0173] According to some embodiments, the light transmitting structure 260 includes a substrate 261 , an anti-reflection layer 262 , a light transmitting structure 263 , a bonding layer 264 , a dummy chip 265 , an anti-reflection layer 266 , a light transmitting structure 267 , a dielectric layer 268 and a bonding pad 269 .

[0174] The substrate 261 includes, for example, a semiconductor substrate. In some embodiments, the substrate 261 is made of an elemental semiconductor material including silicon or germanium in a single crystal structure, a polycrystalline structure, or an amorphous structure.

[0175] In some other embodiments, the substrate 261 is made of a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, an alloy semiconductor, such as silicon germanium (SiGe) or gallium arsenic phosphide (GaAsP), or a combination thereof. The substrate 261 may also include a multilayer semiconductor, a semiconductor-on-insulator (SOI) (such as silicon-on-insulator or germanium-on-insulator), or a combination thereof.

[0176] According to some embodiments, the anti-reflection layer 262 is formed over the surface 261a of the substrate 261. According to some embodiments, the anti-reflection layer 262 is made of a nitride-containing material (e.g., silicon nitride), an oxide-containing material (e.g., silicon dioxide (SiO2) or tantalum pentoxide (Ta2O5)), or other suitable materials with high light transmittance greater than 99%.

[0177] According to some embodiments, a light transmitting structure 263 is formed over the anti-reflection layer 262. According to some embodiments, the light transmitting structure 263 includes a dielectric layer 263a, a waveguide structure 263b, a reflective structure 263c, and a dielectric layer 263d.

[0178] According to some embodiments, dielectric layer 263a is formed over anti-reflective layer 262. According to some embodiments, dielectric layer 263a is made of a dielectric material, such as an oxide-containing material (e.g., silicon oxide or tetraethyl orthosilicate (TEOS) oxide), a nitrogen-containing oxide material (e.g., silicon oxynitride), a glass material (e.g., borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or fluorinated silicate glass (FSG)), or a combination thereof. Alternatively, according to some embodiments, dielectric layer 263a includes a low-k material or a porous dielectric material having a k value lower than that of silicon oxide, or lower than approximately 3.0 or approximately 2.5.

[0179] The dielectric layer 263a is formed using a chemical vapor deposition (CVD) process, such as a low pressure chemical vapor deposition process, a plasma enhanced chemical vapor deposition process, a high density plasma chemical vapor deposition process, an atomic layer deposition process, a spin coating process, a physical vapor deposition process, or other suitable process.

[0180] According to some embodiments, the waveguide structure 263b is formed in the dielectric layer 263a. According to some embodiments, the waveguide structure 263b includes a waveguide layer. According to some embodiments, the waveguide structure 263b is made of a nitride-containing material (e.g., silicon nitride) or a lithium-containing material (e.g., lithium nickelate (LiNiO2)).

[0181] According to some embodiments, the reflective structure 263c is formed in the dielectric layer 263a. According to some embodiments, the reflective structure 263c has a trapezoidal shape. The reflective structure 263c is made of a metal (e.g., copper, aluminum, gold, silver, or tungsten), an alloy thereof, a semiconductor material (e.g., amorphous silicon), an oxide-containing material, a dielectric material, or other suitable material with a high reflectivity greater than 99%.

[0182] According to some embodiments, a dielectric layer 263d is formed in the reflective structure 263c. According to some embodiments, the dielectric layer 263d has a trapezoidal shape. According to some embodiments, the dielectric layer 263d is made of a dielectric material, such as an oxide-containing material (e.g., silicon oxide or tetraethyl orthosilicate (TEOS) oxide), a nitrogen-containing oxide material (e.g., silicon oxynitride), a glass material (e.g., borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or fluorinated silicate glass (FSG)), or a combination thereof.

[0183] Alternatively, according to some embodiments, dielectric layer 263d includes a low-k material or a porous dielectric material having a k value lower than that of silicon oxide, or lower than about 3.0 or about 2.5. In some embodiments, dielectric layers 263a and 263d are made of the same material.

[0184] According to some embodiments, a bonding layer 264 is formed over the light-transmitting structure 263. According to some embodiments, the bonding layer 264 is made of a dielectric material, such as an oxide-containing material (e.g., silicon oxide or tetraethylorthosilicate (TEOS) oxide), a nitrogen-containing oxide material (e.g., silicon oxynitride), a glass material (e.g., borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or fluorinated silicate glass (FSG)), or a combination thereof.

[0185] Alternatively, according to some embodiments, bonding layer 264 includes a low-k material or a porous dielectric material having a k value lower than the k value of silicon oxide, or lower than about 3.0 or about 2.5.

[0186] The bonding layer 264 is formed using a chemical vapor deposition (CVD) process, such as a low pressure chemical vapor deposition process, a plasma enhanced chemical vapor deposition process, a high density plasma chemical vapor deposition process, an atomic layer deposition process, a spin coating process, a physical vapor deposition process, or other suitable process.

[0187] According to some embodiments, dummy chip 265 is bonded to bonding layer 264. In some embodiments, a top surface 265c of dummy chip 265 is substantially flush with top surface 120a of electronic integrated circuit chip 120. According to some embodiments, dummy chip 265 includes substrate 265a and bonding layer 265b. According to some embodiments, substrate 265a has a surface 265a1. According to some embodiments, bonding layer 265b is formed above surface 265a1. According to some embodiments, bonding layer 265b is directly bonded to bonding layer 264.

[0188] The substrate 265a includes, for example, a semiconductor substrate. In some embodiments, the substrate 265a is made of an elemental semiconductor material including silicon or germanium in a single crystal structure, a polycrystalline structure, or an amorphous structure.

[0189] In some other embodiments, the substrate 265a is made of a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, an alloy semiconductor, such as silicon germanium (SiGe) or gallium arsenic phosphide (GaAsP), or a combination thereof. The substrate 265a may also include a multilayer semiconductor, a semiconductor-on-insulator (SOI) (such as silicon-on-insulator or germanium-on-insulator), or a combination thereof.

[0190] According to some embodiments, the bonding layer 265b is made of a dielectric material, such as an oxide-containing material (e.g., silicon oxide or tetraethylorthosilicate (TEOS) oxide), a nitrogen-containing oxide material (e.g., silicon oxynitride), a glass material (e.g., borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG) or fluorinated silicate glass (FSG)) or a combination thereof.

[0191] Alternatively, according to some embodiments, bonding layer 265b includes a low-k material or a porous dielectric material having a k value lower than that of silicon oxide, or lower than about 3.0 or about 2.5.

[0192] The bonding layer 265 b is formed using a chemical vapor deposition (CVD) process, such as a low pressure chemical vapor deposition process, a plasma enhanced chemical vapor deposition process, a high density plasma chemical vapor deposition process, an atomic layer deposition process, a spin coating process, a physical vapor deposition process, or other suitable processes.

[0193] According to some embodiments, the anti-reflection layer 266 is formed over the surface 261b of the substrate 261. According to some embodiments, the anti-reflection layer 266 is made of a nitride-containing material (e.g., silicon nitride), an oxide-containing material (e.g., silicon dioxide (SiO2) or tantalum pentoxide (Ta2O5)), or other suitable materials with high light transmittance greater than 99%.

[0194] According to some embodiments, a light transmitting structure 267 is formed over the anti-reflection layer 266. According to some embodiments, the light transmitting structure 267 includes a dielectric layer 267a, a waveguide structure 267b, a reflective structure 267c, and a dielectric layer 267d.

[0195] According to some embodiments, a dielectric layer 267a is formed over the anti-reflective layer 266. According to some embodiments, the dielectric layer 267a is made of a dielectric material, such as an oxide-containing material (e.g., silicon oxide or tetraethyl orthosilicate (TEOS) oxide), a nitrogen-containing oxide material (e.g., silicon oxynitride), a glass material (e.g., borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or fluorinated silicate glass (FSG)), or a combination thereof. Alternatively, according to some embodiments, the dielectric layer 267a includes a low-k material or a porous dielectric material having a k value lower than that of silicon oxide, or lower than approximately 3.0 or approximately 2.5.

[0196] The dielectric layer 267a is formed using a chemical vapor deposition (CVD) process, such as a low pressure chemical vapor deposition process, a plasma enhanced chemical vapor deposition process, a high density plasma chemical vapor deposition process, an atomic layer deposition process, a spin coating process, a physical vapor deposition process, or other suitable process.

[0197] According to some embodiments, a waveguide structure 267b is formed in the dielectric layer 267a. According to some embodiments, the waveguide structure 267b includes a waveguide layer. According to some embodiments, the waveguide structure 267b is made of a nitride-containing material (e.g., silicon nitride) or a lithium-containing material (e.g., lithium nickelate (LiNiO2)).

[0198] According to some embodiments, the reflective structure 267c is formed in the dielectric layer 267a. According to some embodiments, the reflective structure 267c has a trapezoidal shape. According to some embodiments, the reflective structure 267c is made of a metal (e.g., copper, aluminum, gold, silver, or tungsten), an alloy thereof, a semiconductor material (e.g., amorphous silicon), an oxide-containing material, a dielectric material, or another suitable material with a high reflectivity greater than 99%.

[0199] According to some embodiments, a dielectric layer 267d is formed in the reflective structure 267c. According to some embodiments, the dielectric layer 267d has a trapezoidal shape. According to some embodiments, the dielectric layer 267d is made of a dielectric material, such as an oxide-containing material (e.g., silicon oxide or tetraethylorthosilicate (TEOS) oxide), a nitrogen-containing oxide material (e.g., silicon oxynitride), a glass material (e.g., borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or fluorinated silicate glass (FSG)), or a combination thereof.

[0200] Alternatively, according to some embodiments, dielectric layer 267d includes a low-k material or a porous dielectric material having a k value lower than that of silicon oxide, or lower than about 3.0 or about 2.5. In some embodiments, dielectric layers 267a and 267d are made of the same material.

[0201] According to some embodiments, dielectric layer 268 is formed over light transmitting structure 267. According to some embodiments, dielectric layer 268 is directly bonded to dielectric layer 112 of photonic integrated circuit chip 110.

[0202] According to some embodiments, dielectric layer 268 is made of a dielectric material, such as an oxide-containing material (e.g., silicon oxide or tetraethylorthosilicate (TEOS) oxide), a nitrogen-containing oxide material (e.g., silicon oxynitride), a glass material (e.g., borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or fluorinated silicate glass (FSG)), or a combination thereof.

[0203] Alternatively, according to some embodiments, dielectric layer 268 includes a low-k material or a porous dielectric material having a k value lower than the k value of silicon oxide, or lower than about 3.0 or about 2.5.

[0204] The dielectric layer 268 is formed using a chemical vapor deposition (CVD) process, such as a low pressure chemical vapor deposition process, a plasma enhanced chemical vapor deposition process, a high density plasma chemical vapor deposition process, an atomic layer deposition process, a spin coating process, a physical vapor deposition process, or other suitable process.

[0205] According to some embodiments, bonding pads 269 are formed in dielectric layer 268. According to some embodiments, bonding pads 269 are directly bonded to bonding pads 113 of photonic integrated circuit chip 110. According to some embodiments, bonding pads 269 are made of a conductive material, such as a metal (e.g., copper, aluminum, gold, silver, or tungsten) or alloys thereof.

[0206] like Figure 2 As shown, according to some embodiments, the optical signal L passes through the waveguide structure 267b, is reflected by the reflective structure 267c, passes through the substrate 261, is reflected by the reflective structure 263c, and passes through the waveguide structure 263b. According to some embodiments, since the substrate 261 is larger than Figure 1A The substrate 131 of the chip package structure 100 is thin, so Figure 2 The optical path length of the optical signal L is less than Figure 1A The optical path length of the optical signal L is shortened, thereby reducing the path loss of the optical signal L. Optical signal L.

[0207] Figure 3 FIG is a cross-sectional view of a chip package structure 300 according to some embodiments. Figure 3 As shown, according to some embodiments, the chip package structure 300 and Figure 1A The chip package structure 300 is similar to the chip package structure 100, except that the optical transmission chip 130 of the chip package structure 300 further includes an anti-reflection layer 310 and a dielectric layer 320 in the substrate 131, and the supporting chip 180 of the chip package structure 300 further includes an anti-reflection layer 183, an anti-reflection layer 184, a dielectric layer 185 and an optical transmission structure 186. In addition, according to some embodiments, the chip package structure 300 does not include Figure 1A The light transmission structure 160 of the chip package structure 100 is shown in FIG.

[0208] According to some embodiments, the substrate 131 has a recess 131 r. According to some embodiments, the recess 131 r has a bottom surface. According to some embodiments, the bottom surface includes a convex surface 131 b. According to some embodiments, the convex surface 131 b faces the photonic integrated circuit chip 110.

[0209] According to some embodiments, the waveguide structure 134 is partially located between the convex curved surface 131 b and the photonic integrated circuit chip 110. According to some embodiments, the reflective structure 135 is located between the convex curved surface 131 b and the photonic integrated circuit chip 110.

[0210] The anti-reflection layer 310 conformally covers the inner wall of the concave portion 131r and the convex curved surface 131b. According to some embodiments, a dielectric layer 320 is formed above the anti-reflection layer 310. According to some embodiments, the anti-reflection layer 310 is made of a nitride-containing material (e.g., silicon nitride), an oxide-containing material (e.g., silicon dioxide (SiO2) or tantalum pentoxide (Ta2O5)), or other suitable materials with a high transmittance greater than 99%.

[0211] According to some embodiments, dielectric layer 320 is made of a dielectric material, such as an oxide-containing material (e.g., silicon oxide or tetraethylorthosilicate (TEOS) oxide), a nitrogen-containing oxide material (e.g., silicon oxynitride), a glass material (e.g., borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or fluorinated silicate glass (FSG)), or a combination thereof.

[0212] Alternatively, according to some embodiments, dielectric layer 320 includes a low-k material or a porous dielectric material having a k value lower than the k value of silicon oxide, or lower than about 3.0 or about 2.5. In some embodiments, dielectric layers 133 and 320 are made of the same material. According to some embodiments, anti-reflective layer 310 and dielectric layer 320 are formed using a deposition process and a planarization process, such as a chemical mechanical polishing process.

[0213] According to some embodiments, the anti-reflection layer 183 is located between the substrate 181 and the bonding layer 182. According to some embodiments, the anti-reflection layer 183 is made of a nitride-containing material (e.g., silicon nitride), an oxide-containing material (e.g., silicon dioxide (SiO2) or tantalum pentoxide (Ta2O5)), or other suitable materials with high light transmittance greater than 99%.

[0214] According to some embodiments, the substrate 181 has a recess 181 r. According to some embodiments, the recess 181 r has a bottom surface. According to some embodiments, the bottom surface includes a convex surface 181 b. According to some embodiments, the convex surface 181 b faces away from the light transmission chip 130.

[0215] According to some embodiments, the anti-reflection layer 184 conformally covers the inner wall of the concave portion 181r and the convex curved surface 181b. According to some embodiments, a dielectric layer 185 is formed above the anti-reflection layer 184. According to some embodiments, the anti-reflection layer 184 is made of a nitride-containing material (e.g., silicon nitride), an oxide-containing material (e.g., silicon dioxide (SiO2) or tantalum pentoxide (Ta2O5)), or other suitable materials with a high light transmittance greater than 99%.

[0216] According to some embodiments, dielectric layer 185 is made of a dielectric material, such as an oxide-containing material (e.g., silicon oxide or tetraethylorthosilicate (TEOS) oxide), a nitrogen-containing oxide material (e.g., silicon oxynitride), a glass material (e.g., borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or fluorinated silicate glass (FSG)), or a combination thereof.

[0217] Alternatively, according to some embodiments, dielectric layer 185 includes a low-k material or a porous dielectric material having a k value lower than the k value of silicon oxide, or lower than about 3.0 or about 2.5. According to some embodiments, anti-reflective layer 184 and dielectric layer 185 are formed using a deposition process and a planarization process such as a chemical mechanical polishing process.

[0218] According to some embodiments, the light transmitting structure 186 is formed over the upper surface 181c of the substrate 181. According to some embodiments, the light transmitting structure 186 includes a dielectric layer 186a, a waveguide structure 186b, a reflective structure 186c, and a dielectric layer 186d.

[0219] According to some embodiments, dielectric layer 186a is formed over upper surface 181c of substrate 181. According to some embodiments, dielectric layer 186a is made of a dielectric material, such as an oxide-containing material (e.g., silicon oxide or tetraethyl orthosilicate (TEOS) oxide), a nitrogen-containing oxide material (e.g., silicon oxynitride), a glass material (e.g., borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or fluorinated silicate glass (FSG)), or a combination thereof. Alternatively, according to some embodiments, dielectric layer 186a includes a low-k material or a porous dielectric material having a k value lower than that of silicon oxide, or lower than approximately 3.0 or approximately 2.5.

[0220] According to some embodiments, dielectric layer 186a is formed using a chemical vapor deposition (CVD) process, such as a low pressure chemical vapor deposition process, a plasma enhanced chemical vapor deposition process, a high density plasma chemical vapor deposition process, an atomic layer deposition process, a spin coating process, a physical vapor deposition process, or other suitable process.

[0221] According to some embodiments, a waveguide structure 186b is formed in dielectric layer 186a. According to some embodiments, waveguide structure 186b overlaps convex surface 181b. According to some embodiments, waveguide structure 186b includes a waveguide layer. According to some embodiments, waveguide structure 186b is made of a nitride-containing material (e.g., silicon nitride) or a lithium-containing material (e.g., lithium nickelate (LiNiO2)).

[0222] According to some embodiments, the reflective structure 186c is formed in the dielectric layer 186a. According to some embodiments, the reflective structure 186c has a trapezoidal shape. According to some embodiments, the reflective structure 186c is located above the convex surface 181b.

[0223] According to some embodiments, the reflective structure 186c is made of metal (e.g., copper, aluminum, gold, silver or tungsten), alloys thereof, semiconductor material (e.g., amorphous silicon), oxide-containing material, dielectric material or another suitable material with high reflectivity having a reflectivity higher than 99%.

[0224] According to some embodiments, a dielectric layer 186d is formed in the reflective structure 186c. According to some embodiments, the dielectric layer 186d has a trapezoidal shape. According to some embodiments, the dielectric layer 186d is made of a dielectric material, such as an oxide-containing material (e.g., silicon oxide or tetraethylorthosilicate (TEOS) oxide), a nitrogen-containing oxide material (e.g., silicon oxynitride), a glass material (e.g., borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or fluorinated silicate glass (FSG)), or a combination thereof.

[0225] Alternatively, according to some embodiments, dielectric layer 186d includes a low-k material or a porous dielectric material having a k value lower than that of silicon oxide, or lower than about 3.0 or about 2.5. In some embodiments, dielectric layers 186a, 186d, and 185 are made of the same material.

[0226] According to some embodiments, the convex curved surface 131 b of the substrate 131 and the convex curved surface 181 b of the substrate 181 together form a convex lens, which can focus the optical signal L. Therefore, according to some embodiments, the path loss of the optical signal L is reduced.

[0227] Figure 4 FIG is a cross-sectional view of a chip package structure 400 according to some embodiments. Figure 4 According to some embodiments, the chip package structure 400 is Figure 3 The chip packaging structure 300 is similar to the chip packaging structure 300, except that the convex surface 131b of the substrate 131 of the optical transmission chip 130 of the chip packaging structure 400 protrudes from the lower surface 131a of the substrate 131, and the convex surfaces 181b of the supporting chip 180 and the substrate 181 of the chip packaging structure 400 protrude from the upper surface 181c of the substrate 181.

[0228] According to some embodiments, the anti-reflection layer 310 conformally covers the convex surface 131 b and the lower surface 131 a of the substrate 131. According to some embodiments, the dielectric layer 320 is formed over the anti-reflection layer 310.

[0229] According to some embodiments, the anti-reflection layer 184 conformally covers the convex surface 181 b and the upper surface 181 c of the substrate 181. According to some embodiments, a dielectric layer 185 is formed over the anti-reflection layer 184.

[0230] Figure 5 FIG is a cross-sectional view of a chip package structure 500 according to some embodiments. Figure 5 As shown, the chip packaging structure 500 and Figure 3 The chip package structure 300 is similar to the chip package structure 500, except that the substrate 131 of the optical transmission chip 130 of the chip package structure 500 further has convex curved surfaces 131c and 131d. According to some embodiments, the substrate 181 of the supporting chip 180 of the chip package structure 500 further has convex curved surfaces 181f and 181d.

[0231] According to some embodiments, the anti-reflection layer 310 conformably covers the inner wall of the recess 131r and the convex curved surfaces 131b, 131c, and 131d in the substrate 131. According to some embodiments, the dielectric layer 320 is formed over the anti-reflection layer 310. According to some embodiments, the portion 131e of the substrate 131 having the convex curved surfaces 131b, 131c, and 131d together form a microlens structure.

[0232] The anti-reflection layer 184 conformally covers the inner wall of the recess 181r and the convex surfaces 181b, 181f, and 181d in the substrate 181. According to some embodiments, a dielectric layer 185 is formed over the anti-reflection layer 184. According to some embodiments, the portion 181e of the substrate 181 having the convex surfaces 181b, 181f, and 181d together form a microlens structure.

[0233] The processes and materials used to form the chip package structures 200 , 300 , 400 , and 500 may be similar to or the same as the processes and materials used to form the chip package structure 100 . Figures 1A to 5 Elements having the same or similar structures and materials are designated by the same reference numerals, and therefore, their detailed description will not be repeated here.

[0234] Other features and processes may also be included. For example, test structures may be included to assist in verification testing of three-dimensional (3D) packages or three-dimensional integrated circuit (3DIC) devices. Test structures may include, for example, test pads formed on a redistribution layer or substrate to allow for testing of the three-dimensional (3D) package or three-dimensional integrated circuit (3DIC), the use of probes and / or probe cards, and the like. Verification testing may be performed on intermediate structures as well as final structures. Additionally, the structures and methods disclosed herein may be used in conjunction with test methods that incorporate intermediate verification of known good chips.

[0235] According to some embodiments, a chip package structure and a method for forming the same are provided. This method (for forming the chip package structure) forms an additional optical transmission chip structure in an optical engine package to change the optical path, thereby reducing the optical path length. Consequently, the path loss of the optical signal is reduced.

[0236] A method for forming a convex lens in an optical engine packaging structure (a method for forming a chip packaging structure) concentrates optical signals, thereby reducing path loss of the optical signals.

[0237] According to some embodiments, a chip packaging structure is provided. The chip packaging structure includes a photonic integrated circuit chip, including a dielectric structure, a photodetector, an optical modulator, and a first waveguide structure located in the dielectric structure. The photodetector and the optical modulator are connected to the first waveguide structure. The chip packaging structure includes an electronic integrated circuit chip located above the photonic integrated circuit chip. The electronic integrated circuit chip includes a transistor. The chip packaging structure includes an optical transmission chip located above the photonic integrated circuit chip. The optical transmission chip includes a substrate, a second waveguide structure, and a first reflective structure. The second waveguide structure and the first reflective structure are located between the substrate and the photonic integrated circuit chip, and a first angle between a first upper surface of the second waveguide structure and a first sidewall of the first reflective structure is greater than 90 degrees and less than 180 degrees, and the first sidewall is adjacent to the second waveguide structure.

[0238] In some embodiments, the chip package structure further includes a dielectric layer located in the first reflective structure.

[0239] In some embodiments, the width of the dielectric layer decreases toward the substrate of the light transmitting chip.

[0240] In some embodiments, the chip packaging structure further includes a third waveguide structure and a second reflective structure. The third waveguide structure is located above the substrate of the optical transmission chip. The second reflective structure is located above the substrate of the optical transmission chip. A second angle between the second upper surface of the third waveguide structure and the second sidewall of the second reflective structure is greater than 0 degrees and less than 90 degrees, and the second sidewall is adjacent to the third waveguide structure.

[0241] In some embodiments, the chip package structure further includes a dielectric layer located in the second reflective structure.

[0242] In some embodiments, the width of the dielectric layer decreases toward the substrate of the light transmitting chip.

[0243] In some embodiments, the chip package structure further includes a molding layer located between the electronic integrated circuit chip and the optical transmission chip.

[0244] In some embodiments, the chip packaging structure further includes a supporting chip located above the electronic integrated circuit chip, the optical transmission chip, and the molding layer.

[0245] In some embodiments, the first waveguide structure overlaps the second waveguide structure in a direction perpendicular to a lower surface of the substrate of the light-transmitting chip.

[0246] In some embodiments, the chip packaging structure further includes a dummy chip located above the optical transmission chip, wherein a first top surface of the dummy chip is substantially flush with a second top surface of the electronic integrated circuit chip.

[0247] According to some embodiments, a chip packaging structure is provided. The chip packaging structure includes a photonic integrated circuit chip, which includes a dielectric structure, a light detector, an optical modulator, and a first waveguide structure located in the dielectric structure. The light detector and the optical modulator are coupled to the first waveguide structure. The chip packaging structure includes an electronic integrated circuit chip located above the photonic integrated circuit chip. The electronic integrated circuit chip includes a transistor. The chip packaging structure includes an optical transmission chip located above the photonic integrated circuit chip. The optical transmission chip includes a substrate, a second waveguide structure, and a first reflective structure. The second waveguide structure and the first reflective structure are located between the substrate and the photonic integrated circuit chip, and the second waveguide structure and the first reflective structure are adjacent to each other. The first reflective structure has a first sidewall and a second sidewall opposite the first sidewall, and a first distance between the first sidewall and the second sidewall decreases toward the substrate.

[0248] In some embodiments, the chip package structure further includes a second reflective structure located above the substrate of the optical transmission chip, wherein the second reflective structure has a third sidewall and a fourth sidewall opposite to the third sidewall, and a second distance between the third sidewall and the fourth sidewall decreases toward the substrate.

[0249] In some embodiments, the first sidewall of the first reflective structure overlaps with the fourth sidewall of the second reflective structure in a direction perpendicular to the lower surface of the substrate of the light-transmitting chip.

[0250] In some embodiments, the chip packaging structure further includes an anti-reflection layer located between the second reflective structure and the substrate of the light transmission chip.

[0251] In some embodiments, the chip packaging structure further includes an anti-reflection layer located between the first reflective structure and the substrate of the light transmission chip.

[0252] According to some embodiments, a chip packaging structure is provided. The chip packaging structure includes a photonic integrated circuit chip, which includes a dielectric structure, a light detector, a light modulator, and a first waveguide structure located within the dielectric structure. The light detector and the light modulator are coupled to the first waveguide structure. The chip packaging structure includes an electronic integrated circuit chip located above the photonic integrated circuit chip. The electronic integrated circuit chip includes a transistor. The chip packaging structure includes an optical transmission chip located above the photonic integrated circuit chip. The optical transmission chip includes a substrate and a second waveguide structure located between the substrate and the photonic integrated circuit chip. The substrate has a first convex surface facing the photonic integrated circuit chip, and the second waveguide structure is located between the first convex surface and the photonic integrated circuit chip.

[0253] In some embodiments, the chip packaging structure further includes a first reflective structure located between the first convex curved surface and the photonic integrated circuit chip and adjacent to the second waveguide structure.

[0254] In some embodiments, the chip packaging structure further includes a supporting chip located above the electronic integrated circuit chip and the optical transmission chip, wherein the supporting chip has a second convex surface facing away from the optical transmission chip.

[0255] In some embodiments, the supporting chip includes a second reflective structure located above the second convex curved surface.

[0256] In some embodiments, the supporting chip includes a third waveguide structure located above the second convex curved surface.

[0257] The above summarizes the features of several embodiments to enable those skilled in the art to better understand the concepts of the embodiments of the present invention. Those skilled in the art will appreciate that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art will also appreciate that such equivalent structures do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and replacements can be made without departing from the spirit and scope of the present invention.

Claims

1. A chip packaging structure, characterized in that: The chip packaging structure includes: A photonic integrated circuit chip comprises a dielectric structure, a photodetector, a light modulator, and a first waveguide structure in the dielectric structure, wherein the photodetector and the light modulator are connected to the first waveguide structure; an electronic integrated circuit chip located above the photonic integrated circuit chip, wherein the electronic integrated circuit chip includes a transistor; and An optical transmission chip is located above the photonic integrated circuit chip, wherein the optical transmission chip includes a substrate, a second waveguide structure, and a first reflective structure. The second waveguide structure and the first reflective structure are located between the substrate and the photonic integrated circuit chip, and a first angle between a first upper surface of the second waveguide structure and a first sidewall of the first reflective structure is greater than 90 degrees and less than 180 degrees, and the first sidewall is adjacent to the second waveguide structure.

2. The chip packaging structure according to claim 1, wherein: Also includes: A dielectric layer is located in the first reflective structure.

3. The chip packaging structure according to claim 2, wherein: A width of the dielectric layer decreases toward the substrate of the light transmission chip.

4. The chip packaging structure according to claim 1 or 2, wherein: Also includes: a third waveguide structure located above the substrate of the optical transmission chip; as well as A second reflective structure is located above the substrate of the optical transmission chip, wherein a second angle between a second upper surface of the third waveguide structure and a second sidewall of the second reflective structure is greater than 0 degrees and less than 90 degrees, and the second sidewall is adjacent to the third waveguide structure.

5. A chip packaging structure, characterized in that: The chip packaging structure includes: A photonic integrated circuit chip comprises a dielectric structure, a photodetector, a light modulator, and a first waveguide structure located in the dielectric structure, wherein the photodetector and the light modulator are coupled to the first waveguide structure; an electronic integrated circuit chip located above the photonic integrated circuit chip, wherein the electronic integrated circuit chip includes a transistor; and An optical transmission chip is located above the photonic integrated circuit chip, wherein the optical transmission chip includes a substrate, a second waveguide structure, and a first reflective structure. The second waveguide structure and the first reflective structure are located between the substrate and the photonic integrated circuit chip, and the second waveguide structure and the first reflective structure are adjacent to each other. The first reflective structure has a first sidewall and a second sidewall opposite to the first sidewall, and a first distance between the first sidewall and the second sidewall decreases toward the substrate.

6. The chip packaging structure according to claim 5, wherein: Also includes: A second reflective structure is located above the substrate of the optical transmission chip, wherein the second reflective structure has a third sidewall and a fourth sidewall opposite to the third sidewall, and a second distance between the third sidewall and the fourth sidewall decreases toward the substrate.

7. The chip packaging structure according to claim 6, wherein: The first sidewall of the first reflective structure overlaps with the fourth sidewall of the second reflective structure in a direction perpendicular to a lower surface of the substrate of the optical transmission chip.

8. A chip packaging structure, characterized in that: The chip packaging structure includes: A photonic integrated circuit chip comprises a dielectric structure, a photodetector, a light modulator, and a first waveguide structure located in the dielectric structure, wherein the photodetector and the light modulator are coupled to the first waveguide structure; an electronic integrated circuit chip located above the photonic integrated circuit chip, wherein the electronic integrated circuit chip includes a transistor; and An optical transmission chip is located above the photonic integrated circuit chip, wherein the optical transmission chip includes a substrate and a second waveguide structure. The second waveguide structure is located between the substrate and the photonic integrated circuit chip. The substrate has a first convex curved surface facing the photonic integrated circuit chip, and the second waveguide structure is located between the first convex curved surface and the photonic integrated circuit chip.

9. The chip packaging structure according to claim 8, wherein: Also includes: A first reflective structure is located between the first convex surface and the photonic integrated circuit chip and is adjacent to the second waveguide structure.

10. The chip packaging structure according to claim 9, wherein: Also includes: A supporting chip is located above the electronic integrated circuit chip and the optical transmission chip, wherein the supporting chip has a second convex surface facing away from the optical transmission chip.

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