Circuit for converting large current into small voltage for control chip

Abstract

The utility model relates to a circuit for converting large current into small voltage for a control chip, and relates to the technical field of power electronics. The control chip comprises a rectification unit, a comparison unit, an alternating current output end AC1 and an alternating current output end AC2, the alternating current output end AC1 and the alternating current output end AC2 are electrically connected to the input end of the rectification unit, the output end of the rectification unit is electrically connected to the input end of the comparison unit, and the output end of the comparison unit is electrically connected to the input end of the control chip. According to the invention, the control chip is prevented from being damaged by large current to the greatest extent.

Description

Technical Field

[0001] The present application relates to the technical field of power electronics, and in particular to a high current to low voltage conversion circuit for a control chip. Background Art

[0002] In the field of electronic technology, with the continuous development and advancement of electronic equipment, the importance of chips as core components of control systems has become increasingly prominent. In order to ensure the normal operation of the chip, it is usually necessary to convert the external large current into a smaller voltage suitable for the chip to operate. This can not only effectively extend the service life of the chip, but also improve the overall performance of the system, reduce energy consumption, and make the equipment more stable and reliable. To meet the above needs, existing related technologies usually use rectification and voltage stabilization circuits to achieve the conversion of large current to small voltage. Common rectification schemes include half-wave rectification, full-wave rectification, etc. These rectification methods can effectively convert AC power into DC power. In terms of voltage regulation, the commonly used means are linear regulators or switching regulators, which can provide stable output voltage according to specific application requirements to ensure the safe operation of load devices.

[0003] However, existing rectification and voltage regulation technologies have limitations, particularly when converting high currents to low voltages. Exposure to excessive current can easily lead to chip overheating and even damage. Therefore, preventing high current from damaging the control chip has become a critical issue that needs to be addressed. Utility Model Content

[0004] In order to minimize the damage caused by large current to the control chip, the present application provides a large current to small voltage conversion circuit for the control chip.

[0005] The present application provides a high current to low voltage conversion circuit for controlling a chip using the following technical solution:

[0006] A high-current-to-low-voltage circuit for a control chip includes a rectifier unit and a comparison unit, as well as an AC output terminal AC1 and an AC output terminal AC2. The AC output terminals AC1 and AC2 are electrically connected to the input terminal of the rectifier unit, the output terminal of the rectifier unit is electrically connected to the input terminal of the comparison unit, and the output terminal of the comparison unit is electrically connected to the input terminal of the control chip.

[0007] By adopting the above technical solution, the rectifier unit can be used to convert the AC voltage into a DC voltage, and the comparison unit can be set to convert the large current into a small voltage, so that the voltage output to the input end of the subsequent control chip can be controlled within an appropriate range; and when certain currents do not meet the input current conditions of the control chip, the comparison unit can also process the large current to facilitate subsequent input chip.

[0008] Preferably, the comparison unit includes an operational amplifier U1 and a reference power supply VREF, the output end of the rectifier unit is electrically connected to the inverting input end of the operational amplifier U1, the power output end of the reference power supply VREF is grounded through resistors R5 and R7 in sequence, and the power output end of the reference power supply VREF is also connected to the non-inverting input end of the operational amplifier through resistor R6; the output end of the operational amplifier U1 is also electrically connected to the transistor Q1, the output end of the operational amplifier U1 is electrically connected to the base of the transistor Q1, the voltage output end of the reference power supply VREF is electrically connected to the collector of the transistor Q1, and the emitter of the transistor Q1 is electrically connected to the input end of the control chip.

[0009] By adopting the above technical solution, when the voltage value of the inverting input terminal of the operational amplifier U1 is greater than the voltage value of the non-inverting input terminal of the operational amplifier U1, it means that the current at the front end is too large. At this time, the output terminal of the operational amplifier U1 outputs a low level, thereby turning off the transistor Q1, and the output voltage of the reference power supply VREF cannot be input to the input terminal of the subsequent control chip, thereby avoiding damage to the control chip by large current; when the voltage value of the inverting input terminal of the operational amplifier U1 is less than the voltage value of the non-inverting input terminal of the operational amplifier U1, the output terminal of the operational amplifier U1 outputs a high level, thereby turning on the transistor Q1, and the output voltage of the reference power supply VREF can be input to the input terminal of the subsequent control chip.

[0010] Preferably, the non-inverting input terminal of the operational amplifier U1 is further grounded via a capacitor C3.

[0011] By adopting the above technical solution, the capacitor C3 is used to improve the stability of the voltage input to the non-inverting input terminal of the operational amplifier U1.

[0012] Preferably, the inverting input terminal of the operational amplifier U1 is further grounded via a capacitor C2.

[0013] By adopting the above technical solution, the capacitor C2 is used to improve the stability of the voltage input to the inverting input terminal of the operational amplifier U1.

[0014] Preferably, the comparison unit further includes a power supply V1, a voltage output end of the power supply V1 being electrically connected to a power supply end of the operational amplifier U1, a ground end of the operational amplifier U1 being grounded, and the voltage output end of the power supply V1 being also grounded through a capacitor C4.

[0015] By adopting the above technical solution, the operational amplifier U1 can be powered and operated by setting the power supply V1, and the stability of the voltage output of the power supply V1 can be improved by setting the capacitor C4, so as to ensure the stable operation of the operational amplifier U1.

[0016] Preferably, the rectifier unit includes a rectifier diode D1, a rectifier diode D2, a rectifier diode D3, and a rectifier diode D4, the AC output terminal AC1 is electrically connected to the positive electrode of the rectifier diode D1 and the negative electrode of the rectifier diode D2, the AC output terminal AC2 is electrically connected to the positive electrode of the rectifier diode D3 and the negative electrode of the rectifier diode D4, the negative electrode of the rectifier diode D1 is electrically connected to the negative electrode of the rectifier diode D3, the positive electrode of the rectifier diode D2 is electrically connected to the positive electrode of the rectifier diode D4, and the negative electrode of the rectifier diode D3 is set as the output end of the rectifier unit.

[0017] By adopting the above technical solution, alternating current is converted into direct current through the rectifier diodes D1, D2, D3, and D4, thereby achieving effective rectification of external large current.

[0018] Preferably, the emitter of the transistor Q1 is grounded via a resistor R8, a capacitor C5, and a resistor R9 in sequence; the non-inverting input terminal of the operational amplifier U1 is electrically connected to a PMOS transistor Q2, the drain of the PMOS transistor Q2 is electrically connected to the non-inverting input terminal of the operational amplifier U1, the gate of the PMOS transistor Q2 is electrically connected to the connection point between the capacitor C5 and the resistor R9, and the source of the PMOS transistor Q2 is grounded; the drain of the PMOS transistor Q2 is electrically connected to a diode D3, the anode of the diode D3 is electrically connected to the drain of the PMOS transistor Q2, and the cathode of the diode D3 is set as a control signal output terminal.

[0019] By adopting the above technical solution, when the transistor Q1 is turned off, the gate of the PMOS tube Q2 is grounded and turned on. At this time, the voltage input to the non-inverting input terminal of the operational amplifier U1 can output a control signal through the diode D3.

[0020] Preferably, the device further includes a DELAY signal input terminal provided at the front end, the emitter of the transistor Q1 is electrically connected to a diode D4, the anode of the diode D4 is electrically connected to the emitter of the transistor Q1, the cathode of the diode D4 is grounded via resistors R11 and R12 in sequence, and a PMOS transistor Q4 is electrically connected to the connection point between the resistors R11 and R12; the gate of the PMOS transistor Q4 is electrically connected to the connection point between the resistors R11 and R12, the source of the PMOS transistor Q4 is grounded, the drain of the PMOS transistor Q4 is electrically connected to the DELAY signal input terminal via a resistor R13, and the drain of the PMOS transistor Q4 is set as a DELAY signal output terminal.

[0021] By adopting the above technical solution, when transistor Q1 is turned on, PMOS transistor Q4 is turned off, and the signal input to the DELAY signal input terminal can be output from the DELAY signal output terminal through resistor R13. When transistor Q1 is turned off, PMOS transistor Q4 is turned on, and the signal input to the DELAY signal input terminal cannot be output from the DELAY signal output terminal.

[0022] Preferably, it further includes a diode D1, a diode D2 and a transistor Q3, the anode of the diode D1 is electrically connected to the non-inverting input terminal of the operational amplifier U1, the cathode of the diode D1 is electrically connected to the cathode of the diode D2, the anode of the diode D2 is electrically connected to the emitter of the transistor Q1, and the cathode of the diode D2 is electrically connected to the collector of the transistor Q3; the DELAY signal input terminal is electrically connected to the base of the transistor Q3, and the emitter of the transistor Q3 is grounded.

[0023] By adopting the above technical solution, when the DELAY signal output terminal outputs a high-level signal, the transistor Q3 is turned on, that is, the voltage input to the non-inverting input terminal of the operational amplifier U1 is pulled down to 0V, and the operational amplifier U1 outputs a low level; when the DELAY signal output terminal outputs a low-level signal, the transistor Q3 is cut off, and the voltage of the non-inverting input terminal of the operational amplifier U1 can be obtained through the reference power supply VREF, thereby realizing the automatic opening and closing of the DELAY function.

[0024] Preferably, a power supply V2 is further included, and a voltage output terminal of the power supply V2 is electrically connected to the cathodes of the diode D1 and the diode D2 via a resistor R10.

[0025] By adopting the above technical solution, the clamping protection function can be achieved by setting the power supply V2.

[0026] In summary, this application includes at least one of the following beneficial technical effects:

[0027] 1. By setting up the operational amplifier U1 and its surrounding circuits, the working state of the transistor Q1 can be accurately controlled according to the size of the input current, thereby achieving high-precision voltage conversion and improving the stability of the output voltage;

[0028] 2. By setting the DELAY signal input terminal and the corresponding circuit structure, the transmission of the DELAY signal can be effectively controlled to ensure the stability of the output voltage and the timing control accuracy under different load conditions;

[0029] 3. By setting rectifier diodes D1, D2, D3, and D4, AC power is converted into DC power, achieving effective rectification of external large current. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a circuit diagram of an embodiment of the present application.

[0031] Reference numerals: 1, rectifier unit; 2, comparison unit. DETAILED DESCRIPTION

[0032] The following is combined with Figure 1 This application is described in further detail.

[0033] The embodiment of the present application discloses a high current to low voltage conversion circuit for controlling a chip.

[0034] Reference Figure 1 A high-current-to-low-voltage conversion circuit for a control chip includes a magnetic ring, a rectifier unit 1, and a comparison unit 2. The magnetic ring is electrically connected to two AC output terminals, AC1 and AC2. These terminals are fed into the input of the comparison unit 2 via the rectifier unit 1, converting AC power into DC power. The output of the comparison unit 2 is electrically connected to the input of the control chip, enabling the comparison unit 2 to limit excessive current.

[0035] Rectifier unit 1 includes rectifier diodes D1, D2, D3, and D4. AC output terminal AC1 is electrically connected to the anode of rectifier diode D1 and the cathode of rectifier diode D2. AC output terminal AC2 is electrically connected to the anode of rectifier diode D3 and the cathode of rectifier diode D4. The cathode of rectifier diode D1 is electrically connected to the cathode of rectifier diode D3, and the anode of rectifier diode D2 is electrically connected to the anode of rectifier diode D4, thereby converting AC power into DC power. The cathode of rectifier diode D3 is connected to the output terminal DC of rectifier unit 1, and the anode of rectifier diode D4 is grounded via capacitor C1. Rectifier unit 1 converts the AC power from AC output terminals AC1 and AC2 into DC power, achieving stable power supply.

[0036] Comparator unit 2 includes an operational amplifier U1 and a power supply V1. In this embodiment, the power supply voltage of power supply V1 is set to 12.2V. The voltage output terminal of power supply V1 is electrically connected to the power supply terminal of operational amplifier U1. The ground terminal of operational amplifier U1 is also grounded. The voltage output terminal of power supply V1 is also grounded via capacitor C4. The output terminal DC is grounded via resistor R1 and capacitor C1, respectively. Resistor R2 is connected in parallel across resistor R1, and resistor R3 is connected in parallel across resistor R2. The output terminal DC is also electrically connected to the inverting input terminal of operational amplifier U1 via resistor R4, thereby reducing the voltage input to the inverting input terminal of operational amplifier U1 to within a normal range. Furthermore, the inverting input terminal of operational amplifier U1 is also grounded via capacitor C2, which improves the stability of the voltage input to the inverting input terminal of operational amplifier U1.

[0037] Comparator unit 2 also includes a reference power supply VREF. In this embodiment, the power supply voltage of reference power supply VREF is set to 5V. The voltage output terminal of reference power supply VREF is connected to ground via resistor R5 and capacitor C1. One end of resistor R5 is connected to ground via resistor R7, and the other end of resistor R5 is electrically connected to the non-inverting input terminal of operational amplifier U1 via resistor R6. The non-inverting input terminal of operational amplifier U1 is also grounded via capacitor C3. Capacitor C3 is used to improve the stability of the voltage input to the non-inverting input terminal of operational amplifier U1.

[0038] The output of operational amplifier U1 is electrically connected to transistor Q1, and the output of operational amplifier U1 is electrically connected to the base of transistor Q1. The voltage output of reference power supply VREF is electrically connected to the collector of transistor Q1, and the emitter of transistor Q1 is electrically connected to the input of a subsequent control chip. When the voltage value at the inverting input of operational amplifier U1 is less than the voltage value at the non-inverting input of operational amplifier U1, the output of operational amplifier U1 outputs a high level, thereby turning on transistor Q1 and allowing the output voltage of reference power supply VREF to be input to the input of the subsequent control chip. When the voltage value at the inverting input of operational amplifier U1 is greater than the voltage value at the non-inverting input of operational amplifier U1, the output of operational amplifier U1 outputs a low level, thereby turning off transistor Q1 and preventing the output voltage of reference power supply VREF from being input to the input of the subsequent control chip, thereby preventing damage to the control chip from high current.

[0039] The emitter of transistor Q1 is connected to ground via resistor R8, capacitor C5, and resistor R9, in sequence. The non-inverting input of operational amplifier U1 is electrically connected to a PMOS transistor Q2. The drain of PMOS transistor Q2 is electrically connected to the non-inverting input of operational amplifier U1. The gate of PMOS transistor Q2 is electrically connected to the connection point between capacitor C5 and resistor R9. The source of PMOS transistor Q2 is grounded. The drain of PMOS transistor Q2 is electrically connected to diode D3. The anode of diode D3 is electrically connected to the drain of PMOS transistor Q2, and the cathode of diode D3 is configured as the control signal output terminal CONTROL. When transistor Q1 is turned off, the gate of PMOS transistor Q2 is grounded and conductive. At this time, the voltage input to the non-inverting input of operational amplifier U1 can output a control signal through diode D3.

[0040] The embodiment of the present application also includes a diode D1, a diode D2, and a transistor Q3. The positive electrode of the diode D2 is electrically connected to the connection point between the resistor R8 and the capacitor C5, the negative electrode of the diode D1 is electrically connected to the negative electrode of the diode D2, the positive electrode of the diode D1 is electrically connected to the non-inverting input terminal of the operational amplifier U1, and the negative electrode of the diode D2 is electrically connected to the collector of the transistor Q3. The emitter of the transistor Q3 is grounded. The embodiment of the present application also includes a power supply V2. In this embodiment, the power supply voltage value of the power supply V2 is set to 12V. The voltage output terminal of the power supply V2 is electrically connected to the negative electrodes of the diode D1 and the diode D2 through the resistor R10 to realize the clamping protection function. The DELAY signal input terminal DELAY_IN is electrically connected to the base of the transistor Q3. When the DELAY signal output terminal DELAY_OUT outputs a high-level signal, the transistor Q3 is turned on, that is, the voltage input to the non-inverting input terminal of the operational amplifier U1 is pulled down to 0V, and the operational amplifier U1 outputs a low level; when the DELAY signal output terminal DELAY_OUT outputs a low-level signal, the transistor Q3 is cut off, and the voltage of the non-inverting input terminal of the operational amplifier U1 can be obtained through the reference power supply VREF, thereby realizing the automatic opening and closing of the DELAY function.

[0041] The emitter of transistor Q1 is electrically connected to diode D4. The anode of diode D4 is electrically connected to the emitter of transistor Q1. The cathode of diode D4 is connected to ground via resistors R11 and R12, respectively. The connection point between resistors R11 and R12 is also connected to ground via capacitor C6. A PMOS transistor Q4 is electrically connected to the connection point between resistors R11 and R12. The gate of PMOS transistor Q4 is electrically connected to the connection point between resistors R11 and R12. The source of PMOS transistor Q4 is grounded. The drain of PMOS transistor Q4 is electrically connected to the DELAY signal input terminal DELAY_IN via resistor R13. The drain of PMOS transistor Q4 is also connected to the DELAY signal output terminal DELAY_OUT. When transistor Q1 is turned on, PMOS transistor Q4 is turned off, and the signal input to DELAY signal input terminal DELAY_IN can be output to DELAY signal output terminal DELAY_OUT via resistor R13. When the transistor Q1 is turned off, the PMOS transistor Q4 is turned on, and the signal input from the DELAY signal input terminal DELAY_IN cannot be output from the DELAY signal output terminal DELAY_OUT.

[0042] The implementation principle of a large current to small voltage conversion circuit for a control chip in an embodiment of the present application is as follows: alternating current can be converted into direct current through the rectifier unit 1, thereby realizing effective rectification of external large currents; through the cooperation of the operational amplifier U1 and its related circuits, the large current input to the control chip can be reduced in voltage and limited in current, ensuring that the input current is stable within a normal range and preventing the control chip from overloading.

[0043] The above are all preferred embodiments of the present application, and are not intended to limit the scope of protection of the present application. Therefore, any equivalent changes made based on the structure, shape, and principle of the present application should be included in the scope of protection of the present application.

Claims

1. A high current to low voltage conversion circuit for a control chip, characterized by: The invention comprises a rectifier unit (1) and a comparison unit (2), as well as an AC output terminal AC1 and an AC output terminal AC2, wherein the AC output terminal AC1 and the AC output terminal AC2 are electrically connected to the input terminal of the rectifier unit (1), the output terminal of the rectifier unit (1) is electrically connected to the input terminal of the comparison unit (2), and the output terminal of the comparison unit (2) is electrically connected to the input terminal of the control chip.

2. The high current to low voltage conversion circuit for a control chip according to claim 1, characterized in that: The comparison unit (2) includes an operational amplifier U1 and a reference power supply VREF. The output end of the rectifier unit (1) is electrically connected to the inverting input end of the operational amplifier U1. The power output end of the reference power supply VREF is grounded through resistors R5 and R7 in sequence, and the power output end of the reference power supply VREF is also connected to the non-inverting input end of the operational amplifier through resistor R6. The output end of the operational amplifier U1 is also electrically connected to a transistor Q1. The output end of the operational amplifier U1 is electrically connected to the base of the transistor Q1. The voltage output end of the reference power supply VREF is electrically connected to the collector of the transistor Q1, and the emitter of the transistor Q1 is electrically connected to the input end of the control chip.

3. The high current to low voltage conversion circuit for a control chip according to claim 2, characterized in that: The non-inverting input terminal of the operational amplifier U1 is also grounded via a capacitor C3.

4. The high current to low voltage conversion circuit for a control chip according to claim 2, characterized in that: The inverting input terminal of the operational amplifier U1 is also grounded via a capacitor C2.

5. The high current to low voltage conversion circuit for a control chip according to claim 2, characterized in that: The comparison unit (2) further comprises a power supply V1, a voltage output terminal of the power supply V1 being electrically connected to a power supply terminal of the operational amplifier U1, a ground terminal of the operational amplifier U1 being grounded, and the voltage output terminal of the power supply V1 being also grounded via a capacitor C4.

6. The high current to low voltage conversion circuit for a control chip according to claim 1, characterized in that: The rectifier unit (1) includes a rectifier diode D1, a rectifier diode D2, a rectifier diode D3, and a rectifier diode D4. The AC output terminal AC1 is electrically connected to the positive electrode of the rectifier diode D1 and the negative electrode of the rectifier diode D2. The AC output terminal AC2 is electrically connected to the positive electrode of the rectifier diode D3 and the negative electrode of the rectifier diode D4. The negative electrode of the rectifier diode D1 is electrically connected to the negative electrode of the rectifier diode D3. The positive electrode of the rectifier diode D2 is electrically connected to the positive electrode of the rectifier diode D4. The negative electrode of the rectifier diode D3 is set as the output terminal of the rectifier unit (1).

7. The high current to low voltage conversion circuit for a control chip according to claim 2, characterized in that: The emitter of the transistor Q1 is grounded via a resistor R8, a capacitor C5, and a resistor R9 in sequence; the non-inverting input terminal of the operational amplifier U1 is electrically connected to a PMOS transistor Q2, the drain of the PMOS transistor Q2 is electrically connected to the non-inverting input terminal of the operational amplifier U1, the gate of the PMOS transistor Q2 is electrically connected to the connection point between the capacitor C5 and the resistor R9, and the source of the PMOS transistor Q2 is grounded; the drain of the PMOS transistor Q2 is electrically connected to a diode D3, the anode of the diode D3 is electrically connected to the drain of the PMOS transistor Q2, and the cathode of the diode D3 is set as a control signal output terminal.

8. The high current to low voltage conversion circuit for a control chip according to claim 2, characterized in that: The device further includes a DELAY signal input terminal provided at the front end, the emitter of the transistor Q1 is electrically connected to a diode D4, the anode of the diode D4 is electrically connected to the emitter of the transistor Q1, the cathode of the diode D4 is grounded via resistors R11 and R12 in sequence, and a PMOS transistor Q4 is electrically connected to the connection point between the resistors R11 and R12; the gate of the PMOS transistor Q4 is electrically connected to the connection point between the resistors R11 and R12, the source of the PMOS transistor Q4 is grounded, the drain of the PMOS transistor Q4 is electrically connected to the DELAY signal input terminal via a resistor R13, and the drain of the PMOS transistor Q4 is set as a DELAY signal output terminal.

9. The high current to low voltage conversion circuit for a control chip according to claim 8, characterized in that: It also includes a diode D1, a diode D2 and a transistor Q3, the anode of the diode D1 is electrically connected to the non-inverting input terminal of the operational amplifier U1, the cathode of the diode D1 is electrically connected to the cathode of the diode D2, the anode of the diode D2 is electrically connected to the emitter of the transistor Q1, and the cathode of the diode D2 is electrically connected to the collector of the transistor Q3; the DELAY signal input terminal is electrically connected to the base of the transistor Q3, and the emitter of the transistor Q3 is grounded.

10. The high current to low voltage conversion circuit for a control chip according to claim 9, characterized in that: The device further includes a power supply V2 , wherein a voltage output terminal of the power supply V2 is electrically connected to the cathodes of the diode D1 and the diode D2 via a resistor R10 .

Images