Semiconductor device

Abstract

The present disclosure provides a semiconductor device including a substrate, a first die, a second die, a stress buffer structure, and a metal layer. The first die and the second die are bonded to the first side of the substrate. A stress buffer structure is over the first die and the second die, where the stress buffer structure includes a bottom portion of the first copper via extending through the first insulating layer, an intermediate portion of the first copper via extending through the second insulating layer, and a top portion of the first copper via extending through the third insulating layer, wherein a middle portion of the first copper via is disposed between a bottom portion of the first copper via and a top portion of the first copper via, and wherein a diameter of the middle portion of the first copper via is less than a plurality of diameters of the bottom portion of the first copper via and the top portion of the first copper via. A metal layer is over the stress buffer structure.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic equipment. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconducting layers over a semiconductor substrate; and using lithography to pattern the various material layers to form circuit elements and components. Dozens or hundreds of integrated circuits are typically fabricated on a single semiconductor wafer. Individual dies are singulated by sawing the integrated circuits along scribe lines. The individual dies are then packaged separately, for example, in multi-wafer modules or other types of packaging.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (eg, transistors, diodes, resistors, capacitors, etc.) by continuously reducing minimum feature sizes, which allows more components to be integrated into a given area. Utility Model Content

[0004] The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a first die, a second die, a stress buffer structure, and a metal layer. The first die and the second die are bonded to a first side of the substrate. The stress buffer structure is above the first die and the second die, wherein the stress buffer structure includes a bottom portion of a first copper via extending through a first insulating layer, a middle portion of the first copper via extending through a second insulating layer, and a top portion of the first copper via extending through a third insulating layer, wherein the middle portion of the first copper via is disposed between the bottom portion and the top portion of the first copper via, and wherein a diameter of the middle portion of the first copper via is smaller than a plurality of diameters of the bottom portion and the top portion of the first copper via. The metal layer is above the stress buffer structure.

[0005] The present disclosure also provides a semiconductor device. The semiconductor device includes a first die, a second die, an encapsulant, and a stress buffering structure. The first die is above and bonded to a first side of the second die. The encapsulant surrounds the first die. The stress buffering structure is above the first die and the encapsulant, wherein the stress buffering structure includes a plurality of insulating layers and a plurality of first copper vias, wherein each of the first copper vias extends through the insulating layer, and a percentage of a total volume of the first copper vias to a total volume of the stress buffering structure is in a range from 10% to 30%, and each of the first copper vias includes a bottom portion and a middle portion, wherein a diameter of the middle portion is smaller than a diameter of the bottom portion.

[0006] The present disclosure further provides a semiconductor device. The semiconductor device includes a bottom die, a top die, a mold layer, a first stress buffer layer, a second stress buffer layer, and a heat sink. The top die is bonded to the bottom die. The mold layer surrounds the top die. A first stress buffer layer is above the top die, the first stress buffer layer including a plurality of bottom portions of a plurality of first copper vias extending through a first dielectric layer, wherein a first one of the bottom portions is in physical contact with the silicon substrate of the top die. A second stress buffer layer is above the first stress buffer layer, the second stress buffer layer including a plurality of middle portions of a first copper via extending through the second dielectric layer, wherein each of the middle portions overlaps and is in physical contact with a corresponding one of the bottom portions, and each of the middle portions has a smaller diameter than each of the bottom portions. A heat sink is above the first copper vias and thermally coupled to the first copper vias. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The aspects of this disclosure are as follows: Figure 1 The following detailed description is best understood when read together. Please note that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 and Figure 2 illustrates a cross-sectional view of an intermediate step during a process for forming a semiconductor die according to some embodiments;

[0009] Figures 3 to 12B illustrates top-down and cross-sectional views of intermediate steps during a process for forming an integrated wafer package according to some embodiments;

[0010] 13A to 13B illustrates top-down and cross-sectional views of intermediate steps during a process for forming an integrated wafer package according to some embodiments;

[0011] Figure 14 Illustrated are cross-sectional views of intermediate steps during a process for forming an integrated wafer package, in accordance with some embodiments.

[0012]

Explanation of symbols

[0013] 10: Wafer

[0014] 20: Wafer

[0015] 100: Integrated chip packaging

[0016] 117:Substrate

[0017] 119: Interconnection structure

[0018] 121: bonding layer

[0019] 123:Joint pad

[0020] 129: Cutting Path

[0021] 132: Encapsulating agent

[0022] 133: Stress buffer structure

[0023] 133a: bottom stress buffer layer

[0024] 133b: intermediate stress buffer layer

[0025] 133c: Top stress buffer layer

[0026] 134: Insulation layer

[0027] 136: Bottom through hole

[0028] 138: Insulation layer

[0029] 140: Middle through hole

[0030] 142: Insulation layer

[0031] 144: Top through hole

[0032] 145:Combined through hole

[0033] 146:Metal layer

[0034] 148: Thermal interface materials

[0035] 150:Semiconductor grains

[0036] 152:Metal layer

[0037] 154:Metal heat sink

[0038] 156: Hotspot

[0039] 157: District 1

[0040] 158: District 2

[0041] 211:Substrate perforation

[0042] 217:Substrate

[0043] 219: Interconnection Structure

[0044] 221: Bonding layer

[0045] 223:Joint pad

[0046] 234: Dielectric layer

[0047] 236:Metalized pattern

[0048] 238:Conductive connector

[0049] 240:Packaging substrate

[0050] 246:Joint pad

[0051] 248:Solder resist

[0052] 250: bottom filler

[0053] 252:Joint pad

[0054] 254:Conductive connector

[0055] 260:Substrate core

[0056] AA:Line

[0057] D1: diameter

[0058] D2: diameter

[0059] D3: diameter

[0060] D4: Diameter

[0061] H1: Height

[0062] S1: Spacing

[0063] S2: Spacing

[0064] S3: Spacing

[0065] S4: Spacing

[0066] S5: Spacing

[0067] S6: Spacing

[0068] T1:Thickness

[0069] T2: Thickness

[0070] T3:Thickness

[0071] T4: Total thickness

[0072] XX: Line

[0073] x: direction

[0074] YY:Line

[0075] y: direction DETAILED DESCRIPTION

[0076] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these components and configurations are merely examples and are not intended to be restrictive. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first and second features are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first and second features so that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for simplicity and clarity purposes and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0077] Additionally, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and the like, may be used herein for ease of description to describe the relationship of one or more elements or features to another or further elements or features as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0078] Various embodiments provide methods for forming a 3D integrated chip (3DIC) package, such as a system on integrated chip (SoIC) package. Forming the 3DIC package includes bonding two or more semiconductor dies (e.g., a top die) to a semiconductor wafer (e.g., a bottom die). A stress buffering structure is formed over and in physical contact with the two or more semiconductor dies (e.g., the top die). The stress buffering structure includes one or more insulating layers having a plurality of copper vias extending through the one or more insulating layers, wherein a total volume of the plurality of copper vias and a percentage of a total volume of the stress buffering structure are in a range of 10% to 30%. A metal layer is formed over the stress buffering structure, and a thermal interface material (TIM) is applied to a top surface of the metal layer. A metal heat sink (e.g., a copper lid) is then placed over the 3DIC package, and the metal heat sink is in contact with the metal layer via the TIM. Advantageous features of one or more embodiments described herein include a reduction in mechanical stress due to a mismatch in the coefficients of thermal expansion between a first material (e.g., copper) of a metal heat sink and a second material (e.g., silicon) of two or more semiconductor dies (e.g., the top die). A stress buffering structure acts as an intermediate interface, absorbing or relaxing the mechanical stress caused by the mismatch in the coefficients of thermal expansion between the first and second materials. This reduces the risk of cracking at the interface between the two or more semiconductor dies (e.g., the top die) and the metal heat sink, and reduces the risk of delamination between the metal heat sink and the two or more semiconductor dies (e.g., the top die). Furthermore, the metal heat sink and stress buffering structure allow for improved and more efficient heat dissipation from the integrated chip package, resulting in improved device reliability and device performance.

[0079] Figures 1 to 14 Cross-sectional and top-down views illustrate intermediate steps during a process for forming an integrated wafer package 100, according to some embodiments. Figure 1, a wafer 10 is shown. The wafer 10 includes semiconductor dies 150. Each of the semiconductor dies 150 may be a logic die (e.g., an application processor (AP), a central processing unit (CPU), a microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a hybrid memory cube (HBC), a static random access memory (SRAM) die, a wide input / output (wideIO) memory die, a magnetoresistive random access memory (mRAM) die, a resistive random access memory (rRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a micro-electro-mechanical-system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), or a microcontroller (MCU) die. The wafer 10 may include a processor (DSP) die, a front-end die (e.g., an analog front-end (AFE) die), a biomedical die, or the like. Each semiconductor die 150 may also be a system-on-chip (SoC) die or the like. Wafer 10 may include a substrate 117 (e.g., a semiconductor substrate), an interconnect structure 119 disposed on substrate 117, a bonding layer 121 disposed on interconnect structure 119, and bonding pads 123 disposed on bonding layer 121 and exposed at the front surface of wafer 10. The side of wafer 10 including the exposed bonding pads 123 and bonding layer 121 may also be referred to as the front side of wafer 10.

[0080] The substrate 117 of the wafer 10 may comprise a crystalline silicon wafer. Depending on design requirements, the substrate 117 may include various doped regions (e.g., a p-type substrate or an n-type substrate). In some embodiments, the doped regions may be doped with p-type or n-type dopants. The doped regions may be doped with p-type dopants such as boron or BF2; n-type dopants such as phosphorus or arsenic; and / or combinations thereof. The doped regions may be configured for n-type fin-type field effect transistors (FinFETs) and / or p-type FinFETs. In some alternative embodiments, the substrate 117 may comprise the active layer of a semiconductor-on-insulator (SOI) substrate. The substrate 117 may comprise other semiconductor materials, such as germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates such as multi-layer or gradient substrates may also be used.

[0081] Active and / or passive devices such as transistors, diodes, capacitors, resistors, etc. may be formed in and / or on substrate 117. The devices may be interconnected by interconnect structure 119. Interconnect structure 119 electrically connects the devices on substrate 117 to form one or more integrated circuits. Interconnect structure 119 may include one or more dielectric layers (e.g., one or more interlayer dielectric (ILD) layers, intermetal dielectric (IMD) layers, or the like) and interconnect wires or metal patterns embedded in the one or more dielectric layers. The material of the one or more dielectric layers may include silicon oxide (SiO x , where x>0), silicon nitride (SiN x , where x>0), silicon oxynitride (SiO x N y , where x>0 and y>0) or other suitable dielectric materials. The interconnect wires may include metal wires. For example, the interconnect wires include copper wires, copper pads, aluminum pads, or combinations thereof formed using one or more single damascene processes, dual damascene processes, or the like. The side of wafer 10 including the exposed backside surface of substrate 117 may also be referred to as the backside of wafer 10.

[0082] The bonding layer 121 may include a dielectric layer. The bonding pad 123 is embedded in the bonding layer 121 and allows the connection of the interconnect structure 119 to the device on the substrate 117. The material of the bonding layer 121 may be silicon oxide (SiO x , where x>0), silicon nitride (SiNx , where x>0), silicon oxynitride (SiO x N y , where x>0 and y>0), tetraethylorthosilicate (TEOS), or other suitable dielectric materials, and bonding pad 123 may include a conductive pad (e.g., a copper pad), a conductive via (e.g., a copper via), or a combination thereof. Bonding layer 121 may be formed by depositing a dielectric material over interconnect structure 119 using a chemical vapor deposition (CVD) process (e.g., a plasma-enhanced CVD process or other suitable process); patterning the dielectric material to form bonding layer 121 including openings or vias; and filling the openings or vias defined in bonding layer 121 with a conductive material to form bonding pad 123 embedded in bonding layer 121.

[0083] exist Figure 2 The cutting process is as shown in the previous figure. Figure 1 The cutting process is performed along the cutting paths 129 in the semiconductor die 150. The cutting process singulates the semiconductor dies 150 from one another along the cutting paths 129. The cutting paths 129 are disposed between adjacent semiconductor dies 150. The cutting process may include, for example, a blade cutting process that uses an abrasive disk or blade saw rotating at a high speed to cut along the cutting paths 129. The blade tip may include abrasive or a thin diamond layer.

[0084] exist Figure 3 1 , a semiconductor wafer 20 is bonded to a semiconductor die 150. Wafer 20 may also be referred to as the bottom die. The materials and formation processes of features in wafer 20 can be found by referring to similar features in wafer 10, where similar features in wafer 10 begin with the number "1" and these features correspond to features in wafer 20 and have reference numbers beginning with the number "2." For example, wafer 20 may include a substrate 217 and an interconnect structure 219, the substrate 217 having devices (e.g., transistors, capacitors, diodes, resistors, or the like) formed thereon. The interconnect structure 219 electrically connects the devices on the substrate 217 to form one or more integrated circuits. The interconnect structure 219 includes one or more dielectric layers (e.g., one or more interlayer dielectric (ILD) layers, intermetal dielectric (IMD) layers, or the like) and interconnect wires or metallization patterns embedded in the one or more dielectric layers.

[0085] A bonding layer 221 is disposed on the interconnect structure 219, and a bonding pad 223 is disposed in the bonding layer 221. The bonding pad 223 allows for connection between the interconnect structure 219 and devices on the substrate 217. Wafer 20 further includes through substrate vias (TSVs) 211, which can be electrically coupled to metallization patterns in the interconnect structure 219. The TSVs 211 can be formed by forming recesses in the substrate 217, for example, by etching, grinding, laser technology, combinations thereof, and / or the like. A thin barrier layer can be deposited in parallel over the front side of the substrate 217 and in the openings, such as by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), thermal oxidation, combinations thereof, and / or the like. The barrier layer may comprise a nitride or an oxynitride, such as titanium nitride, titanium oxynitride, tantalum nitride, tantalum oxynitride, tungsten nitride, combinations thereof, and / or the like. A conductive material is deposited over the thin barrier layer and in the opening. The conductive material may be formed by an electrochemical plating process, CVD, ALD, PVD, combinations thereof, and / or the like. Examples of conductive materials are copper, tungsten, aluminum, silver, gold, combinations thereof, and / or the like. Additional conductive material and the barrier layer may be removed from the front side of the substrate 217 by, for example, chemical mechanical polishing. Thus, in some embodiments, the through substrate via 211 may comprise a conductive material and a thin barrier layer between the conductive material and the substrate 217. In a subsequent processing step, the substrate 217 may be thinned to expose the through substrate via 211 (see Figure 10 After thinning, the through-substrate vias 211 provide electrical connections from the back side of the substrate 217 to the front side of the substrate 217. In various embodiments, the back side of the substrate 217 may refer to the side of the substrate 217 opposite the device and interconnect structures 219, and the front side of the substrate 217 may refer to the side of the substrate 217 where the device and interconnect structures 219 are disposed.

[0086] Still see Figure 3Semiconductor die 150 is bonded to wafer 20, for example, in a hybrid bonding configuration. Semiconductor die 150 is positioned face-down, with the front side of semiconductor die 150 facing wafer 20 and the back side of semiconductor die 150 facing away from wafer 20. Semiconductor die 150 is bonded to bonding layer 221 on the front side of wafer 20 and to bonding pads 223 in bonding layer 221. For example, bonding layer 121 of semiconductor die 150 may be directly bonded to bonding layer 221 of wafer 20, and bonding pads 123 of semiconductor die 150 may be directly bonded to bonding pads 223 of wafer 20. In one embodiment, the bond between bonding layer 121 and bonding layer 221 may be an oxygen-oxygen bond or the like. The hybrid bonding process further directly bonds bonding pads 123 of semiconductor die 150 to bonding pads 223 of wafer 20 via direct metal-to-metal bonding. Therefore, the electrical connection between the semiconductor die 150 and the wafer 20 is provided by the physical connection from the bonding pad 123 to the bonding pad 223 .

[0087] As an example, the hybrid bonding process begins by aligning the semiconductor die 150 with the wafer 20, for example, by applying a surface treatment to one or more of the bonding layer 121 or the bonding layer 221. The surface treatment may include a plasma treatment. The plasma treatment may be performed in a vacuum environment. After the plasma treatment, the surface treatment may further include a cleaning process (e.g., by rinsing with deionized water or the like), which may be applied to one or more of the bonding layer 121 or the bonding layer 221. The hybrid bonding process may then proceed to aligning the bonding pad 123 with the bonding pad 223. Next, the hybrid bonding includes a pre-bonding step during which the semiconductor die 150 is brought into contact with the wafer 20. The pre-bonding may be performed at room temperature (e.g., between about 21° C. and about 25° C.). The hybrid bonding process continues with an annealing step at a temperature between about 150° C. and about 400° C. for a duration between about 0.5 hours and about 3 hours, causing the metal (e.g., copper) in bonding pad 123 and the metal (e.g., copper) of bonding pad 223 to diffuse into each other, thereby forming a direct metal-to-metal bond. Although two semiconductor dies 150 are shown bonded to wafer 20, other embodiments may include any number of semiconductor dies 150 bonded to wafer 20.

[0088] exist Figure 4In the embodiment of the present invention, encapsulant 132 is formed over wafer 20 and semiconductor die 150 to encapsulate each of semiconductor die 150. Encapsulant 132 can be formed using compression molding, transfer molding, spin coating, or the like. Encapsulant 132 can be an epoxy resin or a molding compound resin such as polyimide, polyphenylene sulfide (PPS), polyetheretherketone (PEEK), polyethersulfone (PES), a heat-resistant crystalline resin, a combination thereof, or the like.

[0089] After forming the encapsulant 132, a planarization process is performed to remove excess portions of the encapsulant 132 and expose the top surface of the semiconductor die 150. The planarization process may include a grinding process, a CMP process, or the like. Figure 4 As shown in , the planarization process may cause the top surface of the semiconductor die 150 to be flush with the top surface of the encapsulant 132 .

[0090] Figures 5 to 7 The stress buffer structure 133 is shown in FIG. Figure 7 ) is formed on the top surface of the semiconductor die 150 and the top surface of the encapsulant 132. The stress buffer structure 133 may include one or more insulating layers and corresponding vias within the insulating layers. Each insulating layer and its corresponding via disposed within the insulating layer may be collectively referred to as a stress buffer layer.

[0091] exist Figure 5In the embodiment of the present invention, a bottom stress buffer layer 133a of the stress buffer structure 133 is formed above the top surface of the semiconductor die 150 and the top surface of the encapsulant 132. The bottom stress buffer layer 133a includes an insulating layer 134 and a bottom via 136 extending through the insulating layer 134. The bottom via 136 is formed above the top surface of the semiconductor die 150 and, if desired, may also be formed above the top surface of the encapsulant 132 by initially forming a first seed layer (not shown) of one or more thin layers of conductive material. This conductive material facilitates the formation of thicker layers during subsequent processing steps. The first seed layer is formed above the top surface of the semiconductor die 150 and the top surface of the encapsulant 132. The first seed layer may include a layer of copper, titanium, or the like formed using a process such as sputtering, evaporation, PECVD, or the like. A photoresist (also not shown) may then be formed and patterned using, for example, a spin coating technique to cover the first seed layer. Once the photoresist has been formed and patterned, a conductive material may be formed in the openings in the patterned photoresist on the first seed layer. The conductive material may be a material such as copper or the like. The conductive material may be formed by a deposition process such as electroplating, electroless plating, or the like. Once the conductive material has been formed, the photoresist may be removed by a suitable removal process such as ashing or chemical stripping. Additionally, after removing the photoresist, those portions of the first seed layer covered by the photoresist may be removed by, for example, a suitable wet etching process or dry etching process, which may use the conductive material as an etch mask. The remaining portions of the first seed layer and the conductive material form bottom vias 136. In some embodiments, the diameter D1 of each bottom via 136 may be in the range of 8 μm to 20 μm.

[0092] After forming the bottom via 136, an insulating layer 134 is formed over the bottom via 136, the top surface of the semiconductor die 150, and the top surface of the encapsulant 132. The insulating layer 134 may include one or more dielectric materials such as a low-temperature polyimide (LTPI) material or the like. The insulating layer 134 may be formed by a process such as coating (e.g., spin coating) or the like. After forming the insulating layer 134, the excess portion of the insulating layer 134 may be planarized using a grinding process, a CMP process, or the like to remove a portion of the insulating layer 134 and expose the top surface of the bottom via 136. The bottom stress buffer layer 133a is thus formed by exposing the bottom via 136 and the insulating layer 134. Figure 5 As shown in FIG, the planarization may cause the top surface of the bottom via 136 to be flush with the top surface of the insulating layer 134. In one embodiment, the bottom stress buffer layer 133a may have a thickness T1 of up to 10 μm.

[0093] exist Figure 6In the embodiment of the present invention, the middle stress buffer layer 133b of the stress buffer structure 133 is formed above the bottom stress buffer layer 133a. The middle stress buffer layer 133b may include an insulating layer 138 and a middle through hole 140 extending through the insulating layer 138. The middle stress buffer layer 133b may be formed using materials and processes similar to those used in the previous embodiment of the present invention. Figure 5 The insulating layer 138 may be formed using materials and processes similar to those described above for forming the bottom through hole 136. Figure 5 The insulating layer 134 is formed using the materials and processes described above for forming the insulating layer 134. As an example, to form the intermediate vias 140, a photoresist is placed and patterned on top of the bottom stress buffer layer 133a with the desired pattern of the intermediate vias 140. The patterned openings of the photoresist are positioned above a corresponding one of the bottom vias 136, such that each opening exposes the top surface of the corresponding bottom via 136. A conductive material (e.g., copper or the like) is then formed in the patterned openings of the photoresist using, for example, a plating process or the like. Note that forming a second seed layer before forming the conductive layer is optional because the bottom vias may include copper, which facilitates the plating process used to form the conductive material. The photoresist can then be removed using a suitable removal process such as ashing or chemical stripping. The remaining portions of the conductive material form the intermediate vias 140. In this way, each of the intermediate vias 140 overlaps and physically contacts the corresponding bottom via 136. In one embodiment, the diameter D2 of each intermediate through hole 140 may be in a range of 5 μm to 15 μm. In one embodiment, the diameter D2 is smaller than the diameter D1. In one embodiment, the diameter D2 of each intermediate through hole 140 may decrease in the vertical direction (e.g., each intermediate through hole 140 may have a tapered shape), thereby moving from the top surface of the intermediate through hole 140 to the bottom surface of the intermediate through hole 140.

[0094] After forming the middle via 140, an insulating layer 138 is formed over the middle via 140 and the bottom stress buffer layer 133a, such as over the bottom via 136 and the insulating layer 134. The insulating layer 138 is formed using a similar method as previously described. Figure 5 After forming the insulating layer 138, the excess portion of the insulating layer 138 may be planarized using a grinding process, a CMP process, or the like to remove a portion of the insulating layer 138 and expose the top surface of the middle via 140. The middle stress buffer layer 133b is thus formed by exposing the middle via 140 and the insulating layer 138. Figure 6 As shown in FIG, the planarization process may cause the top surface of the middle via 140 to be flush with the top surface of the insulating layer 138. In one embodiment, the middle stress buffer layer 133b may have a thickness T2 of up to 20 μm.

[0095] although Figure 6 Although only one intermediate stress buffer layer 133b is shown above the bottom stress buffer layer 133a, any number of intermediate stress buffer layers 133b may be formed, including one or more additional insulating layers and corresponding intermediate vias extending through the one or more additional insulating layers. The insulating layer and the intermediate via may be formed using processes and materials similar to those used to form the insulating layer 138 and the intermediate via 140, respectively. The steps described above may be repeated until a desired number of intermediate stress buffer layers 133b are formed.

[0096] exist Figure 7 In FIG. 1 , the top stress buffer layer 133c of the stress buffer structure 133 is formed above the middle stress buffer layer 133b. The top stress buffer layer 133c may include an insulating layer 142 and a top through hole 144 extending through the insulating layer 142. The top stress buffer layer 133c may be formed using materials and processes similar to those used in the bottom stress buffer layer 133a and the middle stress buffer layer 133b. For example, the top through hole 144 may be formed using materials similar to those used in the previous embodiment. Figure 5 and Figure 6 The materials and processes described for forming the bottom via 136 and the middle via 140 are formed, and the insulating layer 142 can be formed using materials similar to those previously described in Figure 5 and Figure 6 As an example, to form the top via 144, a third seed layer is formed over the middle stress buffer layer 133b, such as over the top surface of the middle via 140 and the insulating layer 138. The third seed layer is formed using materials similar to those previously described in Figure 5 144 . A photoresist is placed and patterned on top of the third seed layer in the desired pattern for the top vias 144. A conductive material (e.g., copper or the like) is then formed in the patterned openings of the photoresist using, for example, a plating process or the like. The photoresist may then be removed using a suitable removal process such as ashing or chemical stripping. Furthermore, after removing the photoresist, those portions of the third seed layer covered by the photoresist may be removed using, for example, a suitable wet or dry etching process, which may use the conductive material as an etch mask. The remaining portions of the third seed layer and the conductive material form the top vias 144. In some embodiments, the diameter D3 of each top via 144 may be in the range of 8 μm to 20 μm. Diameter D3 may be greater than diameter D2. In some embodiments, diameter D3 may be equal to or different from diameter D1.

[0097] A portion of each top via 144 is positioned so as to overlap and physically contact the corresponding middle via 140 below the portion, and the corresponding middle via 140 is positioned so as to overlap and physically contact the corresponding bottom via 136 below the corresponding middle via 140. In this manner, each top via 144, the corresponding middle via 140 positioned below and physically contacting the top via 144, and the corresponding bottom via 136 positioned below and physically contacting the middle via 140 form a combined via 145. Combined via 145 may also be referred to as a stress buffering via. In addition, a portion of each top via 144 also overlaps with insulating layer 138. In an embodiment, a vertical line AA passes through the center of the combination via 145 , wherein line AA passes through the center of the corresponding top via 144 , the center of the corresponding middle via 140 , and the center of the corresponding bottom via 136 of the combination via 145 .

[0098] After forming the top through hole 144, an insulating layer 142 is formed over the top through hole 144 and the middle stress buffer layer 133b. The insulating layer 142 is formed using a similar method as previously described. Figure 5 and Figure 6 The insulating layer 134 and the insulating layer 138 are formed using the materials and processes described in the foregoing. After forming the insulating layer 142, the excess portion of the insulating layer 142 may be planarized using a grinding process, a CMP process, or the like to remove a portion of the insulating layer 142 and expose the top surface of the top via 144. The top stress buffer layer 133c is thus formed by exposing the top via 144 and the insulating layer 142. Figure 7 As shown in FIG, the planarization process may cause the top surface of the top via 144 to be flush with the top surface of the insulating layer 142. In one embodiment, the top stress buffer layer 133c may have a thickness T3 of up to 10 μm. After forming the top stress buffer layer 133c, the stress buffer structure 133 may have a total thickness T4 of up to 100 μm.

[0099] although Figure 7While only one intermediate stress buffer layer 133b is shown above the bottom stress buffer layer 133a, and one top stress buffer layer 133c is shown above the intermediate stress buffer layer 133b, any number of intermediate stress buffer layers 133b may be formed, including one or more additional first insulating layers and corresponding intermediate vias extending through the one or more additional first insulating layers, and any number of top stress buffer layers 133c may be formed, including one or more additional second insulating layers and corresponding top vias extending through the one or more additional second insulating layers. The first insulating layer and the intermediate vias may be formed using processes and materials similar to those used to form the insulating layer 138 and the intermediate vias 140, respectively. The second insulating layer and the top vias may be formed using processes and materials similar to those used to form the insulating layer 142 and the top vias 144, respectively. The steps described above may be repeated until a desired number of intermediate stress buffer layers 133b and top stress buffer layers 133c are formed. For example, in one embodiment, the total number of layers of the stress buffer structure 133 (eg, including the bottom stress buffer layer 133 a , the middle stress buffer layer 133 b , and the top stress buffer layer 133 c ) may be in the range of 3 to 15.

[0100] Combination vias 145 (e.g., each combination via 145 including a top via 144, a corresponding middle via 140, and a corresponding bottom via 136) extend through the stress buffering structure 133. A first plurality of the combination vias 145 may be disposed above and in physical contact with the semiconductor die 150, and, optionally, a second plurality of the combination vias 145 may be disposed above and in physical contact with the encapsulant 132. For example, the combination vias 145 may be in physical contact with a silicon surface (e.g., of the substrate 117) of the semiconductor die 150. The combination vias 145 allow heat generated from the semiconductor die 150 to travel through the combination vias 145 away from the semiconductor die 150 and the surrounding encapsulant 132, and to a metal heat sink 154 (shown later in FIG. 1 ) where the heat can be dissipated. Figure 9 In this manner, the combined vias 145 are thermally coupled to the semiconductor die 150, thereby acting as an effective heat pipe and facilitating heat transfer away from the semiconductor die 150 and directing the heat to the metal heat sink 154 for efficient dissipation.

[0101] After forming the stress buffer structure 133, the percentage of the total volume of the combined via 145 (e.g., including a material such as copper) to the total volume of the stress buffer structure 133 (e.g., including the combined via 145 and the insulating layers 134, 138, and 142) is in the range of 10% to 30%.

[0102] Advantages can be achieved by forming the stress buffer structure 133 above the semiconductor die 150 and the encapsulant 132 so that the stress buffer structure 133 is disposed between the semiconductor die 150 and the encapsulant 132 and then attaching the metal heat sink 154 (shown in FIG. Figure 9 ). The stress buffer structure 133 has a total thickness T4 that can be up to 100 μm and includes up to 15 insulating layers (e.g., insulating layer 134, insulating layer 138, and insulating layer 142) and a combined via 145 extending through the insulating layers (e.g., insulating layer 134, insulating layer 138, and insulating layer 142). The combined via 145 includes copper, and the insulating layers (e.g., insulating layer 134, insulating layer 138, and insulating layer 142) include a low-temperature polyimide (LTPI) material. Such advantages include a reduction in mechanical stress due to the mismatch in thermal expansion coefficients between the first material (e.g., copper) of the metal heat sink 154 and the second material (e.g., silicon) of the semiconductor die 150. The stress buffer structure 133 acts as an intermediate interface, absorbing or relaxing the mechanical stress caused by the mismatch in thermal expansion coefficients between the first material and the second material. This reduces the risk of cracking at the interface between the semiconductor die 150 and the metal heat sink 154, and reduces the risk of possible delamination between the metal heat sink 154 and the semiconductor die 150. Furthermore, the metal heat sink 154 and the stress buffering structure 133 allow for improved and more efficient heat dissipation from the integrated chip package 100, resulting in improvements in device reliability and device performance.

[0103] Additional advantages can be achieved by forming the stress buffering structure 133 such that the percentage of the total volume of copper in the composite vias 145 to the total volume of the stress buffering structure 133 is within a range of 10% to 30%. For example, if the percentage of the total volume of copper in the composite vias 145 to the total volume of the stress buffering structure 133 is less than 10%, there will be insufficient heat conduit to facilitate heat transfer away from the semiconductor die 150 and to direct the heat to the metal heat sink 154. This will result in insufficient heat dissipation from the integrated chip package 100. Furthermore, if the percentage of the total volume of copper in the composite vias 145 to the total volume of the stress buffering structure 133 is greater than 30%, there will be unacceptably high mechanical stress due to the mismatch in the thermal expansion coefficients of the copper in the composite vias 145 and the second material (e.g., silicon) of the semiconductor die 150. This would therefore mean an increased risk of cracking at the interface between the semiconductor die 150 and the stress buffering structure 133 and an increased risk of delamination between the stress buffering structure 133 and the semiconductor die 150 .

[0104] Other advantages can be achieved by forming the stress buffer structure 133 with a total thickness T4 of up to 100 μm, wherein the top via 144 has a diameter D3 in the range of 8 μm to 20 μm, wherein the middle via 140 has a diameter D2 in the range of 5 μm to 15 μm, and wherein the bottom via 136 has a diameter D1 in the range of 8 μm to 20 μm. These advantages include facilitating and making it easier to form the stress buffer structure 133 while maintaining (e.g., by varying the total thickness T4 and the diameters D1, D2, and D3 within the aforementioned size range parameters) a desired percentage of the total volume of copper of the combined via 145 to the total volume of the stress buffer structure 133, wherein the percentage is in the range of from 10% to 30%.

[0105] Even more advantages can be achieved by forming stress buffering structure 133 with top via 144 having a diameter D3 ranging from 8 μm to 20 μm, intermediate vias 140 having a diameter D2 ranging from 5 μm to 15 μm, and bottom via 136 having a diameter D1 ranging from 8 μm to 20 μm. Diameters D1 and D3 are greater than diameter D2, and diameter D2 of each intermediate via 140 decreases vertically (e.g., each intermediate via 140 may have a tapered shape), moving from the top surface of stress buffering structure 133 toward the bottom surface of stress buffering structure 133. Due to the transition of combined vias 145 from one diameter to another, these advantages include more efficient distribution and dissipation of mechanical stress (e.g., resulting from a mismatch in the thermal expansion coefficients of the first material (e.g., copper) of metal heat sink 154 and the second material (e.g., silicon) of semiconductor die 150) along the height of stress buffering structure 133. Furthermore, due to the tapered effect of the intermediate via 140, stress is more smoothly distributed along the height of the stress buffering structure 133. This reduces potential areas of stress concentration within the stress buffering structure 133 and reduces the risk of cracking at the interface between the semiconductor die 150 and the stress buffering structure 133. Consequently, the risk of delamination between the stress buffering structure 133 and the semiconductor die 150 is reduced.

[0106] exist Figure 8 In the embodiment of the present invention, a metal layer 146 is formed over the stress buffer structure 133, such as over the top via 144 of the insulating layer 142 and the top stress buffer layer 133c. The metal layer 146 may include a layer of copper, titanium, or the like formed using a process such as sputtering, evaporation, CVD, PECVD, or the like.

[0107] Advantages can be achieved by forming the metal layer 146 above the stress buffer structure 133. These advantages include the metal layer 146 acting as a highly conductive path for heat transfer, thereby allowing heat to flow from the underlying stress buffer structure 133 to a subsequently attached metal heat sink 154 (shown in FIG. Figure 9 This prevents localized hot spots from forming above the modular vias 145 and allows for improved and more efficient heat dissipation from the integrated chip package 100 via the metal heat sink 154, resulting in improved device reliability and device performance.

[0108] exist Figure 9 In the embodiment of the present invention, thermal interface material (TIM) 148 is applied to the top surface of metal layer 146. TIM 148 is formed from a thermally conductive material. Acceptable thermally conductive materials include thermal paste; phase change material; metal-filled polymer matrix; solder alloys of lead, tin, indium, silver, copper, bismuth, and the like (such as indium or lead / tin alloy); or the like. If TIM 148 is a solid material, TIM 148 can be heated to a temperature at which TIM 148 undergoes a solid-to-liquid transition and then applied to the top surface of metal layer 146 in liquid form.

[0109] After applying thermal interface material 148 to the top surface of metal layer 146, metal heat sink 154 is then coupled to the top surface of metal layer 146. Metal heat sink 154 is placed on the top surface of metal layer 146 using, for example, a pick-and-place process. Metal heat sink 154 is in contact with the top surface of metal layer 146 via thermal interface material 148. Metal heat sink 154 may comprise a metal such as copper or the like. Metal heat sink 154 may also be subsequently referred to as a copper lid. In one embodiment, the height H1 of metal heat sink 154 may be up to 5 mm.

[0110] In one embodiment, the metal heat sink 154 may include a metal layer 152 disposed above a first surface of the metal heat sink 154. The metal layer 152 may include a material different from that of the metal heat sink 154. For example, the metal layer 152 may include titanium or the like formed by sputtering, evaporation, CVD, PECVD, or the like. In this embodiment, when the metal heat sink 154 is coupled to the top surface of the metal layer 146, the first surface of the metal heat sink 154 faces the top surface of the metal layer 146, such that the metal layer 152 is disposed between the metal layer 146 and the metal heat sink 154.

[0111] Advantages can be achieved by forming a stress buffering structure 133 above and in physical contact with the semiconductor die 150 and the encapsulant 132. The stress buffering structure 133 can include 3 to 15 insulating layers (e.g., insulating layer 134, insulating layer 138, and insulating layer 142) and a composite via 145 extending through the insulating layers (e.g., insulating layer 134, insulating layer 138, and insulating layer 142). The composite via 145 includes copper, and the insulating layers (e.g., insulating layer 134, insulating layer 138, and insulating layer 142) include a low-temperature polyimide (LTPI) material, wherein the percentage of the total volume of the copper of the composite via 145 to the total volume of the stress buffering structure 133 is in a range of 10% to 30%. A metal layer 146 is formed over the stress buffering structure 133, and a metal heat sink 154 is then coupled to and in contact with the metal layer 146 via a thermal interface material 148. Advantages include reduced mechanical stress due to the mismatch in thermal expansion coefficients between the first material (e.g., copper) of the metal heat sink 154 and the second material (e.g., silicon) of the semiconductor die 150. The stress buffering structure 133 acts as an intermediate interface, absorbing or relaxing mechanical stress caused by the mismatch in thermal expansion coefficients between the first and second materials. This reduces the risk of cracking at the interface between the semiconductor die 150 and the metal heat sink 154 and mitigates the risk of possible delamination between the metal heat sink 154 and the semiconductor die 150. Furthermore, the metal heat sink 154 and stress buffering structure 133 allow for improved and more efficient heat dissipation from the integrated wafer package 100, resulting in improved device reliability and device performance.

[0112] exist Figure 10 In the embodiment, a thinning process of the back side of the substrate 217 is performed to expose the through-substrate via 211. The thinning process of the back side of the substrate 217 can be performed by a planarization process such as CMP, grinding, or etching. The thinning process can cause the surface of the through-substrate via 211 to be flush with the surface of the back side of the substrate 217.

[0113] exist Figure 11In the embodiment, dielectric layer 234 is formed on the backside of substrate 217 and on the exposed surface of through-substrate via 211. Dielectric layer 234 may include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, a low-K dielectric material such as phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), SiOxCy, spin-on glass, spin-on polymer, silicon-carbon material, compounds thereof, composites thereof, or combinations thereof. Dielectric layer 234 may be deposited by any suitable method, such as CVD, PECVD, spin coating, or the like.

[0114] The metallization pattern 236 can be formed in the dielectric layer 234, for example, by using photolithography techniques to deposit a photoresist material on the dielectric layer 234 and pattern the photoresist material, thereby exposing portions of the dielectric layer 234 that will become the metallization pattern 236. An etching process, such as an anisotropic dry etching process, can be used to create openings in the dielectric layer 234 that correspond to the exposed portions of the dielectric layer 234. The openings in the dielectric layer 234 can expose the through-substrate vias 211. A seed layer (not shown separately) is formed over the exposed surface of the dielectric layer 234 and in the openings in the dielectric layer 234. In some embodiments, the seed layer is a metal layer that can be a single layer or a composite layer including multiple sublayers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer can be formed using, for example, PVD or the like. A photoresist is then formed over the seed layer and patterned. The photoresist can be formed by spin coating or the like and can be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern 236. The patterning forms an opening through which the photoresist exposes the seed layer. A conductive material is then formed in the opening and on the exposed portion of the seed layer. The conductive material can be formed by plating, such as electroplating, electroless plating, or the like. The conductive material can include a metal, such as copper, titanium, tungsten, aluminum, or the like. Then, portions of the seed layer on which the photoresist and the conductive material are not formed are removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma or the like. Once the photoresist is removed, the exposed portion of the seed layer is removed, such as using an acceptable etching process. The remaining portions of the seed layer and the conductive material in the dielectric layer 234 form the metallization pattern 236. These metallization patterns 236 will be used to electrically connect the substrate through-holes 211 to external devices. In some embodiments, the metallization pattern 236 may also include under bump metallization (UBM).

[0115] Figure 12A The formation of the conductive connector 238 on the metallization pattern 236 is shown. Figure 12B The integrated wafer package 100 is shown along the Figure 12A A top-down view of line XX in . Figure 12A , a conductive connector 238 is formed such that the conductive connector 238 is disposed on the metallization pattern 236 and electrically coupled to the semiconductor die 150 via the through-substrate via 211. The conductive connector 238 may include a controlled collapse chip connection (C4) bump, a ball grid array (BGA) connector, a solder ball, or the like. The conductive connector 238 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the conductive connector 238 is formed by initially forming a solder layer by evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once the solder layer has been formed on the structure, reflow may be performed to shape the material into the desired bump shape.

[0116] The conductive connector 238 is used to connect the integrated chip package 100 to an additional electrical component, which may be a semiconductor substrate, a packaging substrate, a printed circuit board (PCB), or the like (see Figure 14 ).

[0117] exist Figure 12B In the top-down view, the Figure 12A XX in FIG. 1 is shown, where the line XX passes through the center of the middle stress buffer layer 133 b of the stress buffer structure 133 . Figure 12B Thus, the insulating layer 138 of the stress buffering structure 133 and the corresponding intermediate via 140 of the combined via 145 extending through the stress buffering structure 133 are illustrated. Figure 12B As shown, the modular vias 145 are uniformly arranged or stacked within the stress buffering structure 133, such that the modular vias 145 have a uniform density (e.g., a uniform number of modular vias 145 per unit area) across the stress buffering structure 133 and above the semiconductor die 150 and the encapsulant 132. For example, a spacing S1 defines the distance between adjacent modular vias 145 in a first direction (e.g., direction x), and a spacing S2 defines the distance between adjacent modular vias 145 in a second direction (e.g., direction y), where the first direction (e.g., direction x) is orthogonal to the second direction (e.g., direction y). The spacing S1 can be equal to the spacing S2. Furthermore, each modular via 145 has a central via 140 having a diameter (e.g., diameter D2) that is equal to the diameter of the central vias 140 of the other modular vias 145.

[0118] Figure 13A and Figure 13B Unless otherwise specified, like reference numerals in this embodiment (and subsequently discussed embodiments) represent components formed by similar processes. Figures 1 to 12B Therefore, the process steps and applicable materials may not be repeated herein.

[0119] Figure 13A The formation of the conductive connector 238 on the metallization pattern 236 is shown. Figure 13B The integrated wafer package 100 is shown along the Figure 13A A top-down view of line XX in . Figure 13A In the embodiment, the conductive connector 238 is used in the same manner as previously described. Figure 12A The invention can be formed by processes and materials similar to those described in . Figure 13A Also shown are hot spots 156 , which are located in localized areas of the semiconductor die 150 and wafer 20 that experience significantly higher temperatures than surrounding areas during operation of the integrated chip package 100 .

[0120] exist Figure 13B From top to bottom, the diagram is shown in Figure 13A , where the line YY passes through the center of the middle stress buffer layer 133 b of the stress buffer structure 133 . Figure 13B Thus, the insulating layer 138 of the stress buffering structure 133 and the corresponding intermediate via 140 of the combined via 145 extending through the stress buffering structure 133 are illustrated. Figure 13B Further illustrated are the first regions 157 and the second regions 158 within the first regions 157, wherein each second region 158 is surrounded by the first region 157. Each second region 158 is a region of the stress buffer structure 133 that is adjacent to one or more hot spots 156 (previously illustrated in FIG. Figure 13A In the first region 157, the combination vias 145 are uniformly arranged or stacked within the stress buffering structure 133, such that the combination vias 145 have a uniform first density (e.g., a uniform number of combination vias 145 per unit area) across the first region 157. For example, in the first region 157, a spacing S3 defines the distance between adjacent combination vias 145 in a first direction (e.g., direction x), and a spacing S4 defines the distance between adjacent combination vias 145 in a second direction (e.g., direction y), where the first direction (e.g., direction x) is orthogonal to the second direction (e.g., direction y). The spacing S3 may be equal to the spacing S4. Furthermore, in the first region 157, each combination via 145 has a central through-hole 140 having a diameter (e.g., diameter D2) that is equal to the diameter of the central through-holes 140 of the other combination vias 145 in the first region 157.

[0121] In the second region 158, the modular vias 145 are uniformly arranged or stacked within the stress buffering structure 133, such that the modular vias 145 have a uniform second density (e.g., a uniform number of modular vias 145 per unit area) across the second region 158. In one embodiment, the second density of modular vias 145 in the second region 158 is greater than the first density of modular vias 145 in the first region 157. For example, in the second region 158, a spacing S5 defines the distance between adjacent modular vias 145 in a first direction (e.g., direction x), and a spacing S6 defines the distance between adjacent modular vias 145 in a second direction (e.g., direction y), where the first direction (e.g., direction x) is orthogonal to the second direction (e.g., direction y). The spacing S5 may be equal to the spacing S6, and both spacings S5 and S6 may be smaller than spacings S3 and S4. Furthermore, in the second region 158, each modular through-hole 145 has a central through-hole 140 having a diameter (eg, diameter D4) equal to the diameters of the central through-holes 140 of the other modular through-holes 145 in the second region 158. In one embodiment, diameter D4 is smaller than diameter D2.

[0122] In one embodiment, the density of the combination vias 145 in each second region 158 is different from the density of the combination vias 145 in each of the other second regions 158 and the first region 157 .

[0123] Advantages can be achieved by forming a stress buffering structure 133 above and in physical contact with the semiconductor die 150 and the encapsulant 132, wherein the stress buffering structure 133 includes a first region 157 and a second region 158, and wherein each second region 158 overlaps one or more hot spots 156 in the wafer 20 and / or the semiconductor die 150. Each second region 158 is surrounded by the first region 157. In the first region 157, the combination vias 145 have a uniform first density (e.g., a uniform number of combination vias 145 per unit area) across the first region 157 and in the second region 158, and have a uniform second density (e.g., a uniform number of combination vias 145 per unit area) across the second region 158, wherein the second density is greater than the first density. These advantages include an increased number of combined vias 145 per unit area in the second region 158, thereby creating an increased number of thermal conduction paths for the additional heat generated in each hotspot 156 to spread through the stress buffering structure 133 and onto the metal heat sink 154. This results in faster and more efficient removal of heat from the hotspots 156 and the integrated chip package 100, resulting in improved device reliability and device performance.

[0124] exist Figure 14, a packaging substrate 240 is coupled to the integrated wafer package 100. The packaging substrate 240 may include an interposer, a package, a core substrate, a coreless substrate, a printed circuit board (PCB), or the like. In one embodiment, the packaging substrate 240 includes a substrate core 260 and a bonding pad 246 above the substrate core 260. The substrate core 260 may be made of a semiconductor material such as silicon, germanium, diamond, or the like. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, combinations of these materials, and the like may also be used. In addition, the substrate core 260 may be an SOI substrate. Generally, an SOI substrate includes layers of semiconductor materials such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or combinations thereof. In an alternative embodiment, the substrate core 260 is based on an insulating core, such as a fiberglass-reinforced resin core. An example core material is a fiberglass resin such as FR4. Alternative core materials include bismaleimide-triazine BT resin or alternatively other PCB materials or films.Build-up films such as ABF or other laminates can be used for substrate core 260.

[0125] The substrate core 260 may include active and passive devices (not shown). A wide variety of devices, such as transistors, capacitors, resistors, combinations thereof, and the like, may be used to create the structural and functional requirements of the device stack design. The devices may be formed using any suitable method.

[0126] The substrate core 260 may also include metallization layers and vias (not shown), with the bonding pads 246 physically and / or electrically coupled to the metallization layers and vias. The metallization layers may be formed over the active and passive devices and are designed to connect the various devices to form functional circuits. The metallization layers may be formed from alternating layers of dielectric material (e.g., low-k dielectric material) and conductive material (e.g., copper) with vias connecting the conductive material layers, and may be formed by any suitable process, such as deposition, damascene, dual damascene, or the like. In some embodiments, the substrate core 260 is substantially free of active and passive devices.

[0127] In some embodiments, the conductive connectors 238 are reflowed to attach the integrated chip package 100 to the bonding pads 246. The conductive connectors 238 electrically and / or physically couple the package substrate 240, including the metallization layer in the substrate core 260, to the integrated chip package 100. In some embodiments, a solder resist 248 is formed on the substrate core 260. The conductive connectors 238 can be disposed in openings in the solder resist 248 to electrically and mechanically couple to the bonding pads 246. The solder resist 248 can be used to protect areas of the substrate core 260 from external damage.

[0128] Before the conductive connector 238 is reflowed by at least some of the epoxy portion of the epoxy flux remaining after the integrated wafer package 100 is attached to the packaging substrate 240, the conductive connector 238 may have epoxy flux (not shown) formed on the conductive connector 238. This remaining epoxy portion may act as an underfill to reduce stress and protect the joint created by the reflow of the conductive connector 238. In some embodiments, an underfill 250 may be formed between the integrated wafer package 100 and the packaging substrate 240 and surrounding the conductive connector 238. The underfill 250 may be formed by a capillary flow process after the integrated wafer package 100 is coupled to the packaging substrate 240, or by a suitable deposition method before the packaging substrate 240 is coupled to the integrated wafer package 100.

[0129] In one embodiment, the package substrate 240 may include bonding pads 252 above the substrate core 260. Conductive connectors 254 may be coupled to the bonding pads 252 to allow electrical coupling of the package substrate 240 to an external circuit or device. The conductive connectors 254 may be ball grid array (BGA) connectors, solder balls, metal posts, controlled collapse chip connection (C4) bumps, microbumps, bumps formed using electroless nickel-electroless palladium-immersion gold (ENEPIG) technology, or the like. The conductive connectors 254 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, a solder resist 248 is formed on the substrate core 260, and the conductive connectors 254 may be disposed in openings in the solder resist 248 to electrically and mechanically couple to the bonding pads 252. The solder resist 248 may be used to protect areas of the substrate core 260 from external damage.

[0130] In some embodiments, a passive device (e.g., a surface mount device (SMD) (not shown)) can also be attached to the package substrate 240 (e.g., to the bonding pads 246). For example, the passive device can be bonded to the same surface of the package substrate 240 as the conductive connector 238.

[0131] Embodiments of the present disclosure have several advantageous features. Embodiments include a method of forming an integrated chip package. Forming the integrated chip package includes bonding two or more semiconductor dies (e.g., a top die) to a semiconductor wafer (e.g., a bottom die). A stress buffer structure is formed over and in physical contact with the two or more semiconductor dies (e.g., the top die). The stress buffer structure includes one or more insulating layers having a plurality of copper vias extending through the one or more insulating layers, wherein a total volume of the copper vias relative to a total volume of the stress buffer structure is in a range of 10% to 30%. A metal layer is formed over the stress buffer structure, and a thermal interface material (TIM) is applied to a top surface of the metal layer. A metal heat sink (e.g., a copper lid) is then placed over the integrated chip package, and the metal heat sink is in contact with the metal layer via the TIM. Thus, mechanical stress due to the mismatch in thermal expansion coefficients between the first material (e.g., copper) of the metal heat sink and the second material (e.g., silicon) of the two or more semiconductor dies (e.g., the top die) is reduced. The stress buffering structure acts as an intermediate interface, absorbing or relaxing the mechanical stress caused by the mismatch in thermal expansion coefficients between the first and second materials. This reduces the risk of cracking at the interface between the two or more semiconductor dies (e.g., the top die) and the metal heat sink, and reduces the risk of delamination between the metal heat sink and the two or more semiconductor dies (e.g., the top die). Furthermore, the metal heat sink and stress buffering structure allow for improved and more efficient heat dissipation from the integrated wafer package, resulting in improved device reliability and device performance.

[0132] According to some embodiments, a method for manufacturing a semiconductor device includes the following operations. A first die and a second die are bonded to a first side of a substrate. A stress buffer structure is formed above the first die and the second die, wherein the stress buffer structure includes a first portion of a first through-hole extending through a first insulating layer, a second portion of the first through-hole extending through a second insulating layer, and a third portion of the first through-hole extending through a third insulating layer, wherein the second portion of the first through-hole is disposed between the first portion of the first through-hole and the third portion of the first through-hole, and wherein a diameter of the second portion of the first through-hole is smaller than a plurality of diameters of the first portion of the first through-hole and the third portion of the first through-hole. A metal layer is deposited above the stress buffer structure. In some embodiments, the first insulating layer, the second insulating layer, and the third insulating layer include a low-temperature polyimide (LTPI) material. In some embodiments, the first through-hole includes copper. In some embodiments, the diameter of the second portion of the first through-hole decreases vertically from a top surface of the stress buffer structure toward a bottom surface of the stress buffer structure. In some embodiments, the method further includes: forming a molding material over and around each of the first die and the second die before forming the stress buffer structure over the first die and the second die; and performing a planarization process to expose multiple top surfaces of the first die and the second die. In some embodiments, the method further includes coupling a heat sink to the top surface of the metal layer, wherein the first die is thermally coupled to the heat sink via a first via and the metal layer, and the first via is in physical contact with the top surface of the first die. In some embodiments, the stress buffer structure has a thickness of up to 100 μm.

[0133] According to some embodiments, a semiconductor device includes a first die, a second die, an encapsulant, and a stress buffering structure. The first die is above and bonded to a first side of the second die. The encapsulant surrounds the first die. A stress buffering structure is above the first die and the encapsulant, wherein the stress buffering structure includes a plurality of insulating layers and a plurality of first vias. Each of the first vias extends through the insulating layer, the first vias comprising copper, and a percentage of a total volume of copper in the first vias to a total volume of the stress buffering structure is in a range from 10% to 30%. In some embodiments, each of the insulating layers comprises a low-temperature polyimide (LTPI) material. In some embodiments, the first vias have a uniform density within the stress buffering structure. In some embodiments, a plurality of first vias in a first region of the stress buffering structure have a first density, and a plurality of second vias in a second region of the stress buffering structure have a second density, wherein the first and second densities are different. In some embodiments, the semiconductor device further includes: a metal layer above the stress buffering structure; and a heat dissipation structure above and coupled to the metal layer. In some embodiments, each of the first through-holes includes a top portion having a first diameter, a middle portion having a second diameter, and a bottom portion having a third diameter, wherein the second diameter is smaller than both the first and third diameters. In some embodiments, the semiconductor device further includes a packaging substrate coupled to the second side of the second die using a plurality of conductive connectors.

[0134] According to some embodiments, a semiconductor device includes a top die, a bottom die, a molding compound, a first stress buffer layer, a second stress buffer layer, and a heat sink. The top die is bonded to the bottom die. The molding compound surrounds the top die. A first stress buffer layer is above the top die, the first stress buffer layer including a plurality of first through-holes extending through a first dielectric material, wherein a first one of the first through-holes is in physical contact with a substrate of the top die, and wherein the substrate comprises silicon. A second stress buffer layer is above the first stress buffer layer, the second stress buffer layer including a plurality of second through-holes extending through a second dielectric material, wherein each of the second through-holes overlaps and is in physical contact with a corresponding one of the first through-holes. A heat sink is above the first through-holes and the second through-holes and is thermally coupled to the first through-holes and the second through-holes. In some embodiments, the semiconductor device further includes a third stress buffer layer. The third stress buffer layer is above the second stress buffer layer, the third stress buffer layer including a plurality of third through-holes extending through a third dielectric material, wherein a portion of each of the third through-holes overlaps and is in physical contact with a corresponding one of the second through-holes. In some embodiments, the semiconductor device further comprises a metal layer disposed between the third stress buffer layer and the heat sink, wherein the metal layer is in physical contact with a plurality of top surfaces of the third through-holes. In some embodiments, the first through-hole, the second through-hole, and the third through-hole comprise copper, and a percentage of a total volume of the copper of the first through-hole, the second through-hole, and the third through-hole to a total volume of the first stress buffer layer, the second stress buffer layer, and the third stress buffer layer is in a range from 10% to 30%. In some embodiments, the first dielectric material, the second dielectric material, and the third dielectric material comprise a low-temperature polyimide (LTPI) material. In some embodiments, a diameter of each of the second through-holes decreases vertically from a top surface of the second stress buffer layer toward a bottom surface of the second stress buffer layer.

[0135] The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a first die, a second die, a stress buffer structure, and a metal layer. The first die and the second die are bonded to a first side of the substrate. The stress buffer structure is above the first die and the second die, wherein the stress buffer structure includes a bottom portion of a first copper via extending through a first insulating layer, a middle portion of the first copper via extending through a second insulating layer, and a top portion of the first copper via extending through a third insulating layer, wherein the middle portion of the first copper via is disposed between the bottom portion and the top portion of the first copper via, and wherein a diameter of the middle portion of the first copper via is smaller than a plurality of diameters of the bottom portion and the top portion of the first copper via. The metal layer is above the stress buffer structure. In some embodiments, the stress buffer structure has a thickness of up to 100 μm.

[0136] The present disclosure also provides a semiconductor device. The semiconductor device includes a first die, a second die, an encapsulant, and a stress buffering structure. The first die is above and bonded to a first side of the second die. The encapsulant surrounds the first die. The stress buffering structure is above the first die and the encapsulant, wherein the stress buffering structure includes a plurality of insulating layers and a plurality of first copper vias, wherein each of the first copper vias extends through the insulating layer, and a percentage of a total volume of the first copper vias to a total volume of the stress buffering structure is in a range from 10% to 30%, and each of the first copper vias includes a bottom portion and a middle portion, wherein the diameter of the middle portion is smaller than the diameter of the bottom portion. In some embodiments, the first copper vias have a uniform density within the stress buffering structure. In some embodiments, a first plurality of the first copper vias in a first region of the stress buffering structure have a first density, and a second plurality of the first copper vias in a second region of the stress buffering structure have a second density, wherein the first density and the second density are different. In some embodiments, the semiconductor device further includes a packaging substrate coupled to the second side of the second die using a plurality of conductive connectors.

[0137] The present disclosure further provides a semiconductor device. The semiconductor device includes a bottom die, a top die, a molding layer, a first stress buffer layer, a second stress buffer layer, and a heat sink. The top die is bonded to the bottom die. The molding layer surrounds the top die. A first stress buffer layer is above the top die, the first stress buffer layer comprising a plurality of bottom portions of a plurality of first copper vias extending through a first dielectric layer, wherein a first one of the bottom portions is in physical contact with a silicon substrate of the top die. A second stress buffer layer is above the first stress buffer layer, the second stress buffer layer comprising a plurality of middle portions of the first copper vias extending through the second dielectric layer, wherein each of the middle portions overlaps and is in physical contact with a corresponding one of the bottom portions, and each of the middle portions has a diameter smaller than a diameter of each of the bottom portions. A heat sink is above the first copper vias and thermally coupled to the first copper vias. In some embodiments, the semiconductor device further includes a third stress buffer layer above the second stress buffer layer, the third stress buffer layer comprising a plurality of top portions of the first copper vias extending through a third dielectric layer, wherein a portion of each of the top portions overlaps and is in physical contact with a corresponding one of the middle portions. In some embodiments, the semiconductor device further comprises a metal layer disposed between the third stress buffer layer and the heat sink, wherein the metal layer is in physical contact with a plurality of top surfaces of the top portion. In some embodiments, a diameter of each of the intermediate portions decreases vertically from a top surface of the second stress buffer layer toward a bottom surface of the second stress buffer layer.

[0138] The foregoing summarizes the features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they may readily use this disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that such equivalent constructions may be variously modified, substituted, and replaced herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: include: a substrate; A first die and a second die are bonded to a first side of the substrate; A stress buffer structure is above the first die and the second die, wherein the stress buffer structure comprises: a bottom portion of a first copper via extending through a first insulating layer; a middle portion of the first copper via extending through a second insulating layer; and a top portion of the first copper via extending through a third insulating layer, wherein the middle portion of the first copper via is disposed between the bottom portion of the first copper via and the top portion of the first copper via, and wherein a diameter of the middle portion of the first copper via is smaller than diameters of the bottom portion of the first copper via and the top portion of the first copper via; and A metal layer is above the stress buffer structure.

2. The semiconductor device according to claim 1, wherein The stress buffer structure has a thickness of up to 100 μm.

3. A semiconductor device, characterized in that: include: a first die overlying and bonded to a first side of a second die; an encapsulant surrounding the first die; as well as A stress buffer structure is provided above the first die and the encapsulant, wherein the stress buffer structure comprises: Multiple insulation layers; as well as a plurality of first copper vias, wherein each of the plurality of first copper vias extends through the plurality of insulating layers, and a percentage of a total volume of the plurality of first copper vias to a total volume of the stress buffering structure is in a range from 10% to 30%, and each of the plurality of first copper vias includes a bottom portion and a middle portion, and a diameter of the middle portion is smaller than a diameter of the bottom portion.

4. The semiconductor device according to claim 3, wherein The plurality of first copper through holes have a uniform density within the stress buffer structure.

5. The semiconductor device according to claim 3, wherein A first plurality of the first copper vias in a first region of the stress buffer structure has a first density, and a second plurality of the first copper vias in a second region of the stress buffer structure has a second density, wherein the first density and the second density are different.

6. The semiconductor device according to any one of claims 3 to 5, wherein Also includes: A packaging substrate is coupled to a second side of the second die using a plurality of conductive connectors.

7. A semiconductor device, characterized in that: include: a top die bonded to a bottom die; a molding layer surrounding the top die; a first stress buffer layer over the top die, the first stress buffer layer comprising a plurality of bottom portions of a plurality of first copper vias extending through a first dielectric layer, wherein a first of the plurality of bottom portions is in physical contact with a silicon substrate of the top die; a second stress buffer layer overlying the first stress buffer layer, the second stress buffer layer comprising a plurality of middle portions of the plurality of first copper vias extending through a second dielectric layer, wherein each of the plurality of middle portions overlaps and physically contacts a corresponding one of the plurality of bottom portions, and a diameter of each of the plurality of middle portions is smaller than a diameter of each of the plurality of bottom portions; as well as A heat sink is located above and thermally coupled to the first copper through-holes.

8. The semiconductor device according to claim 7, wherein Also includes: a third stress buffer layer overlying the second stress buffer layer, the third stress buffer layer including a plurality of top portions of the plurality of first copper vias extending through a third dielectric layer, wherein a portion of each of the plurality of top portions overlaps and physically contacts a corresponding one of the plurality of middle portions.

9. The semiconductor device according to claim 8, wherein Also includes: A metal layer is disposed between the third stress buffer layer and the heat sink, wherein the metal layer is in physical contact with the top surfaces of the top portions.

10. The semiconductor device according to any one of claims 7 to 8, wherein A diameter of each of the plurality of middle portions decreases in a vertical direction from a top surface of the second stress buffer layer toward a bottom surface of the second stress buffer layer.

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