Interconnection structure

Abstract

The utility model provides an interconnection structure. The structure includes a dielectric layer; a conductive member disposed in the dielectric layer; and a conductive layer disposed over the dielectric layer, where the conductive layer includes a first portion and a second portion adjacent to the first portion. The structure also includes a first barrier layer contacting the first portion of the conductive layer; a second barrier layer contacting a second portion of the conductive layer; and a dielectric material disposed between the first barrier layer and the second barrier layer and contacting the first barrier layer and the second barrier layer, in which a bottom surface of the second barrier layer is substantially coplanar with a bottom surface of the dielectric material.

Description

Technical Field

[0001] The embodiments of the present utility model relate to semiconductor technology, and in particular to an interconnection structure. Background Art

[0002] As the semiconductor industry introduces new generations of integrated circuits (ICs) with higher performance and increased functionality, the density of components forming the ICs increases, while the size, dimensions, and spacing between components or elements decrease. In the past, this reduction was limited only by the ability to define structures using photolithography. Device geometries with smaller dimensions have created new constraints. For example, as the aspect ratio of conductive features in dielectric materials in back-end-of-line (BEOL) interconnect structures increases, the resistivity increases. Consequently, there is a need for improved interconnect structures. Utility Model Content

[0003] The purpose of the present invention is to provide an interconnection structure to solve at least one of the above problems.

[0004] In some embodiments, an interconnect structure is provided, comprising a dielectric layer; a conductive layer disposed over the dielectric layer, wherein the conductive layer comprises a first portion and a second portion adjacent to the first portion; a first barrier layer contacting the first portion of the conductive layer; a second barrier layer contacting the second portion of the conductive layer; and a dielectric material disposed between the first barrier layer and the second barrier layer and contacting the first barrier layer and the second barrier layer, wherein a bottom surface of the second barrier layer is substantially coplanar with a bottom surface of the dielectric material.

[0005] According to one embodiment of the present invention, a portion of the dielectric material further extends to contact at least a bottom surface of the first barrier layer.

[0006] According to one embodiment of the present invention, the dielectric material has an inverted T-shaped profile.

[0007] According to one embodiment of the present invention, the bottom of the dielectric material contacts the top surface of the dielectric layer.

[0008] According to one embodiment of the present invention, the present invention further includes: a barrier layer disposed above the dielectric layer, wherein a portion of the barrier layer contacts the bottom of the dielectric material.

[0009] According to one embodiment of the present invention, a portion of the barrier layer further contacts the first barrier layer and the second barrier layer.

[0010] According to one embodiment of the present invention, it further includes: a metal oxide layer disposed on the dielectric material.

[0011] In some embodiments, an interconnect structure is provided, which includes a dielectric layer; a first conductive component disposed in the dielectric layer; a conductive layer disposed above the dielectric layer, wherein the conductive layer includes a first portion and a second portion adjacent to the first portion, and the second portion of the conductive layer is disposed above the first conductive component; a first barrier layer contacting the first portion of the conductive layer; a second barrier layer contacting the second portion of the conductive layer, wherein the first barrier layer and the second barrier layer are separated by an air gap; and a capping layer contacting the first barrier layer, the second barrier layer, and the dielectric layer, wherein a portion of the capping layer is exposed to the air gap.

[0012] According to one embodiment of the present invention, the present invention further includes: a first dielectric material disposed above the air gap, wherein the first dielectric material includes a surface that is coplanar with a surface of the second portion of the conductive layer.

[0013] According to one embodiment of the present invention, the device further includes: a supporting layer contacting the first dielectric material, wherein the supporting layer is exposed to the air gap. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The following detailed description, taken in conjunction with the accompanying drawings, will provide a better understanding of the embodiments of the present invention. It should be noted that, in accordance with standard industry practice, the various features shown in the figures are not necessarily drawn to scale. In fact, the dimensions of various features may be arbitrarily enlarged or reduced for clarity of illustration.

[0015] Figure 1A is a perspective view of one of various stages in the fabrication of a semiconductor device structure according to some embodiments.

[0016] Figure 1B According to some embodiments, along Figure 1A BB is a cross-sectional side view of this stage of manufacturing the semiconductor device structure.

[0017] Figure 2 FIG. 1 is a cross-sectional side view of a stage in the fabrication of a semiconductor device structure according to some embodiments.

[0018] Figure 3A 、 Figure 3B 、 Figure 3B-1 、 Figure 3C 、 Figure 3D 、 Figure 3E 、 Figure 3F 、 Figure 3G 、 Figure 3H 、 Figure 3I 、 Figure 3J 、 Figure 3K 、 Figure 3L sectional side views of various stages in the fabrication of an interconnect structure according to some embodiments.

[0019] Figure 4A 、 Figure 4B 、 Figure 4C 、 Figure 4D 、 Figure 4E 、 Figure 4F sectional side views of various stages in the fabrication of an interconnect structure according to some embodiments.

[0020] Figure 4D-1 The figure shows some embodiments. Figure 4D An enlarged view of a portion of the interconnect structure is shown.

[0021] Figure 5A 、 Figure 5B 、 Figure 5C 、 Figure 5D 、 Figure 5E 、 Figure 5F 、 Figure 5G sectional side views of various stages in the fabrication of an interconnect structure according to some embodiments.

[0022] Figure 6A 、 Figure 6B 、 Figure 6C 、 Figure 6D 、 Figure 6E 、 Figure 6F 、 Figure 6G 、 Figure 6H sectional side views of various stages in the fabrication of an interconnect structure according to some embodiments.

[0023] Figure 6G-1 According to some embodiments, Figure 6G An enlarged view of a portion of the interconnect structure is shown.

[0024] Figure 7A 、 Figure 7B 、 Figure 7C 、 Figure 7D 、 Figure 7E 、 Figure 7F 、 Figure 7G 、 Figure 7H 、 Figure 7I 、 Figure 7J 、 Figure 7K 、 Figure 7L 、 Figure 7M 、 Figure 7N 、 Figure 7O 、 Figure 7P sectional side views of various stages in the fabrication of an interconnect structure according to some embodiments.

[0025] Figure 7P-1 According to some embodiments, Figure 7P An enlarged view of a portion of the interconnect structure is shown.

[0026] The reference numerals are as follows:

[0027] 100:Semiconductor device structure

[0028] 102: Base

[0029] 108: Channel Area

[0030] 114: Quarantine

[0031] 122: Gate spacer

[0032] 123: Fin sidewall spacer

[0033] 124: Source / drain region

[0034] 126: contact etch stop layer

[0035] 128: interlayer dielectric layer

[0036] 136: Gate dielectric layer

[0037] 138: Gate electrode layer

[0038] 140: Gate stack

[0039] 142: Source / drain contact

[0040] 144: Silicide layer

[0041] 200: device layer

[0042] 202: Intermetallic dielectric layer

[0043] 204, 206, 306, 350: Conductive parts

[0044] 250,300,400,500,600,700:interconnection structure

[0045] 304: dielectric layer

[0046] 310: Adhesive layer

[0047] 312: conductive layer

[0048] 314,344: Hard mask

[0049] 316,346,348: Opening

[0050] 318: first barrier layer

[0051] 320,349: Barrier layer

[0052] 328,342,728: Dielectric materials

[0053] 330,332,312t: Top surface

[0054] 334,352,550,650: cap layer

[0055] 336: Second barrier layer

[0056] 338:Metal oxide layer

[0057] 340: Etching stop layer

[0058] 722: Sacrificial layer

[0059] 724: Support layer

[0060] 726: Air gap

[0061] H1,H2:Height DETAILED DESCRIPTION

[0062] It should be understood that the following disclosure provides many different embodiments or examples to implement different components of the provided subject matter. Specific examples of the various components and their arrangement are described below in order to simplify the description of the disclosure. Of course, these are merely examples and are not intended to limit the embodiments of the present invention. For example, the size of an element is not limited to the range or value of an embodiment of the present disclosure, but may depend on the processing conditions and / or required properties of the element. In addition, in the subsequent description, forming a first component above or on a second component includes embodiments in which the first and second components are formed in direct contact, and may also include embodiments in which additional components can be formed between the first and second components so that the first and second components are not in direct contact. In addition, different examples in the disclosure may use repeated reference symbols and / or words. These repeated symbols or words are for the purpose of simplicity and clarity and are not intended to limit the relationship between the various embodiments and / or the described appearance structures.

[0063] Furthermore, to facilitate description of the relationship of one element or component to another element or component in the drawings, spatially relative terms such as "below," "beneath," "lower," "above," "above," "upper," "top," and similar terms may be used. Spatially relative terms also encompass different orientations of the device in use or operation in addition to the orientations depicted in the drawings. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and the descriptions of the spatially relative terms interpreted accordingly.

[0064] Figure 1A A stage in the fabrication of a semiconductor device structure 100 is shown, the semiconductor device structure 100 including a device layer 200 and an interconnect structure 250 . Figure 1BA schematic cross-sectional view of device layer 200 is shown according to some embodiments. Device layer 200 includes substrate 102 and one or more devices formed in or on substrate 102. Substrate 102 may be a semiconductor substrate. In some embodiments, substrate 102 includes a single crystalline semiconductor layer on at least a surface of substrate 102. Substrate 102 may include a crystalline semiconductor material, but is not limited to silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium arsenic antimonide (GaAsSb), and indium phosphide (InP). For example, substrate 102 is made of silicon. In some embodiments, substrate 102 is a silicon-on-insulator (SOI) substrate, which includes an insulating layer (not shown) disposed between two silicon layers. In one aspect, the insulating layer is an oxygen-containing material, such as an oxide.

[0065] The substrate 102 may include various regions that have been appropriately doped with impurities (eg, p-type or n-type impurities), such as phosphorus for n-type fin field effect transistors (FinFETs) or boron for p-type FinFETs.

[0066] As described above, the device layer 200 may include any suitable device, such as a transistor, a diode, an image sensor, a resistor, a capacitor, an inductor, a memory cell, or a combination thereof. In some embodiments, the device layer 200 includes transistors, such as planar field effect transistors (FETs), fin field effect transistors, nanostructured transistors, or other suitable transistors. The nanostructured transistors may include nanosheet transistors, nanowire transistors, gate-all-around (GAA) transistors, multi-bridge channel (MBC) transistors, or any transistor having a gate electrode surrounding a channel. An example of a device formed on the substrate 102 is a fin field effect transistor, shown in FIG. Figure 1A and Figure 1B The device layer 200 includes a source / drain (S / D) region 124 and a gate stack 140 ( Figure 1A Only one is shown). Each gate stack 140 may be disposed between the source / drain region 124 serving as a source region and the source / drain region 124 serving as a drain region. For example, each gate stack 140 may extend along the Y axis between one or more source / drain regions 124 serving as a source region and one or more source / drain regions 124 serving as a drain region. Figure 1B As shown, two gate stacks 140 are formed on the substrate 102. In some embodiments, more than two gate stacks 140 are formed on the substrate 102. Although not shown, a channel region is formed between the source / drain regions 124 and has at least three surfaces surrounded by the gate stacks 140.

[0067] The source / drain regions 124 may comprise a semiconductor material such as silicon or germanium, a Group III-V compound semiconductor, a Group II-VI compound semiconductor, or other suitable semiconductor material. Exemplary source / drain regions 124 may comprise, but are not limited to, Ge, SiGe, GaAs, AlGaAs, GaAsP, SiP, InAs, AlAs, InP, GaN, InGaAs, InAlAs, GaSb, AlP, GaP, and the like. The source / drain regions 124 may include a p-type dopant (e.g., boron); an n-type dopant (e.g., phosphorus or arsenic); and / or other suitable dopants including combinations thereof. The source / drain regions 124 may be formed by epitaxial growth using chemical vapor deposition, atomic layer deposition (ALD), or molecular beam epitaxy (MBE). The channel region may include one or more semiconductor materials, such as Si, Ge, GeSn, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, GaP, or InP. The channel region may include the same semiconductor material as substrate 102. In some embodiments, device layer 200 may include a fin field-effect transistor, and the channel region is a plurality of fins disposed below gate stack 140. In some embodiments, device layer 200 may include a nanostructure transistor, and gate stack 140 surrounds the channel region.

[0068] like Figure 1A and Figure 1BAs shown, each gate stack 140 includes a gate electrode layer 138 disposed above the channel region (or surrounding the channel region for nanostructured transistors). Gate electrode layer 138 may be a metal-containing material such as tungsten, cobalt, aluminum, ruthenium, copper, multiple layers thereof, or the like, and may be deposited by atomic layer deposition, plasma-enhanced chemical vapor deposition (PECVD), molecular beam epitaxy, physical vapor deposition (PVD), or any suitable deposition technique. Gate stack 140 may further include a gate dielectric layer 136 disposed above the channel region. Gate electrode layer 138 may be disposed above gate dielectric layer 136. In some embodiments, an interfacial layer (not shown) may be disposed between channel region 108 and gate dielectric layer 136, and one or more work function layers (not shown) may be formed between gate dielectric layer 136 and gate electrode layer 138. The interfacial layer may comprise a dielectric material, such as an oxygen-containing material, a nitrogen-containing material, or a multilayer thereof, and may be formed by a suitable deposition method, such as chemical vapor deposition, plasma-assisted chemical vapor deposition, or atomic layer deposition. The gate dielectric layer 136 may comprise a dielectric material, such as an oxygen-containing material, a nitrogen-containing material, a high dielectric constant dielectric material having a dielectric constant value greater than that of silicon dioxide, or a multilayer thereof. The gate dielectric layer 136 may be formed by any suitable method, such as chemical vapor deposition, plasma-assisted chemical vapor deposition, or atomic layer deposition. In some embodiments, the gate dielectric layer 136 may be a compliant layer. The term "compliant" may be used herein to conveniently describe a layer having approximately the same thickness over each region. One or more work function layers may comprise titanium aluminum carbide, titanium aluminum oxide, titanium aluminum nitride, or the like.

[0069] The gate spacers 122 are formed along the sidewalls of the gate stack 140 (e.g., the sidewalls of the gate dielectric layer 136). The gate spacers 122 may comprise silicon oxycarbide, silicon nitride, silicon oxynitride, silicon carbon nitride, the like, multiple layers thereof, or combinations thereof, and may be deposited by chemical vapor deposition, atomic layer deposition, or other suitable deposition techniques. In some embodiments, fin sidewall spacers 123 may be disposed on both sides of each source / drain region 124, and the fin sidewall spacers 123 may comprise the same material as the gate spacers 122. A portion of the gate stack 140, the gate spacers 122, and the fin sidewall spacers 123 may be disposed on the isolation region 114. The isolation region 114 is disposed on the substrate 102. The isolation region 114 may comprise an insulating material, such as an oxygen-containing material, a nitrogen-containing material, or a combination thereof. In some embodiments, the isolation region 114 is a shallow trench isolation (STI). The insulating material may be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor deposition (FCVD), or other suitable deposition processes. In one aspect, the isolation region 114 comprises silicon oxide formed by a flowable chemical vapor deposition process.

[0070] A contact etch stop layer (CESL) 126 is formed on the source / drain regions 124 and the isolation regions 114, and an interlayer dielectric (ILD) layer 128 is formed on the CESL 126. The CESL 126 provides a mechanism to stop the etching process when an opening is formed in the ILD layer 128. The CESL 126 may be conformally deposited on the surfaces of the source / drain regions 124 and the isolation regions 114. The CESL 126 may include an oxygen-containing material or a nitrogen-containing material, such as silicon nitride, silicon carbon nitride, silicon oxynitride, carbon nitride, silicon oxide, silicon carbon oxide, the like, or combinations thereof, and may be deposited by chemical vapor deposition, plasma-assisted chemical vapor deposition, atomic layer deposition, or any suitable deposition technique. The interlayer dielectric layer 128 may include an oxide formed from tetraethylorthosilicate (TEOS), undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), organosilicate glass (OSG), SiOC, and / or any suitable low-k dielectric material (e.g., a material having a lower dielectric constant than silicon dioxide), and may be deposited by spin coating, chemical vapor deposition, flowable chemical vapor deposition, plasma-assisted chemical vapor deposition, physical vapor deposition, or any suitable deposition technique.

[0071] Source / drain contacts 142 may be disposed in the interlayer dielectric layer 128 and on the source / drain regions 124. The source / drain contacts 142 may be conductive and include a material comprising one or more of Ru, Mo, Co, Ni, W, Ti, Ta, Cu, Al, TiN, or TaN. The conductive contacts may be formed by any suitable method, such as electrochemical plating (ECP) or physical vapor deposition. A silicide layer 144 may be disposed between the source / drain contacts 142 and the source / drain regions 124. The silicide layer 144 may be made of a metal or metal alloy silicide, and the metal may include a noble metal, a refractory metal, a rare earth metal, an alloy thereof, or a combination thereof.

[0072] In integrated circuits, interconnect structures (or interconnect line structures) are used to provide signal paths and power supply for semiconductor devices. Integrated circuit chips generally include device layers fabricated during front-end-of-line (FEOL) and middle-end-of-line (MEOL) processes, as well as back-end-of-line (BEOL) layers. The device layers may be formed in and / or on a substrate, and the back-end-of-line layers may be formed on the front side and / or back side of the device layers. The device layers may include various semiconductor devices, such as transistors, diodes, capacitors, inductors, etc., and may be formed in and / or on a substrate. In some embodiments, the device layer may also include a mid-stage structure, such as one or more dielectric layers having conductive components connected to gate and source / drain components in the device layer. The interconnect structures generally include conductive lines and vias formed in the device layer and back-end-of-line layers.

[0073] Figure 2 1 is a cross-sectional side view of a stage in the manufacture of a semiconductor device structure 100 according to some embodiments. An interconnect structure 250 is disposed above the device layer 200 and the substrate 102. The interconnect structure 250 includes various device components, such as a first plurality of conductive components 204 and a second plurality of conductive components 206 and an intermetallic dielectric (IMD) layer 202 to separate and isolate the various conductive components 204 and 206. In some embodiments, the first plurality of conductive components 204 are wires and the second plurality of conductive components 206 are vias. The interconnect structure 250 includes multiple layers of conductive components 204, and the conductive components 204 are arranged in each layer to provide an electrical path for the device layer 200 disposed thereunder. The conductive components 206 provide vertical electrical paths from the device layer 200 to the conductive components 204 and between the conductive components 204. For example, the bottommost conductive component 206 of the interconnect structure 250 can be electrically connected to a source / drain region 124 ( Figure 1A and Figure 1B ) and the gate electrode layer 138 ( Figure 1A and Figure 1B ). Conductive members 204 and 206 may be made of one or more conductive materials, such as metals, metal alloys, metal nitrides, or silicides. For example, conductive members 204 and 206 may be made of copper, aluminum, aluminum-copper alloys, titanium, titanium nitride, tantalum, tantalum nitride, titanium silicon nitride, zirconium, gold, silver, cobalt, nickel, tungsten, tungsten nitride, tungsten silicon nitride, platinum, chromium, molybdenum, hafnium, other suitable conductive materials, or combinations thereof. In some embodiments, a backside interconnect structure (not shown) similar to interconnect structure 250 may be formed on the backside of device layer 200 to provide power supply and / or additional signal connections for device layer 200.

[0074] The IMD layer 202 includes one or more dielectric materials to provide isolation between the conductive components 204 and 206. The IMD layer 202 may include multiple dielectric layers that embed the multiple conductive components 204 and 206. The IMD layer 202 is made of a dielectric material, such as SiO x 、SiO x C y H z or SiO x C y , wherein x, y, and z are integers or non-integers. In some embodiments, the IMD layer 202 includes a dielectric material having a dielectric constant value in the range of about 1 to about 5.

[0075] Figures 3A to 3L The interconnect structure 300 is a cross-sectional side view of various stages of fabrication according to some embodiments. The interconnect structure 300 may be used to form Figure 1A and Figure 1B as well as Figure 2 One or more layers of the interconnect structure 250 shown. Figure 3A As shown, the interconnect structure 300 includes a dielectric layer 304 and one or more conductive features 306 (only one is shown here) disposed in the dielectric layer 304. The dielectric layer 304 can be an interlayer dielectric layer or an intermetallic dielectric (IMD) layer. For example, the dielectric layer 304 can be the interlayer dielectric layer 128 ( Figure 1A and Figure 1B ) or the intermetal dielectric layer 202 ( Figure 2 ). An optional capping layer (not shown) may be disposed on each conductive feature 306. Dielectric layer 304 may comprise the same material as interlayer dielectric layer 128 or intermetallic dielectric layer 202. In some embodiments, dielectric layer 304 comprises a low-k dielectric material having a dielectric constant value in a range of approximately 1.5 to approximately 3.9. In some embodiments, dielectric layer 304 comprises silicon oxide. In some embodiments, dielectric layer 304 comprises SiCOH. Dielectric layer 304 may be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), spin coating, or other suitable processes.

[0076] The conductive component 306 and the capping layer (if used) may each comprise a conductive material such as Cu, Co, Ru, Mo, Cr, W, Mn, Rh, Ir, Ni, Pd, Pt, Ag, Au, Al, alloys of the foregoing, or other suitable materials. In some embodiments, the conductive component 306 and the capping layer each comprise a metal. The conductive component 306 and the capping layer (if used) may be formed by physical vapor deposition (PVD), chemical vapor deposition, atomic layer deposition, or other suitable processes. In some embodiments, the conductive component 306 may have a thickness of about 1000 nm. to about and the cap layer (if used) may have a thickness of about to about The conductive member 306 can be electrically connected to the corresponding source / drain region 124 ( Figure 1A and Figure 1B ) and / or gate electrode layer 138 ( Figure 1A and Figure 1B In some embodiments, the conductive component 306 may be a conductive contact disposed in the interlayer dielectric layer 128 or the conductive components 204 and 206 disposed in the intermetallic dielectric layer 202. For example, the conductive component 306 may be Figure 2 In some embodiments, the conductive feature 306 may include a barrier layer (not shown) disposed between the dielectric layer 306 and the conductive material of the conductive feature 306. The barrier layer may include a conductive material, such as a metal or a metal nitride.

[0077] Please refer to Figure 3A , a glue layer 310, a conductive layer 312, and a hard mask 314 are formed over the dielectric layer 304. In some embodiments, the glue layer 310 is formed on the dielectric layer 304, the conductive layer 312 is formed on the glue layer 310, and the hard mask 314 is formed on the conductive layer 312. In some embodiments, the glue layer 310 is not present, and the conductive layer 312 is formed on the dielectric layer 304. The glue layer 310 may comprise a nitride, such as a metal nitride, and may be formed by physical vapor deposition, chemical vapor deposition, atomic layer deposition, or other suitable process. In some embodiments, the glue layer 310 comprises TiN or TaN. The glue layer 310 may have a thickness of about to about . Glue layer 310 can provide adhesion between conductive layer 312 and the cap layer (if used) or conductive component 306. Conductive layer 312 can include the same material as conductive component 306 and can be formed using the same process as conductive component 306. Conductive layer 312 can have the same thickness as conductive component 306. Hard mask 314 can include SiN, SiON, SiO2, the like, or a combination thereof and can be formed using chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin coating, or other suitable processes. In one exemplary embodiment, hard mask 314 is SiN.

[0078] Next, openings 316 are formed in hard mask 314, conductive layer 312, and adhesive layer 310. Openings 316 can be formed by first patterning hard mask 314 and then transferring the pattern of hard mask 314 to conductive layer 312 and adhesive layer 310. Openings 316 can be formed by a suitable process, such as wet etching, dry etching, or a combination thereof. In some embodiments, openings 316 are formed by one or more etching processes. Openings 316 separate conductive layer 312 into one or more portions, such as multiple portions. Depending on the layout, openings 316 can have different widths from one another. In some embodiments, each portion of conductive layer 312 is a conductive component, such as a wire.

[0079] exist Figure 3B In the embodiment, a first barrier layer 318 is selectively formed on the dielectric layer 304. The first barrier layer 318 may be a self-assembled monolayer (SAM) having a head group and a tail group. The head group of the SAM may be selected so that the head group of the SAM is not formed on the hard mask 314, the conductive layer 312, and the glue layer 310. The tail group of the SAM may be selected so that the tail group of the SAM blocks the precursor (e.g., the precursor used to form the subsequent barrier layer 320). Figure 3C ) is formed on the first barrier layer 318. Suitable materials for the first barrier layer 318 may include organic substances, such as 3-(aminopropyl)triethoxysilane, N-(3-triethoxysilylpropyl)ethylenediamine, 2-(diphenylphosphino)ethyltriethoxysilane, 2-cyanoethyltriethoxysilane, (3-mercaptopropyl)triethoxysilane, N-[3-(diethoxymethylsilyl)propyl]ethylenediamine, diethyl [2-(diethoxymethylsilyl)ethyl]phosphonate, and 3-(2-pyridylethyl)thiopropyltrimethoxysilane. The first barrier layer 318 can be formed by a wet coating process, and the solution used for wet coating can be a protic organic solvent, such as an alcohol, a carboxylic acid, or a combination thereof. Exemplary protic organic solvents include, but are not limited to, methanol, ethanol, 1-propanol, 2-propanol, 1-butanol, 1-pentanol, 1-hexanol, 1-heptanol, 2-ethoxyethanol, and combinations thereof. The solution used for wet coating may also be a polar or non-polar protic solvent. Exemplary polar aprotic solvents include, but are not limited to, N,N-dimethylformamide, N-methyl-2-pyrrolidone, acetonitrile, acetone, ethyl acetate, benzyl ether, trioctylphosphine, trioctylphosphine oxide, and mixtures thereof. Exemplary non-polar protic solvents include, but are not limited to, alkanes, olefins, aromatics, esters, or ether solvents, hexane, octane, benzene, toluene, xylene, and mixtures thereof.

[0080] Other materials, such as compounds with silicon or carbon end groups, may also be used to bond to the exposed surface of the dielectric layer 304. In these embodiments, the first barrier layer 318 may include butyltriethoxysilane, cyclohexyltrimethoxysilane, cyclopentyltrimethoxysilane, dodecyltriethoxysilane, dodecyltrimethoxysilane, decyltriethoxysilane, dimethoxy(methyl)-n-octylsilane, triethoxyethylsilane, ethyltrimethoxysilane, hexyltrimethoxysilane, hexyltriethoxysilane, hexadecyltrimethoxysilane, hexadecyltriethoxysilane, triethoxymethylsilane, trimethoxy ... methoxy(methyl))silane, methoxy(dimethyl)octadecylsilane, methoxy(dimethyl)-n-octylsilane, octadecyltriethoxysilane, triethoxy-n-octylsilane, octadecyltrimethoxysilane, trimethoxy(propyl)silane, trimethoxy-n-octylsilane, triethoxy(propyl)silane, methane, ethane, propane, butane, pentane, hexane, heptane, octane, nonane, decane, undecane, dodecane, pentadecane, hexadecane or other suitable compounds. In these cases, the first barrier layer 318 can be formed by atomic layer deposition, chemical vapor deposition, spin coating, dipping, free radical reaction by remote plasma or other suitable process. The first barrier layer 318 can have a thickness of about to about in the range.

[0081] In some alternative embodiments, the hard mask 314 and the dielectric layer 304 are made of the same material (eg, SiO x ) is formed, a treatment process may be performed to activate the dielectric surface of the hard mask 314 and the dielectric layer 304 in the opening 316. The treatment process may be a plasma treatment process using a process gas (e.g., hydrogen, ammonia and / or an oxygen-containing gas). The oxygen-containing gas may include oxygen, carbon dioxide or other suitable oxygen-containing gases. Next, a first barrier layer 318 is formed on the activated dielectric surface of the hard mask 314 and the dielectric layer 304. This allows the subsequent barrier layer 320 ( Figure 3C ) is deposited on the exposed conductive surface of the conductive layer 312 and the adhesive layer 310, such as Figure 3B-1 shown.

[0082] exist Figure 3CIn the embodiment of the present invention, a barrier layer 320 is formed on the exposed surfaces of the hard mask 314, the conductive layer 312, and the glue layer 310 in each opening 316. The barrier layer 320 may be selectively formed on the exposed surfaces of the hard mask 314, the conductive layer 312, and the glue layer 310, but not on the first barrier layer 318. In other words, the first barrier layer 318 prevents the barrier layer 320 from being formed on the dielectric layer 304. Depending on the thickness of the barrier layer 320, in some cases, the glue layer 310 may or may not be exposed for the barrier layer 320 deposited on the glue layer 310. The barrier layer 320 may comprise a nitride, such as a metal nitride. In some embodiments, the barrier layer 320 comprises a refractory metal nitride, such as TiN or TaN. Other metal materials, such as metal oxides (e.g., RuO-2), may also be used. The selective deposition of the barrier layer 320 can be achieved and / or enhanced by using an atomic layer deposition process and / or a molecular layer deposition (MLD) process, so that the barrier layer 320 has the characteristic or property of specifically bonding with the exposed surfaces of the hard mask 314, the conductive layer 312, and the glue layer 310 through self-limiting surface reactions. Because the portion of the metal-like barrier layer 320 formed on the adjacent portions of the conductive layer 312 is not connected, time-dependent dielectric breakdown (TDDB) failures caused by line-to-line leakage (i.e., leakage between adjacent portions of the conductive layer 312) are reduced. In addition, the use of the first barrier layer 318 as a barrier layer between the dielectric layer 304 and the subsequent dielectric material 328 also helps to reduce the overall dielectric constant value of the interconnect structure 300 and reduce the possibility of time-dependent dielectric breakdown failures due to poor barrier properties associated with the use of dielectric material barrier layers. The barrier layer 320 can have a thickness of about 1000 nm. to about in the range.

[0083] exist Figure 3D In the embodiment, after forming the barrier layer 320, a dielectric material 328 is formed on the barrier layer 320 and the first barrier layer 318. The dielectric material 328 may be a silicon-containing material, such as SiOC, SiO x , SiCN, SiN, SiCON, SiC, or SiON. In some embodiments, dielectric material 328 comprises a low-k dielectric material, such as SiCOH, having a dielectric constant value in the range of about 2 to about 3.6. The low-k dielectric material may have a porosity in the range of about 0.1% to about 40%. Dielectric material 328 may fill opening 316 ( Figure 3C) and over the hard mask 314 until the desired height is achieved. The dielectric material 328 can be formed by flowable chemical vapor deposition, chemical vapor deposition, atomic layer deposition, physical vapor deposition, plasma-assisted chemical vapor deposition, plasma-assisted atomic layer deposition (PEALD), or other suitable processes.

[0084] exist Figure 3E , a planarization process is performed to remove the dielectric material 328, the barrier layer 320, and a portion of the hard mask 314. The planarization process may be performed until the conductive layer 312 is exposed. The barrier layer 320 disposed on the sidewalls of the hard mask 314 may also be removed by the planarization process. The planarization process may be any suitable process, such as a chemical-mechanical polishing (CMP) process. As a result of the planarization process, the top surface 330 of the conductive layer 312 may be substantially coplanar with the top surface 332 of the dielectric material 328. In addition, the bottom of the barrier layer 320, the bottom of the dielectric material 328, and the top surface of the first barrier layer 318 are substantially coplanar. Depending on the height of the opening 316, the remaining dielectric material 328 may have a thickness of about to about The dielectric material 328 protects the first barrier layer 318 during the planarization process.

[0085] In adopting Figure 3B-1 In the case of the alternative embodiment shown, the barrier layer 320 is selectively deposited on the exposed surfaces of the conductive layer 312 and the glue layer 310 (if exposed). After the dielectric material 328 is formed, a planarization process is performed until the conductive layer 312 is exposed, so that the interconnect structure 300 is substantially the same as Figure 3E Shown embodiment.

[0086] exist Figure 3F In the embodiment of the present invention, after the planarization process, a capping layer 334 may be selectively formed on the top surface 330 of the conductive layer 312. The capping layers 334 may each comprise a conductive material, such as Cu, Co, Ru, Mo, Cr, W, Mn, Rh, Ir, Ni, Pd, Pt, Ag, Au, Al, alloys thereof, or other suitable materials. In some embodiments, the capping layers 334 may each comprise a metal. The capping layer 334 may be formed by physical vapor deposition, chemical vapor deposition, atomic layer deposition, or other suitable processes. In some embodiments, the capping layer 334 has a thickness of about 1000 nm. to about The capping layer 334 may be selectively formed on the top surface 330 (which may be metal), but not on the top surface 332 of the dielectric material 328 .

[0087] exist Figure 3GDuring the treatment, a treatment process may be performed to activate the metal surfaces of the cap layer 334 and the barrier layer 320. The treatment process may be a plasma treatment process using a process gas such as hydrogen, ammonia, and / or an oxygen-containing gas. The oxygen-containing gas may include oxygen, carbon dioxide, or other suitable oxygen-containing gases. After the treatment process, a second barrier layer 336 is formed on the activated metal surfaces of the cap layer 334 and the barrier layer 320.

[0088] The second barrier layer 336 may include one or more self-assembled monolayers (SAMs) having a head group and a tail group. The head group of the self-assembled monolayer may be selected based on the material of the cap layer 334. In some embodiments, the head group of the self-assembled monolayer may include a phosphorus (P), sulfur (S), silicon (Si) or nitrogen (N) terminated compound, which may only attach to the treated metal surface of the cap layer 334. The head group of the self-assembled monolayer may not be formed on the dielectric surface of the dielectric material 328. The tail group of the self-assembled monolayer may include a highly hydrophobic long alkyl chain that prevents the adsorption of precursors (such as precursors for forming the subsequent metal oxide layer 338) formed on the second barrier layer 336. In some embodiments, the tail group includes a polymer, such as polyimide. The second barrier layer 336 may be formed, for example, by providing a blocking agent to the exposed surface by chemical vapor deposition, atomic layer deposition, molecular layer deposition (MLD), wet coating, immersion process or other suitable methods. The second barrier layer 336 may have a thickness of about to about in the range.

[0089] In some embodiments, the second barrier layer 336 comprises 1-octadecyl mercaptan, 1-dodecyl mercaptan, stearic acid, 4-dodecylbenzenesulfonic acid, dimethyl octadecylphosphonate, bis(dodecyl)dithiophosphinic acid, bis(octadecyl)dithiophosphinic acid, diethyl n-octadecylphosphonate, octadecylphosphonic acid, decylphosphonic acid, tetradecylphosphonic acid, 2-mercaptobenzothiazole, 2-mercaptobenzoxazole, 2-mercaptobenzimidazole, benzothiazole, benzene Benzimidazole, 2-methylbenzimidazole, 5,6-dimethylbenzimidazole, 2-(methylthio)benzimidazole, 1,2,3-triazole, 1,2,4-triazole, 3-amino-1,2,4-triazole, 1-hydroxybenzotriazole hydrate, 4-methyl-1H-benzotriazole, 5-methyl-1H-benzotriazole, 5,6-dimethyl-1H-benzotriazole, 4-hydroxy-1H-benzotriazole, 1-methylbenzotriazole Amide, 2-methylbenzothiazole, imidazole, methimazole, 5-phenyl-1H-tetrazole, benzotriazole, 5-(3-aminophenyl)tetrazole, 4-amino-4H-1,2,4-triazole, 3-amino-5-mercapto-1,2,4-triazole, 3-amino-5-methylthio-1H-1,2,4-triazole, 2-aminopyrimidine, 2-mercaptopyrimidine, adenine, hypoxanthine, morpholine, 5-amino-1,3,4-thiadiazole- 2-thiol, tryptophan, histidine, 5-(trifluoromethyl)-1H-1,2,3-benzotriazole, 1H-benzotriazole, 1-(4-morpholinylmethyl), phenothiazine, purine, melamine, trithiocyanuric acid, 1,3,4-thiadiazole-2,5-diamine, 3,5-diamino-1,2,4-triazole, 5-aminotetrazole, 3,6-bis(methylthio)-1,2,4,5-tetrazine, aminophylline or other suitable compounds.

[0090] exist Figure 3H In the embodiment, a selective metal oxide layer 338 is formed on the exposed top surface 332 of the dielectric material 328 ( Figure 3E ). The metal oxide layer 338 may be selectively formed on the exposed dielectric surface of the dielectric material 328, but not formed on the second barrier layer 336. In other words, the second barrier layer 336 blocks the metal oxide layer 338 from forming on the metal surface of the cap layer 334. The second barrier layer 336 blocks the precursor of the metal oxide layer 338 from forming thereon, so that the precursor of the metal oxide layer 338 grows on the dielectric surface (such as the dielectric material 328). The metal oxide layer 338 may include a metal, such as Al, Ti, Zr, Hf, Y or other suitable metal. The metal oxide layer 338 may be formed by any suitable process, such as chemical vapor deposition, atomic layer deposition or spin coating. The metal oxide layer 338 extends above the level of the top surface of a portion of the conductive layer 312. The metal oxide layer 338 may have a thickness of about to about The metal oxide layer 338 prevents the subsequent formation of the conductive component 350 ( Figure 3K ) enters between adjacent portions of the conductive layer 312 due to edge placement error (EPE). Therefore, if the thickness of the metal oxide layer 338 is less than about The metal oxide layer 338 may not be sufficient to prevent the conductive member 350 ( Figure 3K ) into between adjacent portions of the conductive layer 312. On the other hand, if the thickness of the metal oxide layer 338 is greater than about Then the manufacturing cost increases, but there is no significant advantage.

[0091] exist Figure 3I The second barrier layer 336 is removed. The removal of the second barrier layer 336 may be performed by any suitable process, such as plasma treatment, thermal treatment, or selective plasma etching. The top surface of the metal oxide layer 338 may be higher than the top surface of the cap layer 334.

[0092] Next, an etch stop layer 340 is formed on the top surface of the metal oxide layer 338 and the top surface of the cap layer 334. A portion of the etch stop layer 340 is also formed on the top surface of the barrier layer 320. The etch stop layer 340 can be a single layer or a multi-layer structure. In some embodiments, the etch stop layer 340 can be an oxide, such as a metal oxide. For example, the etch stop layer 340 can include Al, Zr, Y, Hf, or other suitable metals. In some embodiments, the etch stop layer 340 includes a silicon-containing material, such as SiOC, SiCN, SiN, SiCON, SiO x , SiC, SiON or other suitable materials. The etch stop layer 340 may include a material different from the metal oxide layer 338 to have a different etch selectivity than the metal oxide layer 338. The etch stop layer 340 may be formed by any suitable process, such as chemical vapor deposition, atomic layer deposition, spin coating or any conformal deposition process. The etch stop layer 340 may have a thickness of about to about in the range.

[0093] Next, dielectric material 342 is formed on etch stop layer 340, and hard mask 344 is formed on dielectric material 342. Dielectric material 342 may include the same material as dielectric material 328 and may be formed using the same process as dielectric material 328. Etch stop layer 340 and dielectric material 342 may have different etch selectivities, and metal oxide layer 338 and dielectric material 342 may have different etch selectivities. Hard mask 344 may include the same material as hard mask 314 and may be formed using the same process as hard mask 314. A selective etch stop layer (not shown) may be embedded in dielectric material 342.

[0094] exist Figure 3J , an opening 346 (sometimes also referred to as a via opening) and an opening 348 (sometimes also referred to as a trench opening) are formed in the hard mask 344 and the dielectric material 342. Openings 346 and 348 can be formed by a dual damascene process. For example, opening 346 can be formed by first patterning the hard mask 344 and then transferring the pattern to a portion of the dielectric material 342. A selective etch stop layer (not shown) embedded in the dielectric material 342 can be used to form opening 346. Next, opening 348 is formed by covering a portion of the bottom of opening 346. Thus, opening 348 has a smaller size than opening 346. In some embodiments, opening 348 is a via and opening 346 is a trench. Openings 346 and 348 can be formed by any suitable process, such as one or more etching processes. The etching process also removes a portion of the etch stop layer 340 and the capping layer 334, so that opening 348 exposes a portion of the top surface 312t of the conductive layer 312.

[0095] In some embodiments, opening 348 is aligned with a portion of conductive layer 312, such as a portion of conductive layer 312 disposed between two dielectric materials 328. In some embodiments, opening 348 may be slightly misaligned with this portion of conductive layer 312, exposing a portion of metal oxide layer 338. This misalignment of the via is referred to as edge placement error (EPE). If metal oxide layer 338 is not present, opening 348 may also be formed on dielectric material 328 because dielectric material 342 and dielectric material 328 may comprise the same material. Consequently, subsequently formed conductive features may be formed in dielectric material 328 between adjacent portions of conductive layer 312, which may result in line-to-line leakage. Reliability issues, such as poor breakdown voltage or time-dependent dielectric breakdown, may occur due to line-to-line leakage. With the metal oxide layer 338 disposed on the dielectric material 328, the etching process used to form the opening 348 does not substantially affect the metal oxide layer 338 due to the different etch selectivity of the metal oxide layer 338 compared to the dielectric material 342 and the dielectric material 328. In addition, as described above, the metal oxide layer 338 extends above the level of the top surface of this portion of the conductive layer 312 and has a thickness of about to about . Therefore, even if the etching process used to form opening 348 removes some of metal oxide layer 338, opening 348 is not formed in dielectric material 328 due to the thickness of metal oxide layer 338. Therefore, by including metal oxide layer 338, the risk of line-to-line leakage due to edge placement errors can be reduced. Furthermore, the use of atomic layer deposition (ALD) metal-like barrier layer 320 helps further reduce the possibility of time-dependent dielectric breakdown, which can cause poor barrier properties associated with barrier layers made of dielectric materials.

[0096] In the Figure 3K , a barrier layer 349 and a conductive component 350 are formed in openings 346 and 348. The barrier layer 349 may include Co, W, Ru, Al, Mo, Ti, TiN, TiSi, CoSi, NiSi, Cu, TaN, Ni, or TiSiNi, and may be formed by any suitable process, such as physical vapor deposition, atomic layer deposition, or plasma-assisted chemical vapor deposition. In some embodiments, the barrier layer 349 may be a compliant layer formed by a compliant process, such as atomic layer deposition. The conductive component 350 may include a conductive material, such as a metal. For example, the conductive component 350 includes Cu, Ni, Co, Ru, Ir, Al, Pt, Pd, Au, Ag, Os, W, Mo, alloys of the foregoing, or other suitable materials. The conductive component 350 may be formed by any suitable process, such as electrochemical plating (ECP), physical vapor deposition, chemical vapor deposition, or plasma-assisted chemical vapor deposition. The conductive component 350 may include a conductive material disposed in the opening 348 ( Figure 3J ) and a second portion disposed above the first portion. In some embodiments, the first portion of the conductive feature 350 may be a via, and the second portion of the conductive feature 350 may be a conductive line. The metal oxide layer 338 prevents the conductive feature 350 from being formed between adjacent portions of the conductive layer 312. The conductive feature 350 may be disposed adjacent to and above the metal oxide layer 338. In other words, a portion of the conductive feature 350 may be disposed adjacent to a vertical surface of the metal oxide layer 338 and above a horizontal surface of the metal oxide layer 338.

[0097] exist Figure 3L , a planarization process is performed to remove the barrier layer 349 and the portion of the conductive member 350 disposed above the hard mask 344, and the hard mask 344 can be removed by the planarization process. The planarization process can be any suitable process, such as a chemical mechanical polishing process. A capping layer 352 can be optionally formed on the conductive member 350. The capping layer 352 can include the same material as the conductive member 306. For example, the capping layer 352 includes a metal. The capping layer 352 can be formed by the same process as the optional capping layer (not shown) described above. The capping layer 352 can be optionally formed on the conductive member 350 (which can be a metal), but not on the dielectric material 342. Although not shown, it is contemplated that one or more back-end-of-line (BEOL) processes can be performed on the dielectric material 342 and the capping layer 352.

[0098] Figures 4A to 4F 4 is a cross-sectional side view of various stages of fabricating an interconnect structure 400 according to some embodiments. Various embodiments of the interconnect structure 400 may be used to form Figure 1A 、 Figure 1B 、 Figure 2 One or more layers of the interconnect structure 250 shown in FIG. Figures 4A to 4F The embodiment shown is substantially the same as Figures 3A to 3L The embodiment shown is different except that the first barrier layer 318 is removed before the dielectric material 328 is formed. In this embodiment, the first barrier layer 318 is deposited ( Figure 4B ), a barrier layer 320 is selectively deposited on the exposed surfaces of the glue layer 310 (if exposed), the conductive layer 312 and the hard mask 314, as shown in FIG. Figure 4C The barrier layer 320 may be similar to that described above. Figure 3C Next, the first barrier layer 318 ( Figure 4D The first barrier layer 318 can be removed by any suitable process, such as plasma treatment, thermal treatment (e.g., UV curing), or selective plasma etching. In the case of plasma treatment, both the first barrier layer 318 and the barrier layer 320 can be exposed to a plasma containing H2, H2 / NH3, NH3, etc. The plasma can be generated in situ or from a remote plasma. The plasma treatment removes the first barrier layer 318 and densifies the barrier layer 320.

[0099] After the first barrier layer 318 is removed, the adhesive layer 310 and the dielectric material 304 are exposed, and the dielectric material 328 is similar to the above reference Figure 3D The dielectric material 328 is deposited on the barrier layer 320, the glue layer 310 and the dielectric material 304 in the manner discussed above. Since the first barrier layer 318 is not present, the dielectric material 328 directly contacts the dielectric material 304 and the glue layer 310, as shown in FIG. Figure 4D Similarly, a planarization process is performed to remove a portion of the dielectric material 328, the barrier layer 320, and the hard mask 314 until the conductive layer 312 is exposed, as shown. Figure 4E As shown. After the planarization process, the top surfaces of the conductive layer 312, the barrier layer 320 and the dielectric material 328 are substantially coplanar. Figures 3F to 3L Discuss the process to achieve Figure 4F Interconnect structure 400 is shown. Barrier layer 320 is disposed between and contacts conductive layer 312 and dielectric material 328. A top surface of barrier layer 320 contacts etch stop layer 340, and a top surface of dielectric material 328 contacts metal oxide layer 338.

[0100] In this embodiment, interconnect structure 400 is formed with low contact resistance and low capacitive coupling between adjacent conductive features because dielectric material 328 directly contacts dielectric layer 304, without a dielectric barrier layer disposed between dielectric material 328 and dielectric layer 304, which could otherwise result in time-dependent dielectric breakdown failures due to the poor barrier properties of the dielectric used. Furthermore, because portions of metalloid barrier layer 320 formed on adjacent portions of conductive layer 312 are not connected, time-dependent dielectric breakdown failures due to line-to-line leakage (i.e., leakage between adjacent portions of conductive layer 312) are reduced.

[0101] Figure 4D-1 According to some embodiments, Figure 4D FIG4 is an enlarged view of a portion of interconnect structure 400 in FIG4 . As shown, the bottom portion of dielectric material 328 has a footing that extends radially into the region created by the removal of first barrier layer 318, defined by barrier layer 320, glue layer 310, and dielectric layer 304. Thus, a portion of dielectric material 328 extends laterally and outwardly to contact at least the bottom surface of barrier layer 320. Dielectric material 328 further exhibits an inverted T-shaped profile at the bottom portion, which contacts dielectric layer 304, glue layer 310, and barrier layer 320. Specifically, glue layer 310 does not contact barrier layer 320.

[0102] Figures 5A to 5G 5. The various embodiments of the interconnect structure 500 may be used to form Figure 1A 、 Figure 1B 、 Figure 2 One or more layers of the interconnect structure 250 shown in FIG. Figures 5A to 5G The embodiment shown is substantially the same as Figures 3A to 3L In the embodiment shown, a capping layer is further disposed on the barrier layer 320 and the first barrier layer 318 before the dielectric material 328 is formed. In this embodiment, before the first barrier layer 318 ( Figure 5B ), a barrier layer 320 is selectively deposited on the exposed surfaces of the glue layer 310 (if exposed), the conductive layer 312 and the hard mask 314, as shown in FIG. Figure 5C The barrier layer 320 may be similar to that described above. Figure 3C Then, the capping layer 550 is conformally deposited on the barrier layer 320 and the first barrier layer 318, as shown in FIG. Figure 5DAs shown. The capping layer 550 protects the barrier layer 320 from oxidation during the subsequent deposition of the dielectric material 328. The presence of the capping layer 550 is advantageous when the dielectric material 325 comprises an oxide, which may oxidize the barrier layer 320 during the formation of the dielectric material 325. The capping layer 550 may be a silicon-containing material, such as SiOC, SiCN, SiN, SiCON, SiC, or SiON. In some embodiments, the capping layer 550 and the subsequent dielectric material 328 comprise materials that are chemically different from each other. The capping layer 550 may be formed by atomic layer deposition, chemical vapor deposition, physical vapor deposition, plasma-assisted atomic layer deposition, or other suitable process. The capping layer 550 may have a thickness of about to about After forming the cap layer 550, the dielectric material 328 is similar to the above reference Figure 3D The method discussed is deposited on the cap layer 550 ( Figure 5E ). Then, a planarization process is performed to remove a portion of the dielectric material 328, the capping layer 550, the barrier layer 320, and the hard mask 314 until the conductive layer 312 is exposed, as shown in FIG. Figure 5F As shown. After the planarization process, the top surfaces of the conductive layer 312, the cap layer 550, the barrier layer 320 and the dielectric material 328 are substantially coplanar. Figures 3F to 3L Discuss the process to achieve Figure 5G An interconnect structure 500 is shown.

[0103] In this embodiment, the interconnect structure 500 is formed with low contact resistance and low capacitive coupling (between adjacent conductive features) because the first barrier layer 318 (having a low dielectric constant value) is included between the cap layer 550 and the dielectric layer 304. Furthermore, because a portion of the metalloid barrier layer 320 formed on adjacent portions of the conductive layer 312 is not connected, time-dependent dielectric breakdown failures due to line-to-line leakage (i.e., leakage between adjacent portions of the conductive layer 312) can be reduced.

[0104] Figures 6A to 6H sectional side views of various stages of fabricating an interconnect structure 600 according to some embodiments. Various embodiments of the interconnect structure 600 may be used to form Figure 1A 、 Figure 1B 、 Figure 2 One or more layers of the interconnect structure 250 shown in FIG. Figures 6A to 6H The embodiment shown is substantially the same as Figures 5A to 5G The embodiment shown is the same except that the first barrier layer 318 is removed before the dielectric material 328 is formed. In this embodiment, after the first barrier layer 318 is deposited ( Figure 6B ), the barrier layer 320 is selectively deposited on the exposed surfaces of the glue layer 310 (if exposed), the conductive layer 312 and the hard mask 314, as shown in FIG. Figure 6CThe barrier layer 320 may be similar to that described above. Figure 3C Next, the first barrier layer 318 ( Figure 6D ). The first barrier layer 318 can be removed by any suitable process, such as plasma treatment, thermal treatment, or selective plasma etching. After removing the first barrier layer 318, the capping layer 650 is then conformally deposited on the barrier layer 320, the glue layer 310, and the dielectric layer 304, as shown in FIG. Figure 6E As shown. Cap layer 650 may comprise the same material as cap layer 550 and may be deposited using the same deposition techniques as cap layer 550. Similarly, cap layer 650 and subsequent dielectric material 328 may comprise materials that are chemically different from each other. After forming cap layer 650, dielectric material 328 may be deposited in a manner similar to that described above with reference to FIG. Figure 3D The method discussed is deposited on the cap layer 650 ( Figure 6F ). Then, a planarization process is performed to remove a portion of the dielectric material 328, the capping layer 650, the barrier layer 320, and the hard mask 314 until the conductive layer 312 is exposed, as shown in FIG. Figure 6G As shown. After the planarization process, the top surfaces of the conductive layer 312, the cap layer 650, the barrier layer 320 and the dielectric material 328 are substantially coplanar. Figures 3F to 3L Discuss the process to achieve Figure 6H An interconnect structure 600 is shown.

[0105] In this embodiment, interconnect structure 600 is formed with low contact resistance and low capacitive coupling (between adjacent conductive features) because a portion of cap layer 650 is disposed between dielectric material 328 and dielectric layer 304 and contacts both dielectric material 328 and dielectric layer 304. This provides good barrier properties and eliminates concerns about leakage that may occur due to time-dependent dielectric breakdown failures that may occur with dielectric barriers. Furthermore, because a portion of metalloid barrier layer 320 formed on adjacent portions of conductive layer 312 is not connected, time-dependent dielectric breakdown failures due to line-to-line leakage (i.e., leakage between adjacent portions of conductive layer 312) are reduced.

[0106] Figure 6G-1 According to some embodiments, Figure 6G , a magnified view of a portion of interconnect structure 600 in FIG. As shown, the bottom of dielectric material 328 has a footing that extends radially into the area defined by barrier layer 320, glue layer 310, and dielectric layer 304. Dielectric material 328 thus exhibits an inverted T-shaped profile at the bottom. Dielectric material 328 is separated from barrier layer 320, glue layer 310, and dielectric layer 304 by cap layer 650, which directly contacts dielectric layer 304, glue layer 310, and barrier layer 320. Specifically, glue layer 310 does not contact barrier layer 320.

[0107] Figures 7A to 7P sectional side views of various stages of fabricating an interconnect structure 700 according to some embodiments. Various embodiments of the interconnect structure 700 may be used to form Figure 1A 、 Figure 1B 、 Figure 2 One or more layers of the interconnect structure 250 shown in FIG. Figures 7A to 7E The embodiment shown is substantially the same as Figures 6A to 6E The embodiment shown is not described here in detail. Figure 7F , after forming the capping layer 650, a sacrificial layer 722 is formed in the opening 316 and on the hard mask 314. The sacrificial layer 722 may include a polymer, such as an organic layer having C, O, N or C, O, N and / or H. In some embodiments, the sacrificial layer 722 includes polyurea. The sacrificial layer 722 may be formed by any suitable process, such as chemical vapor deposition, atomic layer deposition, plasma assisted chemical vapor deposition (PECVD), plasma assisted atomic layer deposition (PEALD), or spin coating. Then, the sacrificial layer 722 is recessed to a level below the level of the top surface 321 of the conductive layer 312. The recessing of the sacrificial layer 722 may be performed by any suitable process, such as thermal baking, UV curing, an etch-back process (such as a plasma etching process), or any combination of the foregoing. The recessing of the sacrificial layer 722 may partially open the opening 316, such as Figure 7F In some embodiments, the recess of the sacrificial layer 722 may expose at least a portion of the capping layer 650 in the opening 316. The remaining sacrificial layer 722 may have a height H1 of about to about in the range.

[0108] exist Figure 7G In the embodiment, the support layer 724 is formed on the exposed surface of the interconnect structure 700. In some embodiments, the support layer 724 is formed on the cap layer 650 and the sacrificial layer 722. The support layer 724 may include Si, O, N, or any combination thereof. In some embodiments, the support layer 724 includes SiO, SiCO, SiNO, SiCN, or SiCON. The support layer 724 may be porous to allow UV energy, heat energy, plasma, etc. to reach the sacrificial layer 722 disposed below the support layer 724. The support layer 724 may have a thickness of about to about In the range of, for example, about to about The support layer 724 can be formed by any suitable process, such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, plasma-assisted chemical vapor deposition, or plasma-assisted atomic layer deposition. In some embodiments, the support layer 724 is a compliant layer formed by a low-temperature atomic layer deposition or chemical vapor deposition process. The term "compliant" is used herein to describe a layer having substantially the same thickness over various regions.

[0109] Next, a dielectric material 728 is formed on the support layer 724. The dielectric material 728 may include a silicon-containing material such as SiCO, SiCN, SiN, SiCON, SiO x , SiC or SiON. In some embodiments, the dielectric material 728 comprises a low dielectric constant dielectric material, such as SiCOH, having a dielectric constant value in the range of about 2 to about 3.6. The low dielectric constant dielectric material may have a porosity in the range of about 0.1% to about 40%. The dielectric material 728 may fill the opening 316 ( Figure 7F ), and may be formed over the hard mask 314. The dielectric material 728 may be formed by chemical vapor deposition, atomic layer deposition, plasma-assisted chemical vapor deposition, plasma-assisted atomic layer deposition, or other suitable processes.

[0110] exist Figure 7H , the sacrificial layer 722 is removed, and an air gap 726 is formed in each opening 316 below the support layer 724. The removal of the sacrificial layer 722 may be caused by degradation or decomposition of the sacrificial layer 722. The degradation or decomposition of the sacrificial layer 722 may be performed by any suitable process, such as thermal baking and / or UV curing. In some embodiments, a UV curing process is used to remove the sacrificial layer 722. UV energy may pass through the porous support layer 724 to reach and remove the sacrificial layer 722. The UV energy may have an energy density of about 10 mJ / cm 2 About mJ / cm 2 The removal of the sacrificial layer 722 does not substantially affect other layers of the interconnect structure 700. The air gap 726 may have a height H2 that is substantially the same as Figure 7F The height H1 of the sacrificial layer 722 is shown in FIG. The air gap 726 can reduce the capacitive coupling between adjacent portions of the conductive layer 312. If the height H2 is less than about The air gap 726 may not provide reduced capacitive coupling between adjacent portions of the conductive layer 312. On the other hand, if the height H2 is greater than about The support layer 724 may not have sufficient contact with the barrier layer 320 to prevent material subsequently formed on the support layer 724 from collapsing into the air gap 726 .

[0111] exist Figure 7IIn the process, a planarization process may be performed to remove the portion of the dielectric material 728 formed above the conductive layer 312. The hard mask layer 314 and the portion of the support layer 724 disposed on the hard mask 314 may also be removed by the planarization process. The planarization process may be any suitable process, such as a chemical mechanical polishing process. As a result of the planarization process, the top surface 330 of the conductive layer 312 may be substantially coplanar with the top surface 332 of the dielectric material 728. The remaining dielectric material 728 may have a thickness of about to about The support layer 724 and the dielectric material 728 prevent the introduction of materials (such as polishing slurry) into the air gap 726 during the planarization process.

[0112] The above references can be made to the planarized interconnect structure 700. Figures 3F to 3L For example, after the planarization process, a capping layer 334 is selectively formed on the top surface 330 of the conductive layer 312 ( Figure 7J ). Then, the second barrier layer 336 is formed on the metal surface of the cap layer 334 and the barrier layer 320. The second barrier layer 336 is not formed on the dielectric surface of the support layer 724, the dielectric material 728 and the cap layer 650, as shown in FIG. Figure 7K Next, a metal oxide layer 338 is formed on the exposed top surface 332 ( Figure 7I ). The metal oxide layer 338 is not formed on the second barrier layer 336 and the barrier layer 320 ( Figure 7L ), as mentioned above Figure 3H Next, the second barrier layer 336 is removed by plasma etching or any suitable process. Thereafter, a contact etch stop layer 340, a dielectric material 342, and a hard mask 344 are sequentially formed on the exposed surfaces of the metal oxide layer 338, the cap layer 334, and the barrier layer 320, as shown in FIG. Figure 7M Next, openings 346 and 348 are formed in the hard mask 344 and the dielectric material 342 ( Figure 7N ).exist Figure 7O In the embodiment, the barrier layer 349 and the conductive member 350 are formed in the openings 346 and 348. A planarization process is performed to remove a portion of the barrier layer 349 and the conductive member 350 until the dielectric material 342 is exposed. Then, a capping layer 352 is selectively formed on the conductive member 350, as shown in FIG. Figure 7P Although not shown, it is contemplated that one or more back-end-of-line (BEOL) processes may be performed on the dielectric material 342 and the capping layer 352 .

[0113] Figure 7P-1 According to some embodiments, Figure 7P7 is an enlarged view of a portion of interconnect structure 700 in FIG. In some embodiments, cap layer 650 and support layer 724 surround an air gap 726 disposed between adjacent portions of conductive layer 312. Support layer 724 and dielectric material 728 are disposed above air gap 726. Each conductive feature includes conductive layer 312 disposed between glue layer 310 and cap layer 334. The bottom of cap layer 650 contacts dielectric layer 304 and has a footing profile that extends radially to the area defined by barrier layer 320, glue layer 310, and dielectric layer 304. Barrier layer 320 extends to cover the entire sidewalls of conductive layer 312. The upper portion of cap layer 650 is disposed between barrier layer 320 and support layer 724, contacting both. Dielectric material 728 is disposed between support layer 724 and metal oxide layer 338, contacting both. The bottom of the metal oxide layer 338 further contacts the support layer 724 and the capping layer 650. A portion of the top surface and at least one side of the metal oxide layer 338 contact the etch stop layer 340, and a portion of the top surface and at least one side of the metal oxide layer 338 contact the barrier layer 349. The space where the air gap 726 is located has a generally inverted T-shaped profile that expands outward in a direction away from the dielectric layer 304.

[0114] Embodiments of the present invention provide an interconnect structure with reduced contact resistance and capacitive coupling between adjacent conductive components by providing a separate metal barrier layer disposed on adjacent portions of a conductive layer. The separate barrier layer can reduce line-to-line leakage, which can occur due to time-dependent dielectric breakdown failures caused by the use of a dielectric barrier between a dielectric material and a dielectric layer. In some embodiments, an air gap can be disposed between adjacent portions of the conductive layer, with a support layer and dielectric material disposed above the air gap. The air gap can reduce capacitive coupling between adjacent portions of the conductive layer. The support layer prevents material from filling the air gap.

[0115] One embodiment provides an interconnect structure comprising a dielectric layer; a conductive member disposed in the dielectric layer; and a conductive layer disposed over the dielectric layer, wherein the conductive layer comprises a first portion and a second portion adjacent to the first portion. The structure also comprises a first barrier layer contacting the first portion of the conductive layer; a second barrier layer contacting the second portion of the conductive layer; and a dielectric material disposed between and contacting the first and second barrier layers, wherein a bottom surface of the second barrier layer is substantially coplanar with a bottom surface of the dielectric material.

[0116] In some other embodiments, a portion of the dielectric material further extends to contact at least a bottom surface of the first barrier layer.

[0117] In some other embodiments, the dielectric material has an inverted T-shaped profile.

[0118] In some other embodiments, the bottom of the dielectric material contacts the top surface of the dielectric layer.

[0119] In some other embodiments, the interconnect structure further includes a barrier layer disposed above the dielectric layer, wherein a portion of the barrier layer contacts a bottom of the dielectric material.

[0120] In some other embodiments, the barrier layer is a self-assembled monolayer having head groups and tail groups.

[0121] In some other embodiments, a portion of the barrier layer further contacts the first barrier layer and the second barrier layer.

[0122] In some other embodiments, the barrier layer contacts the bottom of the first barrier layer and the second barrier layer.

[0123] In some other embodiments, the bottoms of the first barrier layer and the second barrier layer, the bottom of the dielectric material, and the top surface of the barrier layer are substantially coplanar.

[0124] In some other embodiments, the interconnect structure further includes a metal oxide layer disposed on the dielectric material.

[0125] Another embodiment provides an interconnect structure comprising a dielectric layer; a first conductive member disposed in the dielectric layer; and a conductive layer disposed over the dielectric layer, wherein the conductive layer comprises a first portion and a second portion adjacent to the first portion, and the second portion of the conductive layer is disposed over the first conductive member. The structure also comprises a first barrier layer contacting the first portion of the conductive layer; a second barrier layer contacting the second portion of the conductive layer, wherein the first barrier layer and the second barrier layer are separated by an air gap. The structure further comprises a capping layer contacting the first barrier layer, the second barrier layer, and the dielectric layer, wherein a portion of the capping layer is exposed to the air gap.

[0126] In some other embodiments, the interconnect structure further includes a first dielectric material disposed above the air gap, wherein the first dielectric material includes a surface that is substantially coplanar with a surface of the second portion of the conductive layer.

[0127] In some other embodiments, the interconnect structure further includes a supporting layer contacting the first dielectric material, wherein the supporting layer is exposed to the air gap.

[0128] In some other embodiments, a portion of the support layer is disposed between the capping layer and the first dielectric material, and contacts the capping layer and the first dielectric material.

[0129] In some other embodiments, the interconnect structure further includes a metal oxide layer disposed on the surface of the first dielectric material; and a second conductive component disposed above the second portion of the conductive layer, wherein the second conductive component is disposed adjacent to and above the metal oxide layer.

[0130] In some other embodiments, the interconnect structure further includes a second dielectric material disposed over the first portion of the conductive layer and the first dielectric material; and an etch stop layer disposed between the second dielectric material and the metal oxide layer and contacting the second dielectric material and the metal oxide layer.

[0131] In some other embodiments, the second conductive component is disposed in the second dielectric material.

[0132] In some other embodiments, the first barrier layer and the second barrier layer each comprise a refractory metal nitride.

[0133] Another embodiment provides a method for forming an interconnect structure, the method comprising forming a conductive layer over a dielectric layer; forming one or more openings in the conductive layer to expose a portion of the dielectric layer, wherein the one or more openings separate the conductive layer into one or more portions. The method also comprises forming a barrier layer on the exposed surface of the dielectric layer; forming the barrier layer to contact the one or more portions of the conductive layer; forming a capping layer on the barrier layer; forming a dielectric material on the capping layer to fill the one or more openings; and performing a planarization process until the one or more portions of the conductive layer are exposed.

[0134] In some other embodiments, the method further includes removing the barrier layer before forming the capping layer.

[0135] The foregoing text summarizes the features of many embodiments, enabling those skilled in the art to better understand the various aspects of the embodiments of the present invention. Those skilled in the art will understand and can readily design or modify other processes and structures based on the embodiments of the present invention to achieve the same objectives and / or the same advantages as the embodiments described herein. Those skilled in the art will also understand that these equivalent structures do not depart from the spirit and scope of the embodiments of the present invention. Various changes, substitutions, or modifications may be made to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention.

Claims

1. An interconnection structure, characterized in that: include: a dielectric layer; a conductive layer disposed above the dielectric layer, wherein the conductive layer comprises a first portion and a second portion adjacent to the first portion; a first barrier layer contacting the first portion of the conductive layer; a second barrier layer contacting the second portion of the conductive layer; and A dielectric material is disposed between the first barrier layer and the second barrier layer and contacts the first barrier layer and the second barrier layer, wherein a bottom surface of the second barrier layer is coplanar with a bottom surface of the dielectric material.

2. The interconnect structure according to claim 1, wherein: A portion of the dielectric material further extends to contact at least a bottom surface of the first barrier layer.

3. The interconnect structure according to claim 2, wherein: The dielectric material has an inverted T-shaped profile.

4. The interconnection structure according to claim 3, wherein: The bottom of the dielectric material contacts the top surface of the dielectric layer.

5. The interconnect structure according to claim 1, wherein: Also includes: A barrier layer is disposed above the dielectric layer, wherein a portion of the barrier layer contacts the bottom of the dielectric material.

6. The interconnect structure according to claim 5, wherein: A portion of the barrier layer further contacts the first barrier layer and the second barrier layer.

7. The interconnection structure according to any one of claims 1 to 6, wherein: Also includes: A metal oxide layer is disposed on the dielectric material.

8. An interconnection structure, characterized in that include: a dielectric layer; a first conductive component disposed in the dielectric layer; a conductive layer disposed above the dielectric layer, wherein the conductive layer comprises a first portion and a second portion adjacent to the first portion, and the second portion of the conductive layer is disposed above the first conductive component; a first barrier layer contacting the first portion of the conductive layer; a second barrier layer contacting the second portion of the conductive layer, wherein the first barrier layer and the second barrier layer are separated by an air gap; and A capping layer contacts the first barrier layer, the second barrier layer and the dielectric layer, wherein a portion of the capping layer is exposed to the air gap.

9. The interconnect structure according to claim 8, wherein: Also includes: A first dielectric material is disposed above the air gap, wherein the first dielectric material includes a surface coplanar with a surface of the second portion of the conductive layer.

10. The interconnect structure according to claim 9, wherein Also includes: A support layer contacts the first dielectric material, wherein the support layer is exposed to the air gap.

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