CP signal processing module based on AC charging pile

Abstract

The utility model discloses a CP signal processing module based on an AC charging pile, comprising a power supply circuit, a PWM output circuit and a signal processing circuit, the output end of the power supply circuit is connected with the PWM output circuit and the signal processing circuit, and the output end of the PWM output circuit is connected with the signal processing circuit. According to the utility model, the independent power supply design is adopted, and the problem that the voltage amplitude of the output PWM signal does not meet the national standard limit value requirement is solved. The comparison circuit directly samples CP signals and converts voltage signals transmitted by the electric automobile into digital signals in an undifferentiated mode, and two-way communication of the automobile pile is achieved. A multi-stage low-pass filtering processing technology is adopted, high-frequency interference is filtered out, and the problem that a measured voltage value fluctuates due to high-frequency interference of a traditional AC pile CP voltage acquisition circuit is effectively solved.

Description

Technical Field

[0001] The utility model relates to the technical field of electric vehicle charging, and in particular to a CP signal processing module based on an AC charging pile. Background Art

[0002] The PWM signal processing circuit in traditional AC charging piles uses a conventional power module to output ±12V voltages. This output uses a switch-to-switch design to generate PWM signals. The electric vehicle recognizes the PWM signal's duty cycle and initiates the charging process. Due to output accuracy errors in the externally purchased power module and a voltage drop of |Vd|≈0.7V during the on-state of the switch, the output PWM signal voltage amplitude does not meet the national standard limits (+VCCmin=11.2V, -VCCmax=-11.4V).

[0003] In addition, the technical conditions for AC orderly charging piles for electric vehicles Q / GDW 12154-2021 added a communication protocol between vehicles and piles based on the GB / T18487.1 protocol. "Before charging, the vehicle switches the S2 switch to generate 9V and 6V pulses, and the charging pile detects 9V (1) and 6V (0) signals for communication." It requires the AC charging pile to identify the pulse signal sent by the vehicle, analyze the vehicle's SOC, VIN code and other information, and realize two-way communication between the vehicle and the pile.

[0004] This puts higher demands on the traditional AC charging pile PWM signal processing technology. Utility Model Content

[0005] The purpose of this utility model is to provide a CP signal processing module based on an AC charging pile, which solves the problem that the amplitude consistency of the PWM signal output by the traditional AC pile is not high and the PWM signal voltage value does not meet the national standard requirements for the PWM signal voltage limit.

[0006] The utility model is implemented by the following technical solutions: a signal processing module based on an AC charging pile CP, comprising: a power supply circuit, a PWM output circuit, and a signal processing circuit, wherein the output end of the power supply circuit is connected to the PWM output circuit and the signal processing circuit, and the output end of the PWM output circuit is connected to the signal processing circuit;

[0007] The power supply circuit is the input of the external power supply voltage into the AC charging pile CP signal processing module, converting the input single power supply voltage into the VPOS and VNEG dual power supply voltages required by the module;

[0008] The PWM output circuit amplifies the PWM signal input from the main control system and outputs a PWM signal that meets standard requirements;

[0009] The signal processing circuit modulates the collected PWM signal and outputs controllable analog and digital TTL level signals.

[0010] Furthermore, the power supply circuit includes a power supply chip U1, and the power supply chip U1 model is ADP5071; PVIN1, PVIN2, PVINSYS, EN1, and EN2 of the power supply chip U1 are connected to the power input terminal VIN, and the power input terminal VIN is also connected to one end of the capacitors C3 and C5, and the other end of the capacitors C3 and C5 is connected to the ground terminal GND; the COMP1 pin of the power supply chip U1 is connected to the capacitor C1 and the resistor R2 in series, the COMP2 pin of the power supply chip U1 is connected to the capacitor C2 and the resistor R4 in series, the capacitor C6 is connected between the VREG pin of the power supply chip U1 and the ground terminal GND, the SYNC / FREQ and AGND pins of the power supply chip U1 are connected to the ground terminal GND, the power inductor L1 is connected between the INBK pin and the SW1 pin of the power supply chip U1, and the power chip U1 The SW1 pin is connected to the positive electrode of diode D1, the negative electrode of diode D1 is connected to the internal positive power supply VPOS of the module, resistor R7 is connected between the internal positive power supply VPOS of the module and the FB1 pin of the power supply chip U1, resistor R8 is connected between the FB1 pin of the power supply chip U1 and the ground terminal GND, the EP and PGND pins of the power supply chip U1 are connected to the ground terminal GND, capacitor C7 is connected between the VREF pin of the power supply chip U1 and the ground terminal GND, resistor R13 is connected between the VREF pin of the power supply chip U1 and the FB2 pin, resistor R14 is connected between the FB2 pin of the power supply chip U1 and the internal negative power supply VNEG, the SW2 pin of the power supply chip U1 is connected to the negative electrode of diode D3, the positive electrode of diode D3 is connected to the internal negative power supply VNEG of the module, and the power inductor L2 is connected between the SW2 pin of the power supply chip U1 and the ground terminal GND.

[0011] Furthermore, the PWM output circuit includes an integrated operational amplifier U3A, resistors R21, R22, R24, R25, R26, an NPN transistor Q1, a PNP transistor Q2, and a capacitor C9; one end of the resistor R26 is connected to the external input PWM signal, and the other end is connected to the second pin of U3A; the resistors R21 and R24 divide the positive power supply VPOS, and input the output voltage to the third pin of the integrated operational amplifier U3A to provide a threshold voltage for the level change inside the circuit; the eighth pin of the integrated operational amplifier U3A is connected to the positive power supply VPOS, and the fourth pin of the integrated operational amplifier U3A is connected to the positive power supply VPOS. Connect to the negative power supply VNEG; capacitor C9 is connected across the positive power supply VPOS and the negative power supply VNEG to act as a filter; one end of the resistor R22 is connected to the positive power supply VPOS inside the module, and the other end is connected to the first pin of the output end of the integrated operational amplifier U3A; the collector of the transistor Q1 is connected to the positive power supply VPOS inside the module, the base is connected to the first pin of the output end of the integrated operational amplifier U3A, and the emitter is connected to one end of the resistor R25; the collector of the transistor Q2 is connected to the negative power supply VNEG inside the module, the base is connected to the first pin of the output end of the integrated operational amplifier U3A, and the emitter is connected to one end of the resistor R25.

[0012] Furthermore, the signal processing circuit includes a digital signal output signal generating circuit, a CP grounding alarm output signal generating circuit before starting charging, and a CP grounding detection alarm output signal generating circuit during charging. The structures of the three signal generating circuits are the same.

[0013] Furthermore, the digital signal output signal generating circuit includes an integrated operational amplifier U2A, resistors R1, R3, R5, R6, R9, R10, R11, and a diode D2; one end of the current limiting resistor R5 is connected to the CP_OUT signal output by the PWM output circuit, and the other end is connected to the third pin of the integrated operational amplifier U2A; resistors R10 and R11 divide the positive power supply VPOS and input the voltage signal to the second pin of the integrated operational amplifier U2A to provide a threshold voltage for the level change inside the circuit; the eighth pin of the integrated operational amplifier U2A is connected to the positive power supply VPOS, and the fourth pin of the integrated operational amplifier U2A is connected to the positive power supply VPOS. The pin is connected to the negative power supply VNEG; a resistor R1 is connected between the third pin of the integrated operational amplifier U2A and the first pin of the output end, and the resistors R5, R1 and U2A together constitute a hysteresis comparator; one end of the resistor R3 is connected to the positive power supply VPOS voltage divider, and the other end of the resistor R3 is connected to one end of the resistor R9 and one end of the resistor R6, the other end of the resistor R9 is grounded, and the other end of the resistor R6 is connected to the cathode of the diode D2, and the anode of the diode D2 is grounded; after the output signal of the hysteresis comparator is modulated by the limit value circuit composed of the resistors R3, R9, R6 and the diode D2, the module outputs a controllable SOC_ACQ signal.

[0014] Furthermore, the output end of the PWM output circuit is also connected to a filter circuit, which includes resistors R33, R34, R35, R36, R37, R38, R39, R40, integrated operational amplifiers U4A, U4B, a diode D6 and capacitors C10, C12, C13, C14; wherein the output signal of the PWM output circuit is divided by the series resistors R36 and R40 of the low-pass filter circuit, wherein one end of the resistor R36 is connected to the output signal output end of the PWM output circuit, the other end of the resistor R36 is connected to one end of the resistor R40, the other end of the resistor R40 is grounded, the resistor R40 is connected in parallel with the capacitor C13, the other end of the resistor R36 is connected to the non-inverting end of the integrated operational amplifier U4B through the series resistors R37 and R38, and the resistor R37 is connected to the non-inverting end of the integrated operational amplifier U4B. , capacitor C10 is connected between the connection end of R38 and the inverting and inverting ends of the operational amplifier U4B, capacitor C14 is connected between the inverting end of the integrated operational amplifier U4B and the ground end, the inverting end of the integrated operational amplifier U4B is connected to the output end, the output end of the integrated operational amplifier U4B is connected to the positive electrode of the diode D6, the negative electrode of the diode D6 is connected to one end of the resistor R34, the other end of the resistor R34 is connected to the inverting end of the integrated operational amplifier U4A, one end of the resistor R39, and one end of the capacitor C12, the other end of the resistor R39 and the other end of the capacitor C12 are grounded, the inverting end of the operational amplifier U4A is connected to the output end, the output end of the operational amplifier U4A is connected to one end of the resistor R33, the other end of the resistor R33 is connected to one end of the resistor R35, and the other end of the resistor R35 is grounded.

[0015] Advantages of this utility model:

[0016] 1) The utility model adopts an independent power supply design to solve the problem that the output PWM signal voltage amplitude does not meet the national standard limit requirements.

[0017] 2) The comparison circuit directly samples the CP signal and converts the 9V (1) and 6V (0) voltage signals transmitted from the electric vehicle into digital signals without any difference, thus realizing two-way communication between the vehicle and the charging pile.

[0018] 3) Multi-stage low-pass filtering technology is used to filter out high-frequency interference, effectively solving the problem of measured voltage fluctuation caused by high-frequency interference in the traditional AC pile CP voltage acquisition circuit.

[0019] 4) The analog and switch quantities detect the CP voltage simultaneously, and a hysteresis comparator design scheme is adopted. It has multiple protection mechanisms, rapid fault handling response, strong anti-interference ability, and is stable and reliable. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0021] Figure 1 This is a schematic diagram of the appearance and structure of an AC charging pile CP signal processing module of the utility model;

[0022] Figure 2 This is a schematic diagram of the internal principle of the CP signal processing module of an AC charging pile in this utility model;

[0023] Figure 3 This is a data communication diagram of the CP signal processing module of an AC charging pile in the utility model;

[0024] Figure 4 This is a waveform diagram of the PWM signal output by the CP signal processing module of an AC charging pile in this utility model. DETAILED DESCRIPTION

[0025] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0026] As attached Figure 1 As shown: A CP signal processing module based on an AC charging pile, the pin function definitions are as follows:

[0027] VIN: DC voltage input positive pole;

[0028] GND: DC voltage input negative pole;

[0029] CP_IN: PWM signal TTL level input;

[0030] CP_OUT: PWM signal ±12V voltage output;

[0031] SOC_ACQ: Digital signal output. This pin allows the AC charging station's main control system to identify the pulse signal sent by the vehicle. During the charging process, the main control system can also use this pin to monitor the AC charging station's output PWM signal frequency.

[0032] INCPG_DET: CP ground fault alarm output before starting charging. During the charging process, when the CP signal ground fault occurs, the INCPG_DET pin outputs an alarm level. When the CP signal returns to normal, the INCPG_DET pin outputs a normal level.

[0033] PWM_AL: CP grounding detection alarm output during charging. When a CP signal grounding fault occurs during charging, the PWM_AL pin outputs an alarm level. When the CP voltage signal returns to normal, the PWM_AL pin outputs a normal level.

[0034] ADC_VO: Analog output. The AC charging pile main control system can monitor the CP voltage value in real time through this pin. When abnormal CP voltage occurs, the system alarms. When the CP voltage returns to normal, the alarm is cleared.

[0035] As attached Figure 2 As shown in the figure: A signal processing module based on AC charging pile CP mainly includes: (1) power supply part, (2) PWM output part, and (3) signal processing part.

[0036] In the power supply part, the external power supply voltage is input into the entrance of the AC charging pile CP signal processing module.

[0037] The PWM output part amplifies the PWM signal input by the main control system and outputs a PWM signal that meets the standard requirements.

[0038] The signal processing part modulates the collected PWM signal and outputs controllable analog and digital TTL level signals.

[0039] A CP signal processing module based on AC charging pile, the specific implementation plan is as follows:

[0040] (1) The power supply section converts the input single power supply voltage into the VPOS and VNEG dual power supply voltages required within the module. The module input voltage range is DC (+3 to +15) V, with a wide input voltage range and strong versatility. Capacitors C3 and C5 connect VIN and GND to store energy and filter. PVIN1, PVIN2, PVINSYS, EN1, and EN2 of the power supply chip U1 are connected to the power input VIN. Capacitor C1 and resistor R2 together form the compensation network of the boost regulation error amplifier and are connected to the COMP1 pin of the power supply chip U1. Capacitor C2 and resistor R4 together form the compensation network of the inverting regulation error amplifier and are connected to the COMP2 pin of the power supply chip U1 (the power supply chip U1 model is ADP5071).

[0041] Capacitor C6 has one end connected to the VREG pin of power chip U1 and the other end connected to GND, providing filtering. The SYNC / FREQ and AGND pins of power chip U1 are connected to GND. Power inductor L1 has one end connected to the INBK pin of power chip U1 and the other end connected to the SW1 pin of power chip U1. Diode D1 has its anode connected to the SW1 pin of power chip U1 and its cathode connected to the module's internal positive power supply, VPOS. Resistor R7 has one end connected to the module's internal positive power supply, VPOS, and the other end connected to the FB1 pin of power chip U1. Resistor R8 has one end connected to the FB1 pin of power chip U1 and the other end connected to GND. The EP and PGND pins of power chip U1 are connected to GND. Capacitor C7 has one end connected to the VREF pin of power chip U1 and the other end connected to GND, providing filtering. Resistor R13 has one end connected to the VREF pin of power chip U1 and the other end connected to the FB2 pin of power chip U1. One end of resistor R14 is connected to pin FB2 of power chip U1, and the other end is connected to the module's internal negative power supply VNEG. The cathode of diode D3 is connected to pin SW2 of power chip U1, and the positive end is connected to the module's internal negative power supply VNEG. One end of power inductor L2 is connected to pin SW2 of power chip U1, and the other end is connected to GND.

[0042] Power inductors L1 and L2 act as filters, while diodes D1 and D3 prevent backflow. Resistors R7 and R8 form the positive power supply output feedback network, while resistors R14 and R13 form the negative power supply output feedback network. In actual designs, VPOS and VNEG should be designed with a margin to allow for a voltage drop of |Vd| ≈ 0.7V for the switching transistor. VPOS = +(12V + Vd)V, and VNEG = -(12V - Vd)V. The specific formulas for calculating the VPOS and VNEG voltages are:

[0043] VPOS = VFB1(1 + R7 / R8); VNEG = VFB2 - (R14 / R13) (VREF - VFB2). The voltage values ​​of VFB1, VFB2, and VREF can be found in the design manual of power supply chip U1.

[0044] (2) In the PWM output section, one end of the current-limiting resistor R26 is connected to the external input PWM signal, and the other end is connected to pin 2 of U3A. Resistors R21 and R24 divide the positive power supply VPOS and input the output voltage to pin 3 of the integrated operational amplifier U3A, providing the threshold voltage for the internal level change of the circuit. Pin 8 of the integrated operational amplifier U3A is connected to the positive power supply VPOS, and pin 4 of the integrated operational amplifier U3A is connected to the negative power supply VNEG. Capacitor C9 is connected across the positive power supply VPOS and negative power supply VNEG to provide filtering. One end of the pull-up resistor R22 is connected to the module's internal positive power supply VPOS, and the other end is connected to pin 1 of the integrated operational amplifier U3A. The collector of transistor Q1 is connected to the module's internal positive power supply VPOS, the base is connected to pin 1 of the integrated operational amplifier U3A, and the emitter is connected to one end of resistor R25. The collector of transistor Q2 is connected to the module's internal negative power supply VNEG, the base is connected to pin 1 of the integrated operational amplifier U3A, and the emitter is connected to one end of resistor R25. The function of the switching tubes Q1 and Q2 in the circuit is to amplify the PWM signal of the input module, modulate it into a controllable PWM voltage signal, and output the controllable PWM voltage signal through the current limiting resistor R25.

[0045] (3) Signal processing: One end of the current-limiting resistor R5 is connected to the CP_OUT signal of the PWM output part, and the other end is connected to the third pin of the integrated operational amplifier U2A. Resistors R10 and R11 divide the positive power supply VPOS and input the voltage signal to the second pin of the integrated operational amplifier U2A, providing the threshold voltage for the internal level change of the circuit. The eighth pin of the integrated operational amplifier U2A is connected to the positive power supply VPOS, and the fourth pin of the integrated operational amplifier U2A is connected to the negative power supply VNEG. Resistors R5, R1 and U2A together form a hysteresis comparator. Due to the effect of feedback, the threshold voltage value of the hysteresis comparator changes with the change of the output voltage, effectively suppressing noise interference and improving the stability of the system. After the output signal of the hysteresis comparator is modulated by the limit value circuit formed by resistors R3, R9, R6 and diode D2, the module outputs a controllable SOC_ACQ signal.

[0046] Similarly, the design principles of the INCPG_DET and PWM_AL signal generation circuits are similar to those of the SOC_ACQ signal generation circuit, and the functions of the functional components are the same, so they will not be described here.

[0047] Resistors R36 and R40 divide the CP voltage signal, and after filtering by capacitor C13, it is passed to the low-pass filter circuit composed of resistors R37, R38, capacitors C10, C14 and U4B. The low-pass filter circuit is an electronic filter circuit that allows signals below the cutoff frequency to pass, but does not allow signals above the cutoff frequency to pass. Its function in the module is to effectively filter out high-frequency interference and retain the signal required by the module. Diode D6 releases the negative voltage in the collected signal to GND. The positive voltage signal passes through the voltage divider filter circuit composed of resistors R34, R39 and capacitor C12 and is input into the second-stage integrated operational amplifier U4A. The first pin of the integrated operational amplifier U4A outputs the analog signal. After voltage division by resistors R33 and R354, it outputs the controllable analog signal ADC_V0.

[0048] Example 2: (1) When the charging pile is in standby mode and the CP voltage is detected to change from 12V to 9V, it is considered that the user has plugged in the charger, and the main control system software controls the monitoring of the level change of the SOC_ACQ pin.

[0049] (2) The monitored pin level changes are parsed into digital signals containing vehicle SOC, VIN code and other information in the form of serial port data with a baud rate of 1000bps.

[0050] (3) The main control system sends the received electric vehicle VIN and other information to the charging control platform for data authentication. If the authentication fails, no other actions are performed and the system waits for the user to start charging. If the authentication succeeds, the AC charging pile sends a PWM signal and waits for the next process to be triggered.

[0051] (4) When the vehicle receives a 9V PWM signal and the self-test is normal, the vehicle S2 switch is controlled to close. At this time, the CP voltage becomes 6V, the charging pile closes the output relay, and enters the energy exchange stage.

[0052] (5) After the electric vehicle is fully charged, the S2 switch is disconnected and the CP voltage changes from 6V to 9V. After waiting for about 5 minutes, the AC charging pile considers that the electric vehicle battery is fully charged and stops sending the PWM signal, thus ending the charging.

[0053] (6) During the standby and charging process of the charging pile, the charging pile detects the voltage signals of the INCPG_DET, PWM_AL, and ADC_VO pins in real time to check whether there is a CP short circuit or abnormal CP voltage. If the above problems occur, the system immediately enters the fault handling process. After the fault is eliminated, it returns to the normal working process.

[0054] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A CP signal processing module based on an AC charging pile, characterized in that: include: A power supply circuit, a PWM output circuit, and a signal processing circuit, wherein the output end of the power supply circuit is connected to the PWM output circuit and the signal processing circuit, and the output end of the PWM output circuit is connected to the signal processing circuit; The power supply circuit is the input of the external power supply voltage into the AC charging pile CP signal processing module, converting the input single power supply voltage into the VPOS and VNEG dual power supply voltages required by the module; The PWM output circuit amplifies the PWM signal input from the main control system and outputs a PWM signal that meets standard requirements; The signal processing circuit modulates the collected PWM signal and outputs controllable analog and digital TTL level signals.

2. The AC charging pile CP signal processing module according to claim 1, characterized in that: The power supply circuit includes a power supply chip U1, and the power supply chip U1 model is ADP5071; PVIN1, PVIN2, PVINSYS, EN1, and EN2 of the power supply chip U1 are connected to the power input terminal VIN, and the power input terminal VIN is also connected to one end of capacitors C3 and C5, and the other end of the capacitors C3 and C5 is connected to the ground terminal GND; the COMP1 pin of the power supply chip U1 is connected to the capacitor C1 and the resistor R2 in series, the COMP2 pin of the power supply chip U1 is connected to the capacitor C2 and the resistor R4 in series, the capacitor C6 is connected between the VREG pin of the power supply chip U1 and the ground terminal GND, the SYNC / FREQ and AGND pins of the power supply chip U1 are connected to the ground terminal GND, the power inductor L1 is connected between the INBK pin and the SW1 pin of the power supply chip U1, and the SW1 pin of the source chip U1 is connected to the ground terminal GND. The pin is connected to the positive pole of diode D1, the negative pole of diode D1 is connected to the internal positive power supply VPOS of the module, resistor R7 is connected between the internal positive power supply VPOS of the module and the FB1 pin of the power supply chip U1, resistor R8 is connected between the FB1 pin of the power supply chip U1 and the ground terminal GND, the EP and PGND pins of the power supply chip U1 are connected to the ground terminal GND, capacitor C7 is connected between the VREF pin of the power supply chip U1 and the ground terminal GND, resistor R13 is connected between the VREF pin of the power supply chip U1 and the FB2 pin, resistor R14 is connected between the FB2 pin of the power supply chip U1 and the internal negative power supply VNEG, the SW2 pin of the power supply chip U1 is connected to the negative pole of diode D3, the positive pole of diode D3 is connected to the internal negative power supply VNEG of the module, and the power inductor L2 is connected between the SW2 pin of the power supply chip U1 and the ground terminal GND.

3. The AC charging pile CP signal processing module according to claim 1, characterized in that: The PWM output circuit includes an integrated operational amplifier U3A, resistors R21, R22, R24, R25, R26, an NPN transistor Q1, a PNP transistor Q2, and a capacitor C9; one end of the resistor R26 is connected to the external input PWM signal, and the other end is connected to the second pin of U3A; the resistors R21 and R24 divide the positive power supply VPOS, and input the output voltage to the third pin of the integrated operational amplifier U3A to provide a threshold voltage for the level change inside the circuit; the eighth pin of the integrated operational amplifier U3A is connected to the positive power supply VPOS, and the fourth pin of the integrated operational amplifier U3A is connected to the negative power supply VPOS. Source VNEG; capacitor C9 is connected across the positive power supply VPOS and the negative power supply VNEG to act as a filter; one end of resistor R22 is connected to the positive power supply VPOS inside the module, and the other end is connected to the first pin of the output end of the integrated operational amplifier U3A; the collector of transistor Q1 is connected to the positive power supply VPOS inside the module, the base is connected to the first pin of the output end of the integrated operational amplifier U3A, and the emitter is connected to one end of resistor R25; the collector of transistor Q2 is connected to the negative power supply VNEG inside the module, the base is connected to the first pin of the output end of the integrated operational amplifier U3A, and the emitter is connected to one end of resistor R25.

4. The AC charging pile CP signal processing module according to claim 1, characterized in that: The signal processing circuit includes a digital signal output signal generating circuit, a CP grounding alarm output signal generating circuit before starting charging, and a CP grounding detection alarm output signal generating circuit during charging. The structures of the three signal generating circuits are the same.

5. The AC charging pile CP signal processing module according to claim 4, characterized in that: The digital signal output signal generating circuit includes an integrated operational amplifier U2A, resistors R1, R3, R5, R6, R9, R10, R11, and a diode D2; one end of the current limiting resistor R5 is connected to the CP_OUT signal output by the PWM output circuit, and the other end is connected to the third pin of the integrated operational amplifier U2A; the resistors R10 and R11 divide the positive power supply VPOS, and input the voltage signal to the second pin of the integrated operational amplifier U2A to provide a threshold voltage for the level change inside the circuit; the eighth pin of the integrated operational amplifier U2A is connected to the positive power supply VPOS, and the fourth pin of the integrated operational amplifier U2A is connected Negative power supply VNEG; a resistor R1 is connected between the third pin of the integrated operational amplifier U2A and the first pin of the output end, and the resistors R5, R1 and U2A together constitute a hysteresis comparator; one end of the resistor R3 is connected to the positive power supply VPOS voltage divider, and the other end of the resistor R3 is connected to one end of the resistor R9 and one end of the resistor R6, the other end of the resistor R9 is grounded, and the other end of the resistor R6 is connected to the cathode of the diode D2, and the anode of the diode D2 is grounded; after the output signal of the hysteresis comparator is modulated by the limit value circuit formed by the resistors R3, R9, R6 and diode D2, the module outputs a controllable SOC_ACQ signal.

6. The AC charging pile CP signal processing module according to claim 1, characterized in that: The output end of the PWM output circuit is also connected to a filter circuit, which includes resistors R33, R34, R35, R36, R37, R38, R39, and R40, integrated operational amplifiers U4A and U4B, a diode D6, and capacitors C10, C12, C13, and C14; wherein the output signal of the PWM output circuit is divided by the series-connected resistors R36 and R40 of the low-pass filter circuit, wherein one end of the resistor R36 is connected to the output signal output end of the PWM output circuit, the other end of the resistor R36 is connected to one end of the resistor R40, the other end of the resistor R40 is grounded, the resistor R40 is connected in parallel with the capacitor C13, the other end of the resistor R36 is connected to the non-inverting end of the integrated operational amplifier U4B through the series-connected resistors R37 and R38, and the resistors R37, R A capacitor C10 is connected between the 38 connection terminal and the inverting terminal of the operational amplifier U4B, a capacitor C14 is connected between the inverting terminal of the integrated operational amplifier U4B and the ground terminal, the inverting terminal of the integrated operational amplifier U4B is connected to the output terminal, the output terminal of the integrated operational amplifier U4B is connected to the positive electrode of the diode D6, the negative electrode of the diode D6 is connected to one end of the resistor R34, the other end of the resistor R34 is connected to the inverting terminal of the integrated operational amplifier U4A, one end of the resistor R39, and one end of the capacitor C12, the other end of the resistor R39 and the other end of the capacitor C12 are grounded, the inverting terminal of the operational amplifier U4A is connected to the output terminal, the output terminal of the operational amplifier U4A is connected to one end of the resistor R33, the other end of the resistor R33 is connected to one end of the resistor R35, and the other end of the resistor R35 is grounded.

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