Digital wake-up low-power-consumption circuit

Abstract

The utility model discloses a digital wake-up low power consumption circuit, specifically relates to battery management technical field, including master controller U5, wake-up circuit, filter acquisition voltage division circuit and trigger circuit, master controller U5 is connected with control power supply, wake-up circuit is connected with microcontroller through EN network, trigger circuit one end is connected with wake-up circuit, and trigger circuit one end is connected with microcontroller. The other end of the trigger circuit is connected with a filtering acquisition voltage division circuit which is close to the power supply anode of the output end of the control power supply. According to the utility model, the microcontroller sends an enable signal to control the input MOS of the power supply, the mos can be completely switched off and the power supply of a post-stage circuit can be cut off through the microcontroller in a static state, so that the static low power consumption is realized, and when the chip is not waken up or does not meet the low power consumption, the microcontroller sends the enable signal to control the power supply. Therefore, the low-power-consumption requirement of the circuit can be met by the circuit without being limited to whether the chip needs to meet the requirement, and the optionality is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of battery management, in particular to a digital wake-up low-power consumption circuit. Background Art

[0002] Outdoor battery packs, often referred to as outdoor power supplies, are becoming increasingly common in everyday travel. They are typically low-voltage, always-on power supplies. For these types of battery packs, it's normal for the charger to wake up the entire pack and charge it. However, in reality, when the charger isn't fully inserted, voltage fluctuations caused by poor contact can cause the pack to activate due to interference. Alternatively, when the battery pack is exposed to complex environments, such as strong electromagnetic interference, fluctuations in the potential difference between the positive and negative terminals can cause the pack to malfunction. This is especially true when the MOSFET is on the high side, where voltage fluctuations at the positive power supply output lead to improper startup. Furthermore, outdoor battery packs are used relatively infrequently and are often stored for extended periods. Not only do they waste energy during extended standby periods, but they also often experience low battery levels when reactivated, hindering their use.

[0003] Typically, existing solutions for low power consumption mainly rely on chips with low power consumption functions or chips with wake-up functions. This is not a wide range of options, and some chips often fail to achieve low power consumption, making them unsuitable for selection. Utility Model Content

[0004] The purpose of the utility model is to provide a digital wake-up low-power circuit to solve the problems raised in the prior art.

[0005] To achieve the above objectives, the present invention provides the following technical solutions:

[0006] A digital wake-up low-power circuit includes a main controller U5, a wake-up circuit, a filtering and collecting voltage divider circuit, and a trigger circuit. The main controller U5 is connected to a control power supply, the wake-up circuit is connected to a microcontroller via an EN network, one end of the trigger circuit is connected to the wake-up circuit, and the other end of the trigger circuit is connected to the filtering and collecting voltage divider circuit. The filtering and collecting voltage divider circuit is close to the positive power supply of the control power supply output end.

[0007] In a preferred embodiment, the wake-up circuit includes a microcontroller U4, one end of which is respectively connected in series with a resistor R34, a resistor R35 and a capacitor C43, one end of the microcontroller U4 is grounded through a resistor R32, the microcontroller U4 is connected to a resistor R39 and a resistor R30, the resistor R39 is connected in series with a capacitor C49 and then grounded, one end of the resistor R39 is connected to a main node, the resistor R30 is connected in parallel with a transformer and a resistor R40, the resistor R30 is connected to a capacitor C46 and a capacitor C47 arranged in parallel, the capacitor C47 is connected to the resistor R40, and a voltage-stabilizing diode group T2 is connected in series between the resistor R40 and the resistor R30.

[0008] In a preferred embodiment, the master node includes a resistor R42 and a resistor R44 connected in parallel, the resistor R42 is connected to the resistor R30, and the resistor R44 is connected to the microcontroller U4.

[0009] In a preferred embodiment, the filtering and collecting voltage divider circuit includes a capacitor C62 and a capacitor C65, a crystal X1 and a resistor R64 are connected between the capacitors C62 and C65, and one end of the resistor R64 is connected to a resistor R63.

[0010] In a preferred embodiment, the trigger circuit includes a bidirectional breakdown diode, a resistor R2 and a capacitor C13 arranged in parallel, and the bidirectional breakdown diode, the resistor R2 and the capacitor C13 are connected in parallel to the bottom line and the diode D1, the diode D1 is connected to the voltage regulator diode D2, the resistor R6 and the PMOS tube Q1 arranged in parallel, one end of the PMOS tube Q1 is connected to the inductor L1 and the capacitor C10, and the capacitor C10 is connected in parallel with the capacitor C11, the capacitor C14, the capacitor C12 and the power supply C9.

[0011] In a preferred embodiment, the voltage stabilizing diode D2, the resistor R6, and the PMOS transistor Q1 are connected in parallel to a resistor R13, one end of the resistor R13 is connected to the PMOS transistor Q2, the PMOS transistor Q2 is provided with a voltage stabilizing diode D6, a resistor R22, and a capacitor C25 in parallel, and the voltage stabilizing diode D6, the resistor R22, and the capacitor C25 are connected in parallel to a resistor R20 and a diode D5.

[0012] Compared with the prior art, the beneficial effects of the present invention are:

[0013] The digital wake-up low-power consumption circuit described in the present invention controls the input MOS of the power supply through a microcontroller sending an enable signal. When in static state, the microcontroller can completely shut down the MOS and cut off the power supply of the subsequent circuit, thereby achieving static low power consumption. In this way, when the chip does not have a wake-up function or does not meet the low power consumption requirements, the microcontroller can send an enable signal to shut down the power supply of the subsequent circuit so that the circuit meets the low power consumption requirements of the circuit. In this way, there is no need to be limited to whether the chip itself meets the requirements, thereby improving the selectivity. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 This is a schematic diagram of the overall circuit structure of the utility model;

[0015] Figure 2 This is a schematic diagram of the structure of the wake-up circuit of the utility model;

[0016] Figure 3 This is a schematic diagram of the structure of the filter collection voltage divider circuit of the utility model;

[0017] Figure 4 It is a structural diagram of the trigger circuit of the utility model. DETAILED DESCRIPTION

[0018] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0019] Example: See Figures 1-4 , the utility model provides a digital wake-up low-power circuit, the technical solution is as follows:

[0020] A digital wake-up low-power circuit includes a main controller U5, a wake-up circuit, a filtering and collecting voltage divider circuit, and a trigger circuit. The main controller U5 is connected to a control power supply, the wake-up circuit is connected to a microcontroller via an EN network, one end of the trigger circuit is connected to the wake-up circuit, and the other end of the trigger circuit is connected to the filtering and collecting voltage divider circuit. The filtering and collecting voltage divider circuit is close to the positive power supply of the control power supply output end.

[0021] In a preferred embodiment, the wake-up circuit includes a microcontroller U4, one end of which is respectively connected in series with a resistor R34, a resistor R35 and a capacitor C43, one end of the microcontroller U4 is grounded through a resistor R32, the microcontroller U4 is connected to a resistor R39 and a resistor R30, the resistor R39 is connected in series with a capacitor C49 and then grounded, one end of the resistor R39 is connected to a main node, the resistor R30 is connected in parallel with a transformer and a resistor R40, the resistor R30 is connected to a capacitor C46 and a capacitor C47 arranged in parallel, the capacitor C47 is connected to the resistor R40, and a voltage stabilizing diode group T2 is connected in series between the resistor R40 and the resistor R30. The wake-up circuit is the enable voltage of the microcontroller U4, so when the enable terminal voltage of the microcontroller U4 reaches the enable voltage, the microcontroller U4 is normally turned on and the battery pack is woken up for charging.

[0022] In a preferred embodiment, the master node includes a resistor R42 and a resistor R44 connected in parallel, the resistor R42 is connected to the resistor R30, and the resistor R44 is connected to the microcontroller U4.

[0023] In a preferred embodiment, the filtering and collecting voltage divider circuit includes a capacitor C62 and a capacitor C65, a crystal X1 and a resistor R64 are connected between the capacitors C62 and C65, and one end of the resistor R64 is connected to a resistor R63.

[0024] In a preferred embodiment, the trigger circuit includes a bidirectional breakdown diode, a resistor R2 and a capacitor C13 arranged in parallel, and the bidirectional breakdown diode, the resistor R2 and the capacitor C13 are connected in parallel to the bottom line and the diode D1, the diode D1 is connected to the voltage regulator diode D2, the resistor R6 and the PMOS tube Q1 arranged in parallel, one end of the PMOS tube Q1 is connected to the inductor L1 and the capacitor C10, and the capacitor C10 is connected in parallel with the capacitor C11, the capacitor C14, the capacitor C12 and the power supply C9.

[0025] In a preferred embodiment, the voltage stabilizing diode D2, the resistor R6, and the PMOS transistor Q1 are connected in parallel to a resistor R13, one end of the resistor R13 is connected to the PMOS transistor Q2, the PMOS transistor Q2 is provided with a voltage stabilizing diode D6, a resistor R22, and a capacitor C25 in parallel, and the voltage stabilizing diode D6, the resistor R22, and the capacitor C25 are connected in parallel to a resistor R20 and a diode D5.

[0026] The working principle of the present invention is as follows: the output signal of the control power supply is collected by the filtering and collecting voltage divider circuit, and is connected to the wake-up circuit after being processed by the trigger circuit. The microcontroller U4 in the wake-up circuit sends an enable signal to control the input MOS of the power supply. When static, the microcontroller can completely shut down the MOS and cut off the power supply of the subsequent circuit, thereby achieving static low power consumption. In this way, when the chip does not have wake-up or does not meet the low power consumption requirements, the microcontroller can send an enable signal to shut down the power supply of the subsequent circuit so that the circuit meets the low power consumption requirements of the circuit. In this way, there is no need to be limited to whether the chip itself meets the requirements, which improves the selectivity.

[0027] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the present invention is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be encompassed within the present invention. Any reference sign in a claim should not be construed as limiting the claim to which it relates.

Claims

1. A digital wake-up low-power circuit, characterized in that: It includes a main controller U5, a wake-up circuit, a filtering and collecting voltage divider circuit and a trigger circuit. The main controller U5 is connected to the control power supply. The wake-up circuit is connected to the microcontroller through the EN network. One end of the trigger circuit is connected to the wake-up circuit, and the other end of the trigger circuit is connected to the filtering and collecting voltage divider circuit. The filtering and collecting voltage divider circuit is close to the positive power supply of the control power supply output end.

2. The digital wake-up low-power circuit according to claim 1, characterized in that: The wake-up circuit includes a microcontroller U4, one end of which is connected in series with a resistor R34, a resistor R35 and a capacitor C43, one end of which is grounded through a resistor R32, the microcontroller U4 is connected to a resistor R39 and a resistor R30, the resistor R39 is connected in series with a capacitor C49 and then grounded, one end of the resistor R39 is connected to a main node, the resistor R30 is connected in parallel with a transformer and a resistor R40, the resistor R30 is connected to a capacitor C46 and a capacitor C47 arranged in parallel, the capacitor C47 is connected to the resistor R40, and a voltage-stabilizing diode group T2 is connected in series between the resistor R40 and the resistor R30.

3. The digital wake-up low-power circuit according to claim 2, characterized in that: The master node includes a resistor R42 and a resistor R44 connected in parallel. The resistor R42 is connected to the resistor R30, and the resistor R44 is connected to the microcontroller U4.

4. The digital wake-up low-power circuit according to claim 1, characterized in that: The filtering, collecting and voltage-dividing circuit includes a capacitor C62 and a capacitor C65 , a crystal X1 and a resistor R64 are connected between the capacitors C62 and C65 , and one end of the resistor R64 is connected to a resistor R63 .

5. The digital wake-up low-power circuit according to claim 1, characterized in that: The trigger circuit includes a bidirectional breakdown diode, a resistor R2, and a capacitor C13 arranged in parallel, and the bidirectional breakdown diode, resistor R2, and capacitor C13 are connected in parallel to the bottom line and the diode D1. The diode D1 is connected to the voltage regulator diode D2, the resistor R6, and the PMOS tube Q1 arranged in parallel. One end of the PMOS tube Q1 is connected to the inductor L1 and the capacitor C10. The capacitor C10 is connected in parallel with the capacitor C11, the capacitor C14, the capacitor C12, and the power supply C9.

6. The digital wake-up low-power circuit according to claim 5, characterized in that: The voltage stabilizing diode D2, the resistor R6, and the PMOS transistor Q1 are connected in parallel to a resistor R13. One end of the resistor R13 is connected to the PMOS transistor Q2. The PMOS transistor Q2 is provided with a voltage stabilizing diode D6, a resistor R22, and a capacitor C25 in parallel. The voltage stabilizing diode D6, the resistor R22, and the capacitor C25 are connected in parallel to a resistor R20 and a diode D5.

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