Quasi-super junction trench gate silicon carbide VDMOS

Abstract

The utility model provides a quasi-super junction trench gate silicon carbide VDMOS, which comprises a drift layer connected to a silicon carbide substrate, and a plurality of N-type regions uniformly arranged at intervals at the lower part of the drift layer; a plurality of P-type masking regions are uniformly arranged at the upper part of the drift layer at intervals, each N-type region is connected to the silicon carbide substrate, and a groove is formed in the drift layer; the P-type well region is connected to the drift layer and the P-type masking region, an N-type source region and a P-type source region are arranged in the P-type well region, and the P-type source region is connected to the N-type source region; the lower part of the gate dielectric layer is arranged in the groove, and the gate dielectric layer is respectively connected with the drift layer and the P-type masking region; the outer side surface of the gate dielectric layer is respectively connected with the inner side surface of the P-type well region and the inner side surface of the N-type source region; a groove is formed in the gate dielectric layer; the gate metal layer is arranged in the groove; the source metal layer is respectively connected with the P-type well region, the P-type source region and the N-type source region; the drain metal layer is connected to the silicon carbide substrate, so that the voltage endurance capability of the device is improved, and the on-resistance of the device is reduced.

Description

Technical Field

[0001] The utility model relates to a quasi-super junction trench gate silicon carbide VDMOS. Background Art

[0002] As a prominent representative of SiC power devices, the SiC vertical bipolar metal-oxide-semiconductor field-effect transistor (VDMOS) plays a vital role in a variety of fields, including electric vehicles, aerospace, and power conversion. Different applications place varying emphasis on the performance requirements of SiC power MOSFETs, but generally, they all pursue the following characteristics: higher voltage withstand capability to cope with extreme voltage conditions; lower on-resistance to reduce energy loss; faster switching speeds to improve efficiency; higher reliability, including gate stability, tolerance to drain voltage surges, and robustness under short-circuit conditions; and lower body diode conduction losses to optimize overall energy efficiency. These comprehensive performance improvements are the technical goals that SiC power MOSFETs are constantly pursuing. Utility Model Content

[0003] The technical problem to be solved by the present invention is to provide a quasi-superjunction trench gate silicon carbide VDMOS, in which an N-type region and a masking region are constructed inside the device, thereby forming a horizontally and vertically combined quasi-superjunction voltage-resistant structure to improve the voltage-resistant capability of the device. At the same time, the N-type region can reduce the on-resistance of the device.

[0004] The utility model provides a quasi-superjunction trench gate silicon carbide VDMOS, comprising:

[0005] Silicon carbide substrate,

[0006] A drift layer, wherein the lower side of the drift layer is connected to the upper side of the silicon carbide substrate, a plurality of N-type regions are evenly spaced at the lower portion of the drift layer; a plurality of P-type masking regions are evenly spaced at the upper portion of the drift layer, the lower side of each N-type region is connected to the upper side of the silicon carbide substrate, and a groove is provided on the drift layer;

[0007] A P-type well region, wherein the lower side of the P-type well region is connected to the upper side of the drift layer and the upper side of the P-type masking region, an N-type source region and a P-type source region are provided in the P-type well region, and the P-type source region is connected to the N-type source region;

[0008] a gate dielectric layer, wherein the lower portion of the gate dielectric layer is disposed in the groove, the lower side surface of the gate dielectric layer is respectively connected to the upper side surface of the drift layer and the upper side surface of the P-type shielding region; the outer side surface of the gate dielectric layer is respectively connected to the inner side surface of the P-type well region and the inner side surface of the N-type source region; and a trench is provided in the gate dielectric layer;

[0009] a gate metal layer, the gate metal layer being disposed in the trench;

[0010] a source metal layer, the source metal layer being connected to the P-type well region, the P-type source region, and the N-type source region respectively;

[0011] and a drain metal layer connected to the lower side of the silicon carbide substrate.

[0012] The advantages of the present invention are:

[0013] 1. Optimization of the voltage-withstand structure: By constructing an N-type region and a P-type masking region, the traditional device's vertical pn junction voltage-withstand structure is transformed into a structure where both vertical and lateral pn junctions share the voltage-withstand structure. This design effectively improves the device's voltage-withstand capability while maintaining the silicon wafer thickness and lateral conditions, achieving a quasi-superjunction structure and thus enhancing the device's electrical performance.

[0014] 2. Reduced on-resistance: The N-type region in the trench gate structure not only transforms the device's voltage-withstand structure but also successfully reduces the device's on-resistance by appropriately increasing the doping concentration of the N-type drift layer. This improvement helps improve device energy efficiency and reduce energy loss.

[0015] 3. Enhanced Gate Reliability: While constructing a quasi-superjunction structure, the device's P-type shielding region also features a specially designed structure located at the gate corner at the bottom of the trench gate. This design effectively addresses gate reliability issues caused by electric field concentration, consistently improving electrical performance at the bottom of the trench gate and thus enhancing overall device reliability.

[0016] The trench gate device of the utility model achieves a dual improvement in voltage resistance and conduction performance while maintaining a compact structure, providing a more reliable solution for the application of high-voltage power devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0018] Figure 1 This is a schematic diagram of a quasi-superjunction trench gate silicon carbide VDMOS according to the present invention.

[0019] Figure 2 This is a cross-sectional view of the process of a quasi-superjunction trench gate silicon carbide VDMOS in this utility model. Figure 1 .

[0020] Figure 3 This is a cross-sectional view of the process of a quasi-superjunction trench gate silicon carbide VDMOS in this utility model. Figure 2 .

[0021] Figure 4 This is a cross-sectional view of the process of a quasi-superjunction trench gate silicon carbide VDMOS in this utility model. Figure 3 .

[0022] Figure 5 This is a cross-sectional view of the process of a quasi-superjunction trench gate silicon carbide VDMOS in this utility model. Figure 4 .

[0023] Figure 6 This is a cross-sectional view of the process of a quasi-superjunction trench gate silicon carbide VDMOS in this utility model. Figure 5 .

[0024] Figure 7 This is a cross-sectional view of the process of a quasi-superjunction trench gate silicon carbide VDMOS in this utility model. Figure 6 .

[0025] Figure 8 This is a cross-sectional view of the process of a quasi-superjunction trench gate silicon carbide VDMOS in this utility model. Figure 7 .

[0026] Figure 9 This is a cross-sectional view of the process of a quasi-superjunction trench gate silicon carbide VDMOS in this utility model. Figure 8 .

[0027] Figure 10 This is a cross-sectional view of the process of a quasi-superjunction trench gate silicon carbide VDMOS in this utility model. Figure 9 .

[0028] Figure 11 This is a cross-sectional view of the process of a quasi-superjunction trench gate silicon carbide VDMOS in this utility model. Figure 10 .

[0029] Figure 12 This is a cross-sectional view of the process of a quasi-superjunction trench gate silicon carbide VDMOS in this utility model. Figure 10 one. DETAILED DESCRIPTION

[0030] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0032] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "in contact with," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion.

[0033] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of one element or feature to other elements or features depicted in the figures. It should be understood that, in addition to the orientations depicted in the figures, spatially relative terms also encompass different orientations of the device in use and operation. For example, if the device in the figures is flipped over, an element or feature described as "under" or "beneath" or "beneath" the other elements would be oriented "over" the other elements or features. Thus, the exemplary terms "under" and "under" may encompass both the upper and lower orientations. Additionally, the device may also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0034] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0035] like Figure 1 As shown, the embodiment of the present application provides a quasi-superjunction trench gate silicon carbide VDMOS, including:

[0036] Silicon carbide substrate 1,

[0037] A drift layer 2, wherein the lower side of the drift layer 2 is connected to the upper side of the silicon carbide substrate 1, and a plurality of N-type regions 21 are evenly spaced apart at the lower portion of the drift layer 2; a plurality of P-type masking regions 22 are evenly spaced apart at the upper portion of the drift layer 2, and the lower side of each N-type region 21 is connected to the upper side of the silicon carbide substrate 1; and a groove 23 is provided on the drift layer 2;

[0038] A P-type well region 3, wherein the lower side of the P-type well region 3 is connected to the upper side of the drift layer 2 and the upper side of the P-type masking region 22, and an N-type source region 31 and a P-type source region 32 are provided in the P-type well region 3, and the P-type source region 32 is connected to the N-type source region 31;

[0039] a gate dielectric layer 4, wherein the lower portion of the gate dielectric layer 4 is disposed within the recess 23, the lower side of the gate dielectric layer 4 being connected to the upper side of the drift layer 2 and the upper side of the P-type shielding region 22; the outer side of the gate dielectric layer 4 being connected to the inner side of the P-type well region 3 and the inner side of the N-type source region 31; and a trench 41 being disposed within the gate dielectric layer 4;

[0040] a gate metal layer 5 , the gate metal layer 5 being disposed in the trench 41 ;

[0041] A source metal layer 6 , wherein the source metal layer 5 is connected to the P-type well region 3 , the P-type source region 32 , and the N-type source region 31 ;

[0042] and a drain metal layer 7 , wherein the drain metal layer 7 is connected to the lower side of the silicon carbide substrate 1 .

[0043] In this embodiment, preferably, the P-type masking regions 22 are not located directly above the N-type regions 21, the lower side surface of each P-type masking region 22 and the upper side surface of each N-type region 21 are located in the same plane, and the doping concentrations of the P-type masking regions 22 and the N-type regions 21 are both greater than the doping concentration of the drift layer 2.

[0044] In this embodiment, preferably, the number of the P-type masking regions 22 is 4, wherein the upper side surfaces of two P-type masking regions 22 are connected to the lower side surface of the P-type well region 3, and the upper side surfaces of the other two P-type masking regions 22 are connected to the lower side surface of the gate dielectric layer 4, and these two P-type masking regions 22 are located on both sides of the bottom of the gate dielectric layer 4.

[0045] In this embodiment, preferably, the thickness of the N-type region 21 is 60%-80% of the thickness of the drift layer 2; the thickness of the P-type masking region 22 is 20%-40% of the thickness of the drift layer 2; and the sum of the thickness of the N-type region 21 and the thickness of the P-type masking region 22 is equal to the thickness of the drift layer 2.

[0046] In this embodiment, preferably, the thickness of the bottom of the gate dielectric layer 4 is less than or equal to the depth of the groove 23 .

[0047] like Figures 1 to 12 As shown, the method for preparing the silicon carbide VDMOS comprises the following steps:

[0048] Step 1: Deposit metal on the lower side of the silicon carbide substrate 1 to form a drain metal layer 7; and perform epitaxial growth on the upper side of the silicon carbide substrate 1 to form a drift layer 2;

[0049] Step 2: forming a barrier layer 8 above the drift layer 2, etching the barrier layer 8 to form through holes, and performing ion implantation into the drift layer 2 to form a plurality of N-type regions 21;

[0050] Step 3: remove the original barrier layer 8, re-form the barrier layer 8, etch the barrier layer 8 to form through holes, and perform ion implantation into the drift layer 2 to form a plurality of P-type masking regions 22;

[0051] Step 4: remove the original barrier layer 8, re-form the barrier layer 8, etch the barrier layer 8 to form a through hole, and perform ion implantation into the drift layer 2 to form a P-type well region 3. The ion implantation energy is 70-170 keV.

[0052] Step 5: remove the original barrier layer 8, re-form the barrier layer 8, etch the barrier layer 8 to form a through hole, and perform ion implantation into the P-type well region 3 to form an N-type source region 31. The ion implantation energy is 70-130 keV.

[0053] Step 6: remove the original barrier layer 8, re-form the barrier layer 8, etch the barrier layer 8 to form a through hole, and perform ion implantation into the P-type well region 3 to form a P-type source region 32. The ion implantation energy is 70-130 keV.

[0054] Step 7: removing the original barrier layer 8, re-forming the barrier layer 8, etching the barrier layer 8 to form a through hole, etching the drift layer 2 to form a groove 23, and oxidizing to form a gate dielectric layer 4, wherein the gate dielectric layer 4 is provided with a trench 41;

[0055] Step 8: removing the original barrier layer 8, re-forming the barrier layer 8, etching the barrier layer 8 to form a through hole, and depositing metal into the trench 41 to form a gate metal layer 5;

[0056] Step 9: remove the original barrier layer 8, re-form the barrier layer 8, etch the barrier layer 8 to form a through hole, etch the drift layer 2 to the upper side of the P-type well region 3, deposit metal to form a source metal layer 6, remove the barrier layer 8, and complete the preparation.

[0057] In another embodiment of the present invention, the silicon carbide substrate 1 and the drift layer 2 are both N-type; the doping concentration of the N-type silicon carbide substrate 1 is 2-8e18cm -3 , the doping concentration of the N-type drift layer 2 is 1-5e17cm -3, the doping concentration of the N-type region 21 is 0.8-1.2e18cm -3 The doping concentration of the P-type masking region 22 is 1-5e18cm -3 , the doping concentration of the P-type well region 3 is 1-3e17 cm -3 The gate dielectric layer is silicon dioxide, and the doping concentration of the N-type source region 31 is 2-8e18cm -3 , the doping concentration of the P-type source region 32 is 6-1.2e19cm -3 ; The concentration of the N-type silicon carbide substrate 1 is to ensure the formation of a low-resistance ohmic contact with the drain metal layer 7, thereby reducing the overall on-resistance of the device; the doping concentration of the N-type drift layer 2 is a compromise between the reverse withstand voltage and on-resistance of the device; the doping concentration of the N-type region 21 is to lead the potential of the silicon carbide substrate 1 upward to realize the quasi-superjunction structure of the device; the doping concentration of the P-type masking region 22 is to form a quasi-superjunction structure with the N-type region 21, thereby improving the withstand voltage of the device; the P-type well region 3 is to form the longitudinal withstand voltage structure of the device and the gate control structure of the device; the N-type source region 31 and the P-type source region 32 are to form a low-resistance ohmic contact with the source metal layer 6.

[0058] The thickness of the N-type silicon carbide substrate 1 of the device is 1 μm, and the thickness of the N-type drift layer 2 is 10-30 μm. The thickness is adjusted within the above range according to the different requirements for the withstand voltage characteristics of the device. The thickness of the N-type region 21 is 60%-80% of the thickness of the N-type drift layer 2, and the thickness of the P-type masking region 22 is 20%-40% of the thickness of the N-type drift layer 2 (under this thickness condition, a gate structure thickness of 600 nm needs to be reserved). The thickness of the N-type source region 31 and the P-type source region 32 is 200 nm, and the P-type well region 3 is 200 nm. The thickness below the N-type source region 31 and the P-type source region 32 is 100nm, the thickness of the P-type well region 3 is 300nm, the thickness of the bottom of the gate dielectric layer 4 is 50nm, the thickness of the source metal layer 6 is 200nm, and the thickness of the gate metal layer 5 is 550nm; the thickness of the N-type silicon carbide substrate 1 is to form an effective support for the device structure, the N-type drift layer 2 is the main longitudinal voltage-resistant structure of the device, and its thickness directly affects the voltage-resistant capability of the device, the N-type region 21 and the P-type masking region 22 are to form The lateral voltage-withstand structure of the device is formed, and the bottom of the N-type region 21 and the top of the P-type masking region 22 are designed to be at the same height. Due to the error caused by the process, the error shall not exceed 100nm. The P-type well region 3 is to realize the gate control structure of the device while minimizing the impact on the on-resistance of the device; the N-type region 21 and the P-type masking region 22 are constructed in the trench gate device, and the longitudinal pn junction voltage-withstand structure of the traditional device can be converted into a longitudinal pn junction and a transverse pn junction voltage-withstand structure, so that the voltage-withstand capability of the device can be improved under the same thickness and the same lateral conditions, and a quasi-superjunction structure can be realized. In addition to converting the voltage-withstand structure of the device, the N-type region 21 in the trench gate structure can also reduce the on-resistance of the device by partially increasing the doping concentration of the N-type drift layer 2. In addition to constructing the quasi-superjunction structure, the P-type masking region 22 of the device also deliberately sets part of the structure at the gate corner at the bottom of the trench gate, which can solve the gate reliability problem caused by the electric field concentration at the bottom of the trench gate.

[0059] Although the specific implementation methods of the present invention are described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A quasi-superjunction trench gate silicon carbide VDMOS, characterized in that: include: Silicon carbide substrate, A drift layer, wherein the lower side of the drift layer is connected to the upper side of the silicon carbide substrate, a plurality of N-type regions are evenly spaced at the lower portion of the drift layer; a plurality of P-type masking regions are evenly spaced at the upper portion of the drift layer, the lower side of each N-type region is connected to the upper side of the silicon carbide substrate, and a groove is provided on the drift layer; A P-type well region, wherein the lower side of the P-type well region is connected to the upper side of the drift layer and the upper side of the P-type masking region, an N-type source region and a P-type source region are provided in the P-type well region, and the P-type source region is connected to the N-type source region; a gate dielectric layer, wherein the lower portion of the gate dielectric layer is disposed in the groove, the lower side surface of the gate dielectric layer is respectively connected to the upper side surface of the drift layer and the upper side surface of the P-type shielding region; the outer side surface of the gate dielectric layer is respectively connected to the inner side surface of the P-type well region and the inner side surface of the N-type source region; and a trench is provided in the gate dielectric layer; a gate metal layer, the gate metal layer being disposed in the trench; a source metal layer, the source metal layer being connected to the P-type well region, the P-type source region, and the N-type source region respectively; and a drain metal layer connected to the lower side of the silicon carbide substrate.

2. The quasi-superjunction trench gate silicon carbide VDMOS according to claim 1, wherein: The P-type shielding regions are not located directly above the N-type regions, and the lower side surface of each P-type shielding region and the upper side surface of each N-type region are located in the same plane.

3. The quasi-superjunction trench gate silicon carbide VDMOS according to claim 1, wherein: The doping concentrations of the P-type shielding region and the N-type region are both greater than the doping concentration of the drift layer.

4. The quasi-superjunction trench gate silicon carbide VDMOS according to claim 1, wherein: There are four P-type masking regions, of which the upper side surfaces of two P-type masking regions are connected to the lower side surface of the P-type well region, and the upper side surfaces of the other two P-type masking regions are connected to the lower side surface of the gate dielectric layer, and these two P-type masking regions are located on both sides of the bottom of the gate dielectric layer.

5. The quasi-superjunction trench gate silicon carbide VDMOS according to claim 1, wherein: The thickness of the N-type region is 60%-80% of the thickness of the drift layer; the thickness of the P-type shielding region is 20%-40% of the thickness of the drift layer; the sum of the thickness of the N-type region and the thickness of the P-type shielding region is equal to the thickness of the drift layer.

6. The quasi-superjunction trench gate silicon carbide VDMOS according to claim 1, wherein: The thickness of the bottom of the gate dielectric layer is less than or equal to the depth of the groove.

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