Signal receiving device, analog-digital hybrid test board card and test machine

Abstract

The utility model relates to a signal receiving device, an analog-digital hybrid test board card and a test machine. The signal receiving device comprises a digital waveform collector, a waveform receiving module, an external clock chip and a storage module, the external clock chip is connected with the analog-to-digital conversion device, the digital waveform collector is connected with the analog-to-digital conversion device and the waveform receiving module, and the waveform receiving module is connected with the storage module; the external clock chip outputs a sampling clock with a fixed frequency to the analog-to-digital conversion device; the digital waveform collector receives the original waveform with the fixed frequency output by the analog-to-digital conversion device according to the sampling clock, outputs the required reconstructed waveform of any clock and sends the reconstructed waveform to the waveform receiving module; and the waveform receiving module stores the received reconstructed waveform into the storage module. A required reconstructed waveform with any frequency can be generated by resampling an original waveform with a fixed frequency, analog-to-digital conversion can be completed by outputting a sampling clock with a fixed frequency to an analog-to-digital conversion device by an external clock chip, and the frequency of the sampling clock does not need to be adjusted by the external clock chip; and the hardware requirements on the external clock chip and the analog-to-digital conversion device are low, and the design cost is reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor testing technology, and in particular to a signal receiving device, an analog-digital hybrid testing board, and a testing machine. Background Art

[0002] Semiconductor automated testing refers to the use of automatic test equipment (ATE) to inspect various parameters of devices under test (DUTs), eliminating defective products and ensuring the quality of semiconductor devices before they leave the factory. In analog testing, especially high-speed analog testing, the test signals transmitted to the DUT often have very high requirements for harmonics, signal-to-noise ratio, amplitude, and signal frequency. When implementing IQ functions, the tester must ensure IQ channel synchronization.

[0003] Traditional test signal reception schemes synchronize the IQ channels by changing the frequency of the clock signal output by the clock circuit, thereby adjusting the sampling clock phase of the ADC (analog-to-digital converter) in the IQ channels. This method of receiving test signals by adjusting the ADC sampling clock phase places very high demands on the hardware of the clock circuit, resulting in a complex and costly design. Utility Model Content

[0004] Based on this, it is necessary to provide a signal receiving device, an analog-digital hybrid test board and a test machine that can reduce design costs in order to address the above problems.

[0005] In a first aspect, the present application provides a signal receiving device, comprising: a digital waveform collector, a waveform receiving module, an external clock chip, and a storage module; the external clock chip is connected to an analog-to-digital conversion device, the digital waveform collector is connected to the analog-to-digital conversion device and the waveform receiving module, and the waveform receiving module is connected to the storage module;

[0006] The external clock chip outputs a sampling clock of a fixed frequency to the analog-to-digital conversion device; the digital waveform collector receives the original waveform of the fixed frequency output by the analog-to-digital conversion device according to the sampling clock, outputs the reconstructed waveform of the required arbitrary clock and sends it to the waveform receiving module; the waveform receiving module stores the received reconstructed waveform in the storage module.

[0007] In one embodiment, the waveform receiving module includes:

[0008] A receiving control module, connected to the digital waveform collector and the read-write control module, receives the reconstructed waveform, and sends a write request instruction to the read-write control module;

[0009] The read-write control module is connected to the storage module and stores the reconstructed waveform into the storage module according to the write request instruction.

[0010] In one embodiment, the read / write control module is connected to the storage module via an Avalon interface.

[0011] In one embodiment, the digital waveform collector includes:

[0012] a synchronization control module connected to the waveform data processing module and the analog-to-digital conversion device, configured to receive the original waveform of a fixed frequency output by the analog-to-digital conversion device, and send the original waveform to the waveform data processing module after receiving a trigger signal;

[0013] The waveform data processing module is connected to the waveform receiving module, receives the original waveform, and outputs a required reconstructed waveform of any frequency to the waveform receiving module.

[0014] In one embodiment, the synchronization control module includes:

[0015] A synchronous receiving control module, connected to the acquisition signal processing module and two or more analog-to-digital conversion devices, receives the original waveforms output by each of the analog-to-digital conversion devices, and synchronously sends multiple original waveforms to the acquisition signal processing module after receiving a trigger signal;

[0016] The acquisition signal processing module is connected to the waveform data processing module, synthesizes the received multiple original waveforms, and outputs one original waveform to the waveform data processing module.

[0017] In one embodiment, the synchronous receiving control module is connected to the analog-to-digital conversion device via an LVDS interface to receive the original waveform.

[0018] In one embodiment, the signal receiving device further includes:

[0019] The service decoding module is connected to the digital waveform collector, the waveform receiving module and the external clock chip, configures parameters of the digital waveform collector, the waveform receiving module and the external clock chip, and performs waveform reading operations on the storage module through the waveform receiving module.

[0020] In one embodiment, the external clock chip is a PLL clock chip, and / or the storage module is a DDR storage module.

[0021] A second aspect of the present application provides an analog-digital hybrid test board, comprising the above-mentioned signal receiving device.

[0022] A third aspect of the present application provides a test machine, comprising a communication board, a backplane and the above-mentioned analog-digital hybrid test board.

[0023] In the above-mentioned signal receiving device, analog-to-digital hybrid test board, and tester, an external clock chip outputs a fixed-frequency sampling clock to an analog-to-digital conversion device; a digital waveform collector receives the original waveform with a fixed frequency output by the analog-to-digital conversion device according to the sampling clock, outputs a desired reconstructed waveform with an arbitrary clock, and sends it to a waveform receiving module; the waveform receiving module stores the received reconstructed waveform in a storage module. The desired reconstructed waveform with an arbitrary frequency can be generated by resampling the original waveform with a fixed frequency. The external clock chip outputs the fixed-frequency sampling clock to the analog-to-digital conversion device to complete analog-to-digital conversion. There is no need for the external clock chip to adjust the sampling clock frequency, and the hardware requirements for the external clock chip and the analog-to-digital conversion device are low, reducing design costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a structural block diagram of a signal receiving device in one embodiment;

[0025] Figure 2 FIG. 1 is a schematic structural diagram of a signal receiving device in one embodiment. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0028] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if there is transmission of electrical signals or data between the connected circuits, modules, units, etc.

[0029] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, components, parts, or combinations thereof. Furthermore, the term "and / or" as used in this specification includes any and all combinations of the relevant listed items.

[0030] In one embodiment, Figure 1 As shown, a signal receiving device is provided, comprising: a digital waveform collector 110, a waveform receiving module 120, an external clock chip 130, and a storage module 150. It may further include an analog-to-digital converter (ADC) 140. The external clock chip 130 is connected to the ADC 140, the digital waveform collector 110 is connected to the ADC 140 and the waveform receiving module 120, and the waveform receiving module 120 is connected to the storage module 150. The external clock chip 130 outputs a fixed-frequency sampling clock to the ADC 140. The digital waveform collector 110 receives the original waveform with a fixed frequency output by the ADC 140 based on the sampling clock, outputs a reconstructed waveform with a desired arbitrary clock, and sends it to the waveform receiving module 120. The waveform receiving module 120 stores the received reconstructed waveform in the storage module 150. Furthermore, the external clock chip 130 is also connected to the digital waveform collector 110, outputting a fixed-frequency sampling clock to the digital waveform collector 110, and the digital waveform collector 110 receives waveforms based on the sampling clock.

[0031] Among them, the user can set the parameters of the digital waveform collector 110 according to the actual scenario needs, so that the digital waveform collector 110 resamples the original waveform and generates a reconstructed waveform of any desired frequency. The arbitrary frequency set by the user is less than or equal to the frequency of the sampling clock. The external clock chip 130 can be a PLL (Phase Locked Loop) clock chip, and the storage module 150 can be a DDR (Double Data Rate) storage module composed of DDR4 particles. After receiving the analog waveform output by the device under test, the analog-to-digital conversion device 140 performs analog-to-digital conversion and sampling on the analog waveform according to a fixed-frequency sampling clock, generates an original waveform and sends it to the digital waveform collector 110. The digital waveform collector 110 processes the original waveform and generates a reconstructed waveform of any desired frequency. The device under test can be a semiconductor chip or other device. The number of analog-to-digital conversion devices 140 can be one or more. For example, for the IQ channels of the test machine, a single or multiple analog-to-digital conversion devices 140 can be set corresponding to each channel to receive the analog waveform output by the device under test and perform analog-to-digital conversion on the analog waveform based on the sampling clock.

[0032] like Figure 2As shown, the digital waveform collector 110 may include a synchronization control module 112 and a waveform data processing module 114. The synchronization control module 112 is connected to the waveform data processing module 114 and the analog-to-digital conversion device 140, and is used to receive the original waveform of a fixed frequency output by the analog-to-digital conversion device 140 and send the original waveform to the waveform data processing module 114 after receiving a trigger signal. The waveform data processing module 114 is connected to the waveform receiving module 120, receives the original waveform, and outputs a reconstructed waveform of any desired frequency to the waveform receiving module 120. Furthermore, the signal receiving device may also include a service decoding module 160. The service decoding module 160 is connected to the digital waveform collector 110, the waveform receiving module 120, and the external clock chip 130, and configures parameters of the digital waveform collector 110, the waveform receiving module 120, and the external clock chip 130 according to instructions issued by the host computer, and performs waveform reading operations on the storage module 150 through the waveform receiving module 120.

[0033] The digital waveform collector 110, waveform receiving module 120, and service decoding module 160 can be located within an FPGA (Field-Programmable Gate Array), while the external clock chip 130, analog-to-digital converter 140, and storage module 150 are located outside the FPGA. Port PLL_CTRL of the service decoding module 160 is connected to the external clock chip 130 via an SPI (Serial Peripheral Interface) interface. Parameters are configured for the external clock chip 130 so that it outputs a fixed-frequency sampling clock to the analog-to-digital converter 140. This can be configured to output the sampling clock at the maximum allowable frequency (e.g., 200 MHz) or at another frequency. Port DTG_CTRL of the service decoding module 160 is connected to the synchronization control module 112 and the waveform data processing module 114 for parameter configuration. The port DTG_CTRL and the port DDR_RQE of the service decoding module 160 are connected to the waveform receiving module 120 to perform parameter configuration and waveform reading operations.

[0034] Continue to refer to Figure 2The synchronous control module 112 includes a synchronous receiving control module 1122 and an acquisition signal processing module 1124. The synchronous receiving control module 1122 is connected to the acquisition signal processing module 1124 and more than two analog-to-digital conversion devices 140, receives the original waveforms output by each analog-to-digital conversion device 140, and synchronously sends multiple original waveforms to the acquisition signal processing module 1124 after receiving the trigger signal; the acquisition signal processing module 1124 is connected to the waveform data processing module 114, synthesizes the received multiple original waveforms, and outputs one original waveform to the waveform data processing module 114.

[0035] Taking the test machine as an example, each channel is equipped with two ADC chips. An acquisition signal processing module 1124 and a waveform data processing module 114 can be configured for each IQ channel. The synchronous reception control module 1122 receives two raw waveforms from each channel via an LVDS (Low-Voltage Differential Signaling) interface and buffers them in an internal FIFO (First Input First Output) buffer. Upon receiving a trigger signal TRIG from the service decoding module 160, the synchronous reception control module 1122 outputs the two raw waveforms from the same channel in the internal FIFO buffer to the corresponding acquisition signal processing module 1124. The acquisition signal processing module 1124 synthesizes the two raw waveforms from the same channel into one raw waveform, which is then output to the waveform data processing module 114. By synthesizing the two raw waveforms into one I / Q channel raw waveform, the impact of noise can be reduced and the SNR indicator improved. The waveform data processing module 114 performs digital signal processing, such as AC (alternating current) calibration, DC (direct current) calibration, resampling control, low-pass filtering, etc., according to the instructions issued by the service decoding module 160 (such as the DTG_Digital_CTRL_SIGNAL instruction), and generates a reconstructed waveform of the required frequency and sends it to the waveform receiving module 120.

[0036] Continue to refer to Figure 2 The sampling clock of the four ADC chips in the IQ channel is set to a fixed maximum sampling clock (200MHz). However, the user requires a waveform of arbitrary frequency. In this case, the waveform data processing module 114 is required to resample the original waveform sampled at a fixed frequency. During the resampling process, the initial phase of the reconstructed waveform generated by the resampling can be changed by setting the initial phase, realizing the arbitrary frequency and arbitrary phase adjustment function of the IQ channel. Using ordinary ADC chips can realize the IQ function and the functions of the two non-IQ channels at the same time, eliminating the need for an external clock chip 130 to adjust the sampling clock frequency, simplifying the operation and improving test efficiency.

[0037] Furthermore, the synchronous reception control module 1122 simultaneously collects the original waveform and accompanying clock data_clk output by the analog-to-digital conversion device 140 according to the sampling clock, ensuring synchronization of the output sampled data. Taking the test machine with dual IQ channels as an example, the sampling clocks input to the two ADC chips in each channel are provided by the external clock chip 130. Simultaneously, the external clock chip 130 also transmits the sampling clocks to the synchronous reception control module 1122. Therefore, the sampling clock input to the synchronous reception control module 1122 is co-sourced and co-frequency with the sampling clocks of the four ADC chips. The synchronous reception control module 1122 can use the input sampling clocks to simultaneously perform digital sampling on the four ADC chips.

[0038] Because the ADC chip output data is output using DDR dual-edge sampling, the synchronous reception control module 1122 uses the sampling clock input by the external clock chip 130 to simultaneously sample the original waveforms and the associated clock data_clk output by the four ADC chips. The dual-edge sampling results of the ADC data are determined based on the sampling results of each ADC chip's associated clock data_clk. When the ADC's associated clock data_clk is high, the ADC data is sampled using odd-numbered samples; otherwise, the ADC data is sampled using even-numbered samples. After obtaining the sampled data results from the four ADC chips, the synchronous reception control module 1122 arranges the four 16-bit sampled data into 64-bit data in channel order and writes it into the cross-clock domain buffer FIFO using the input sampling clock as the write clock. Once the cross-clock buffer FIFO is not empty, the synchronous reception control module 1122 uses the system clock as the read clock to read the data from the buffer, completing the cross-clock domain conversion operation. After the cross-clock domain conversion to the system clock, data synchronization control of the four ADC chips is maintained.

[0039] After obtaining the data from the four ADCs based on the system clock, the synchronous receiving control module 1122 divides the 64-bit data into four 16-bit data according to the channel order, and then the acquisition signal processing module 1124 combines the data of ADC0 and ADC1 of channel I into one channel of data, and combines the data of ADC0 and ADC1 of channel Q into one channel of data. The two channels of data of channel I are directly added together, and the two channels of data of channel Q are directly added together. At this time, the synchronous acquisition control of the I and Q channel data is completed.

[0040] Among them, after receiving the trigger signal TRIG sent by the business decoding module 160, the synchronous reception control module 1122 determines whether the working mode issued by the business decoding module 160 is the IQ mode. If it is the IQ mode, as long as the trigger signal TRIG of one of the IQ channels is pulled high, the synchronous reception control module 1122 will simultaneously control the IQ channels to start data acquisition and transmit the integrated data of the I channel and the Q channel to the subsequent waveform data processing module 114 for processing. At this time, the IQ channels can be output synchronously until the acquisition length is reached and the acquisition is stopped. At this time, the synchronous reception control module 1122 will not send the I channel and Q channel data to the waveform data processing module 114; if the trigger signal TRIG is not received, the synchronous reception control module 1122 will not send the I channel and Q channel data to the waveform data processing module 114; when the working mode is not IQ, the synchronous reception control module 1122 controls the data collected by the IQ channels to be output to the subsequent waveform data processing module 114 according to the trigger signal TRIG of each of the IQ channels.

[0041] In one embodiment, the waveform receiving module 120 includes a receiving control module 122 and a read / write control module 124. The receiving control module 122 is connected to the digital waveform collector 110 and the read / write control module 124, receives the reconstructed waveform, and sends a write request instruction to the read / write control module 124. The read / write control module 124 is connected to the storage module 150 and stores the reconstructed waveform in the storage module 150 according to the write request instruction. The read / write control module 124 is connected to the storage module 150 via an Avalon interface.

[0042] The receiving control module 122 is specifically connected to the waveform data processing module 114 in the digital waveform collector 110. The port DTG_CTRL of the service decoding module 160 is connected to the receiving control module 122 to configure parameters for the receiving control module 122. The port DDR_RQE of the service decoding module 160 is connected to the read-write control module 124 to perform waveform reading operations on the storage module 150 through the read-write control module 124. Specifically, after receiving the reconstructed waveform, the receiving control module 122 initiates a write request instruction for the I channel and / or Q channel to the read-write control module 124 based on the sampling length, storage address, and other information issued by the service decoding module 160. The read-write control module 124 writes the reconstructed waveform of the I channel and / or Q channel into the storage module 150 according to the write request instruction.

[0043] Reference Figure 2The following describes the complete processing process of the original waveform: After the signal receiving device is powered on, the host computer communicates with the business decoding module 160 and issues instructions. The business decoding module 160 configures parameters for the waveform data processing module 114, the receiving control module 122 and the external clock chip 130. The external clock chip 130 outputs a fixed-frequency sampling clock to the analog-to-digital conversion device 140.

[0044] The synchronous reception control module 1122 receives the original waveform output by the ADC chip and caches it. After receiving the trigger signal TRIG sent by the service decoding module 160, it outputs the original waveform to the acquisition signal processing module 1124 for waveform synthesis. The synthesized original waveform is then input into the waveform data processing module 114 for resampling. After receiving the reconstructed waveform, the reception control module 122 sends a write request instruction to the read-write control module 124 based on the parameters configured by the service decoding module 160. The read-write control module 124 stores the reconstructed waveform in the storage module 150 based on the write request instruction. The host computer can also send instructions to the read-write control module 124 to read the reconstructed waveform from the storage module 150.

[0045] In one embodiment, an analog-digital hybrid test board is further provided, comprising the above-mentioned signal receiving device.

[0046] In one embodiment, a test machine is provided, comprising a communication board, a backplane, and the aforementioned analog-digital hybrid test board. The communication board is connected to the analog-digital hybrid test board via the backplane. The test machine also includes a host computer that communicates with the communication board. The host computer can be, but is not limited to, various personal computers, laptops, smartphones, tablet computers, and portable wearable devices. The portable wearable devices can be smart watches, smart bracelets, head-mounted devices, and the like.

[0047] The above-mentioned signal receiving device, method, analog-digital hybrid test board and test machine have the following advantages:

[0048] 1. This application uses the ADC chip to fix the sampling clock frequency. After power-on initialization, there is no need to repeatedly configure the external clock chip, which can simplify the complex procedures of the hardware link, reduce the index requirements for the external clock chip, and save costs.

[0049] 2. This application uses an ADC chip to fix the sampling clock frequency, and performs resampling operations through digital domain algorithms to achieve arbitrary frequency design, which can achieve uHZ resolution adjustment. This indicator requirement is difficult to achieve by the existing method of adjusting the sampling rate through the clock chip.

[0050] 3. This application can realize both IQ functions and non-IQ functions, making it more flexible and convenient to use and improving the efficiency of equipment use.

[0051] 4. The control method of this application facilitates the expansion, reuse, and transplantation of program channels and can be directly used in other projects. For program updates, only channels need to be added or reduced, which facilitates program code maintenance.

[0052] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0053] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the utility model patent. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A signal receiving device, characterized in that: include: A digital waveform collector, a waveform receiving module, an external clock chip and a storage module; the external clock chip is connected to an analog-to-digital conversion device, the digital waveform collector is connected to the analog-to-digital conversion device and the waveform receiving module, and the waveform receiving module is connected to the storage module; The external clock chip outputs a fixed-frequency sampling clock to the analog-to-digital conversion device; the digital waveform collector receives the original waveform of the fixed frequency output by the analog-to-digital conversion device according to the sampling clock, outputs the required reconstructed waveform of any clock and sends it to the waveform receiving module; The waveform receiving module stores the received reconstructed waveform into the storage module.

2. The signal receiving device according to claim 1, wherein: The waveform receiving module includes: A receiving control module, connected to the digital waveform collector and the read-write control module, receives the reconstructed waveform, and sends a write request instruction to the read-write control module; The read-write control module is connected to the storage module and stores the reconstructed waveform into the storage module according to the write request instruction.

3. The signal receiving device according to claim 2, wherein: The read-write control module is connected to the storage module via an Avalon interface.

4. The signal receiving device according to claim 1, wherein: The digital waveform collector comprises: a synchronization control module connected to the waveform data processing module and the analog-to-digital conversion device, configured to receive the original waveform of a fixed frequency output by the analog-to-digital conversion device, and send the original waveform to the waveform data processing module after receiving a trigger signal; The waveform data processing module is connected to the waveform receiving module, receives the original waveform, and outputs a required reconstructed waveform of any frequency to the waveform receiving module.

5. The signal receiving device according to claim 4, wherein: The synchronization control module includes: A synchronous receiving control module, connected to the acquisition signal processing module and two or more analog-to-digital conversion devices, receives the original waveforms output by each of the analog-to-digital conversion devices, and synchronously sends multiple original waveforms to the acquisition signal processing module after receiving a trigger signal; The acquisition signal processing module is connected to the waveform data processing module, synthesizes the received multiple original waveforms, and outputs one original waveform to the waveform data processing module.

6. The signal receiving device according to claim 5, characterized in that: The synchronous receiving control module is connected to the analog-to-digital conversion device via an LVDS interface to receive the original waveform.

7. The signal receiving device according to claim 4, wherein: Also includes: The service decoding module is connected to the digital waveform collector, the waveform receiving module and the external clock chip, configures parameters of the digital waveform collector, the waveform receiving module and the external clock chip, and performs waveform reading operations on the storage module through the waveform receiving module.

8. The signal receiving device according to any one of claims 1 to 7, characterized in that: The external clock chip is a PLL clock chip, and / or the storage module is a DDR storage module.

9. An analog-digital hybrid test board, characterized in that: The signal receiving device comprises the signal receiving device according to any one of claims 1 to 8.

10. A testing machine, characterized in that: The device comprises a communication board, a backplane and the analog-digital hybrid test board card as claimed in claim 9.

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