Test board compatible with multiple NAND sockets

Abstract

The utility model relates to the field of chip testing, in particular to a test board compatible with various NAND sockets, which comprises a connector J1, a first NAND socket, a second NAND socket, power conversion circuits and a voltage selection circuit, the connector J1 is connected between a main board and the first NAND socket and between the main board and the second NAND socket and used for realizing communication between a tested NAND and the main board, the number of the power conversion circuits is multiple, and the voltage selection circuit is connected between the main board and the first NAND socket and between the main board and the second NAND socket and used for realizing communication between the tested NAND and the main board. And the voltage selection circuit is used for converting an input voltage into various output voltages, the input of the voltage selection circuit is the output voltage of the power conversion circuit, and the corresponding voltage is selected through the power selection circuit to supply power to the first NAND socket and the second NAND socket. According to the utility model, the compatibility of NAND Flash chips of various packages, various manufacturers and various models is realized, the cost is saved, and the test efficiency is improved.

Description

Technical Field

[0001] The utility model relates to the field of chip testing, in particular to a test board compatible with multiple NAND sockets. Background Art

[0002] During SoC chip design, a thorough understanding of NAND Flash characteristics is essential. Furthermore, due to the wide variety of NAND Flash types and models available on the market, chips must be compatible with different models from different manufacturers. Therefore, simultaneous testing of NAND Flash models from different manufacturers is more practical. Different NAND Flash models have different packaging and operating voltages, and current test boards rarely offer both packaging and power supply compatibility with multiple NAND sockets. Utility Model Content

[0003] The technical problem to be solved by the utility model is to provide a test board compatible with multiple NAND sockets, thereby achieving compatibility with NAND Flash chips of multiple packages, multiple manufacturers and multiple models, saving costs and improving test efficiency.

[0004] In order to solve the above technical problems, the technical solution adopted by the present invention is: a test board compatible with multiple NAND sockets, including a connector J1, a first NAND socket, a second NAND socket, a power conversion circuit and a voltage selection circuit. The NAND under test is installed on the first NAND socket or the second NAND socket. The connector J1 is connected between the mainboard and the first NAND socket and the second NAND socket to achieve communication between the NAND under test and the mainboard. The test point is set between the NAND under test and the mainboard to test the communication between the NAND and the FPGA mainboard. The power conversion circuit has multiple channels for converting input voltage into multiple output voltages. The input of the voltage selection circuit is the output voltage of the power conversion circuit, and the corresponding voltage is selected by the power selection circuit to power the first NAND socket and the second NAND socket.

[0005] Furthermore, the first NAND socket is a BGA152 packaged NAND socket, an I / O pin of the first NAND socket is connected to the connector J1, and a filter capacitor is connected between a power pin of the first NAND socket and ground.

[0006] Furthermore, the second NAND socket is a BGA154 packaged NAND socket, an I / O pin of the second NAND socket is connected to the connector J1, and a filter capacitor is connected between a power pin of the second NAND socket and ground.

[0007] Furthermore, the power conversion circuit is implemented based on the chip EML3175. The input end of the chip EML3175 is connected to the input voltage, and the input voltage is connected to the enable end of the chip EML3175 through a pull-up resistor. The output end of the chip EML3175 outputs the converted voltage through a voltage divider and filtering circuit.

[0008] Furthermore, a four-way power conversion circuit is provided for converting the +5V input voltage into +3.3V, +2.5V, +1.8V and +1.2V respectively.

[0009] Furthermore, the voltage selection circuit includes a 3-pin connector and a jumper. Two pins of the 3-pin connector are connected to the output voltage of the voltage conversion circuit, namely pin 1 and pin 3. Another pin of the 3-pin connector is connected to the operating voltage of the first NAND socket or the second NAND socket, namely pin 2. The jumper is connected between pins 1 and 2 or between pins 2 and 3.

[0010] Furthermore, it also includes a connector J5, which is connected to the connector J1, and a test point is reserved between the connector J5 and the connector J1.

[0011] The beneficial effects of the present invention include compatibility with NAND Flash chips from various packages, manufacturers, and models, significantly reducing testing costs while still meeting testing requirements and improving testing efficiency. The test board is compatible with various NAND sockets, allowing for quick and easy replacement of NAND Flash chips. Furthermore, the inclusion of a voltage conversion circuit and a voltage selection circuit ensures power supply to the test board, eliminating the complex wiring of multiple power supplies from the motherboard. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is a principle block diagram of the utility model;

[0013] Figure 2 This is the circuit schematic diagram of connector J1;

[0014] Figure 3 The following is the schematic diagram of two power conversion circuits;

[0015] Figure 4 This is the schematic diagram of the other two power conversion circuits;

[0016] Figure 5 Schematic diagram for selecting circuits for voltage;

[0017] Figure 6 This is the schematic diagram of the first NAND socket;

[0018] Figure 7 This is the schematic diagram of the second NAND socket;

[0019] Figure 8 This is the circuit schematic diagram of connector J5. DETAILED DESCRIPTION

[0020] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0021] Example 1

[0022] This embodiment discloses a test board compatible with multiple NAND sockets, such as Figure 1 As shown, the device includes a connector J1, a first NAND socket, a second NAND socket, a power conversion circuit, and a voltage selection circuit. The NAND device under test is installed on the first or second NAND socket. Connector J1 is connected between the motherboard and the first or second NAND socket, enabling communication between the NAND device under test and the motherboard. A test point is located between the NAND device under test and the motherboard to test communication between the NAND device and the FPGA motherboard. The power conversion circuit has multiple channels for converting input voltages into multiple output voltages. The voltage selection circuit receives the output voltage of the power conversion circuit as input, and the power selection circuit selects the corresponding voltage to power the first and second NAND sockets.

[0023] like Figure 6 As shown, the first NAND socket is a BGA152 packaged NAND socket. Its I / O pins are connected to connector J1. Multiple parallel filter capacitors are connected between the power pins and ground of the first NAND socket. Due to the large number of pins on this socket, unconnected pins are not shown for clarity.

[0024] like Figure 7As shown, the second NAND socket is a BGA154 packaged NAND socket. Its I / O pins are connected to connector J1. Multiple parallel filter capacitors are connected between the power pins and ground of the second NAND socket. Due to the large number of pins on this socket, unconnected pins are not shown for clarity.

[0025] In this embodiment, the power conversion circuit is implemented based on the chip EML3175. The input end of the chip EML3175 is connected to the input voltage, and the input voltage is connected to the enable end of the chip EML3175 through a pull-up resistor. The output end of the chip EML3175 outputs the converted voltage through a voltage divider and filtering circuit.

[0026] like Figure 3 、 4 This embodiment has 4 power conversion circuits, which are Figure 3 The power conversion circuit shown in a converts the +5V input voltage into +3.3V. Figure 3 The power conversion circuit shown in b converts the +5V input voltage into +2.5V. Figure 4 The power conversion circuit shown in a converts the +5V input voltage into +1.8V. Figure 4 The power conversion circuit shown in Figure b converts the +5V input voltage into +1.2V. In the power conversion circuit, two resistors form a voltage divider resistor. Figure 3 Taking circuit a as an example, resistors R8 and R11 form a voltage divider resistor. Resistor R8 is connected between the output terminal of chip EML3175 and the feedback voltage terminal. Resistor R11 is connected between the feedback voltage terminal of chip EML3175 and ground. Inductor L1 and capacitors C12 and C13 form a filter circuit. Inductor L1 is connected between the output terminal of chip EML3175 and the output power supply 3.3V. Capacitors C12 and C13 are connected in parallel between the output power supply 3.3V and.

[0027] like Figure 5 As shown, the voltage selection circuit has two paths, each consisting of a 3-pin connector and a jumper. Two pins of the 3-pin connector are connected to the output voltage of the voltage conversion circuit, called pin 1 and pin 3, respectively. The other pin of the 3-pin connector is connected to the operating voltage of the first NAND socket or the second NAND socket, called pin 2. The jumper is connected between pins 1 and 2 or between pins 2 and 3.

[0028] like Figure 8 As shown, this embodiment further includes a connector J5, which is connected to the connector J1, and a test point is reserved between the connector J5 and the connector J1.

[0029] The test board described in this embodiment has a 5V power input. A 5V-to-3.3V power chip and a 5V-to-1.8V power chip are added to the test board, providing 3.3V and 1.8V voltages for the BGA152 packaged NAND Flash. A 5V-to-2.5V power chip and a 5V-to-1.2V power chip are added to provide 2.5V and 1.2V voltages for the BGA154 packaged NAND Flash. The 3.3V and 2.5V voltages are selected via a 3-pin connector and jumper cap, while the 1.8V and 1.2V voltages are selected via a 3-pin connector and jumper cap. The voltage value is selected based on the NAND Flash package used.

[0030] The test board is compatible with both BGA152 and BGA154 Flash Socket packages, allowing testing of all NAND Flash chips from all manufacturers and models on a single test board. Test points for data and control signals are also reserved on the board (via connector J5), making it easier to test communication between the FPGA and NAND Flash chips, as well as read and write timing, to verify communication between the main control unit and the NAND Flash in subsequent products.

[0031] This embodiment achieves compatibility with NAND Flash chips of various packages, manufacturers, and models, significantly reducing testing costs while meeting testing requirements and improving testing efficiency. The test board is compatible with various NAND sockets, allowing for quick and easy replacement of NAND Flash chips.

[0032] The above description is only the basic principle and preferred embodiments of the present invention. Improvements and substitutions made by those skilled in the art based on the present invention fall within the scope of protection of the present invention.

Claims

1. A test board compatible with multiple NAND sockets, characterized by: The device includes a connector J1, a first NAND socket, a second NAND socket, a power conversion circuit, and a voltage selection circuit. The NAND device under test is installed on the first NAND socket or the second NAND socket. The connector J1 is connected between the mainboard and the first NAND socket or the second NAND socket to achieve communication between the NAND device under test and the mainboard. The test point is set between the NAND device under test and the mainboard to test the communication between the NAND device and the FPGA mainboard. The power conversion circuit has multiple channels for converting input voltage into multiple output voltages. The input of the voltage selection circuit is the output voltage of the power conversion circuit. The power selection circuit selects the corresponding voltage to power the first NAND socket and the second NAND socket.

2. The test board compatible with multiple NAND sockets according to claim 1, characterized in that: The first NAND socket is a BGA152 packaged NAND socket. An I / O pin of the first NAND socket is connected to the connector J1. A filter capacitor is connected between a power pin of the first NAND socket and ground.

3. The test board compatible with multiple NAND sockets according to claim 1, characterized in that: The second NAND socket is a BGA154 packaged NAND socket, an I / O pin of the second NAND socket is connected to the connector J1, and a filter capacitor is connected between a power pin of the second NAND socket and ground.

4. The test board compatible with multiple NAND sockets according to claim 1, characterized in that: The power conversion circuit is implemented based on the chip EML3175. The input end of the chip EML3175 is connected to the input voltage, and the input voltage is connected to the enable end of the chip EML3175 through a pull-up resistor. The output end of the chip EML3175 outputs the converted voltage through a voltage divider and filtering circuit.

5. The test board compatible with multiple NAND sockets according to claim 4, characterized in that: It is equipped with 4 power conversion circuits for converting the +5V input voltage into +3.3V, +2.5V, +1.8V and +1.2V respectively.

6. The test board compatible with multiple NAND sockets according to claim 1, characterized in that: The voltage selection circuit includes a 3-pin connector and a jumper. Two pins of the 3-pin connector are connected to the output voltage of the voltage conversion circuit, called pins 1 and 3, respectively. The other pin of the 3-pin connector is connected to the operating voltage of the first or second NAND socket, called pin 2. The jumper is connected between pins 1 and 2 or between pins 2 and 3.

7. The test board compatible with multiple NAND sockets according to claim 1, characterized in that: It also includes a connector J5, which is connected to the connector J1. A test point is reserved between the connector J5 and the connector J1.

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