Pcie-based nand flash particle test system

Abstract

The utility model relates to the field of nand testing, in particular to a nand flash particle testing system based on pcie. Comprising a host and a test module, the test module comprises a pcie interface, a master control MCU, a temperature control module, a memory dram and base sockets, the master control MCU is connected with the host through the pcie interface, the temperature control module and the memory dram are also connected with the master control MCU, the master control MCU is connected with a plurality of base sockets through a bus, and nand flash to be tested is arranged on the base sockets; the host is provided with a command sending module and an error statistical analysis module, a test command is sent to the test module through the pcie interface, the test module executes the corresponding test command and then returns an execution result to the host through the pcie, and the error statistical analysis module performs statistical analysis on the execution result. The device is provided with an efficient and convenient interactive interface pcie, and the test efficiency can be improved.

Description

Technical Field

[0001] The utility model relates to the field of NAND testing, in particular to a NAND flash particle testing system based on PCIE. Background Art

[0002] Due to the physical properties of NAND Flash, the number of errors in read data varies under different conditions, such as temperature, number of erase / write cycles, and rest time. Generally, the number of errors increases significantly with increasing temperature, number of erase / write cycles, and rest time. However, since the increase in the number of errors under various conditions is not strictly linear, and multiple conditions often affect the number of errors simultaneously during actual use, it is difficult to predict the number of errors generated during data reads. This, in turn, can have unpredictable effects on NAND Flash data read performance and data accuracy. Therefore, it is necessary to test the number of errors generated when reading data under different conditions to obtain the error distribution probabilities. These error distribution probabilities can then be used to optimize NAND Flash read performance and improve data accuracy.

[0003] The number of errors when reading data from NAND Flash is affected by various factors. To determine the error distribution probability of NAND Flash under various scenarios, it is necessary to perform data read operations on the NAND Flash under various conditions and compare the errors generated during each read operation with the original data. The error distribution probability can then be calculated through multiple batch sample tests. For example, 16 NAND flash chips are selected and divided into four equal groups after data is written. After being left at 80°C for 4, 8, 12, and 16 hours, the data is read and the number of errors in each group is counted to determine the error distribution probability for this scenario. This scenario requires issuing write and read commands to each of the 16 NAND flash chips, recording the rest time, performing data comparisons, and calculating error statistics. This requires frequent command and data exchange. Generally, increasing the number of test granularity or test variable conditions increases the interaction overhead exponentially. Existing test equipment typically uses serial communication between the host and the test module, or performs complex computations such as data comparison and statistics on the host of the test module. This results in slow data transmission and low test efficiency. Utility Model Content

[0004] In view of the defects of the existing technology, the utility model provides a PCIE-based NAND Flash particle testing system with an efficient and convenient interactive interface PCIE, which can improve the testing efficiency.

[0005] In order to solve the technical problem, the technical solution adopted by the utility model is: a PCIE-based NAND flash particle testing system, including a host and a test module, the test module including a PCIE interface, a main control MCU, a temperature control module, a memory DRAM and a base socket, the main control MCU is connected to the host through the PCIE interface, the temperature control module and the memory DRAM are also connected to the main control MCU, the main control MCU is connected to multiple base sockets through a bus, and the NAND flash to be tested is set on the base socket; the host is provided with a command sending module and an error statistical analysis module, the test command is sent to the test module through the PCIE interface, the test module executes the corresponding test command and returns the execution result to the host through PCIE, and the error statistical analysis module performs statistical analysis on the execution result.

[0006] Furthermore, the NAND flash to be tested is plugged into the socket of the base.

[0007] Furthermore, the temperature control module includes a temperature probe, a heating plate, a fan and a microclimate chamber. The temperature probe, the heating plate and the fan are arranged in the microclimate chamber. The microclimate chamber is buckled on the NAND flash to be tested. The temperature probe, the heating plate and the fan are respectively connected to the main control MCU.

[0008] Furthermore, the number of base sockets is 16.

[0009] Furthermore, the test commands sent by the host to the main control MCU include write and read commands and temperature settings.

[0010] The beneficial effects of the present invention are as follows: the test module is connected to the host through a PCIE interface. PCIE is a high-speed serial computer expansion bus with fast data transmission speed, which can improve the data interaction speed between the host and the test module. In addition, the PCIE interface is plug-and-play, and the convenience of replacing the test tool is greatly improved compared with the traditional wiring method. By putting complex calculation operations such as data comparison and data statistics on the upper host for execution, the complexity of the test device is simplified, and the test device does not require strong data processing capabilities. The main control MCU is replaceable and highly selective, which reduces the cost requirements of the test device. It can be expanded to mount multiple NAND flash particles and test them at the same time. Relying on the powerful data interaction capability of PCIE, the test efficiency is greatly improved compared with the traditional serial port method. There are more test samples at the same time, and the test time and test complexity are basically unchanged, and the test results are more reliable. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is the principle frame of the utility model;

[0012] Figure 2 Flowchart for testing this system. DETAILED DESCRIPTION

[0013] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0014] Example 1

[0015] This embodiment discloses a nand flash particle testing system based on pcie. Figure 1 As shown, it includes a host and a test module. The test module includes a PCIe interface, a main control MCU, a temperature control module, a memory DRAM and a base socket. The main control MCU is connected to the host through the PCIe interface and communicates based on the PCIe interface protocol. It receives various operation instructions issued by the upper host, such as NAND flash write and read commands, temperature settings, etc. The content of the operation instructions is set according to the agreement between the test system and the upper host control system and can be flexibly changed.

[0016] The temperature control module and memory DRAM are also connected to the main control MCU. The main control MCU is connected to multiple base sockets through a bus, and the NAND flash to be tested is set on the base socket; the host is equipped with a command sending module and an error statistics analysis module. The test command is sent to the test module through the PCIE interface. After the test module executes the corresponding test command, the execution result is returned to the host through PCIE. The error statistics analysis module performs statistical analysis on the execution result.

[0017] In this embodiment, the master MCU is not directly connected to the NAND flash under test, but rather to a socket. The NAND flash under test does not need to be soldered to the test device, but rather plugs into the socket on the socket, making it easy to replace the NAND flash chip under test. The master MCU can also connect to multiple sockets simultaneously via a bus, allowing for easy expansion of the sample size to be tested.

[0018] In this embodiment, the temperature control module includes a temperature probe, a heater, a fan, and a microclimate chamber. The temperature probe, heater, and fan are located within the microclimate chamber, which snaps onto the NAND flash memory under test. The temperature probe, heater, and fan are each connected to the main control MCU. The temperature control module is used to set the test temperature within the test device and includes functions such as temperature stabilization, temperature increase, and temperature decrease. DRAM is used to cache data, such as control information from the main control MCU.

[0019] In this example, the base has 16 sockets. After data is written, the sockets are divided into four equal groups. The data is read after being left at 80°C for 4, 8, 12, and 16 hours, respectively. The number of errors in each group is counted to obtain the error distribution probability for this scenario. Although this scenario also requires frequent exchange of commands and data between the host and the test device, PCIe communication significantly improves communication speed.

[0020] In this embodiment, the host is provided with a command sending module and an error statistics analysis module, which puts complex calculation operations such as data comparison and data statistics into the upper host for execution, thereby simplifying the complexity of the test device and eliminating the need for strong data processing capabilities.

[0021] like Figure 2 As shown in the figure, the testing process of this system is as follows:

[0022] 1. After the test device is connected to the host through the PCIe interface, the system is initialized by starting the PCIe power supply.

[0023] 2. After the host detects the device mounted on the PCIe interface, it can send pre-agreed operation instructions through the host computer.

[0024] 3. After receiving the operation instructions via PCIe, the test device's main MCU parses the instructions and executes the corresponding operation. When receiving a NAND flash operation instruction, the main MCU generates the corresponding NAND flash command and sends it to the corresponding NAND flash chip for execution. When receiving a temperature control operation instruction, it sends it to the temperature control module for temperature control.

[0025] 4. After the tester's main MCU completes the operation instructions sent by the host, it uploads the execution results back to the host via PCIe. The host statistically summarizes all the execution results returned by the tester and analyzes them to generate the final data result, which is the probability distribution of the number of NAND flash errors in the current test scenario.

[0026] This test system can conveniently transmit commands and data through PCIE, set different test conditions, and test various characteristics of NAND flash in batches.

[0027] The above description is only the basic principle and preferred embodiments of the present invention. Improvements and substitutions made by those skilled in the art based on the present invention fall within the scope of protection of the present invention.

Claims

1. A PCIE-based NAND Flash particle testing system, characterized by: It includes a host and a test module. The test module includes a PCIe interface, a main control MCU, a temperature control module, a memory DRAM and a base socket. The main control MCU is connected to the host through the PCIe interface. The temperature control module and the memory DRAM are also connected to the main control MCU. The main control MCU is connected to multiple base sockets through a bus. The NAND flash to be tested is set on the base socket; the host is equipped with a command sending module and an error statistics analysis module. The test command is sent to the test module through the PCIe interface. After the test module executes the corresponding test command, the execution result is returned to the host through PCIe. The error statistics analysis module performs statistical analysis on the execution result.

2. The PCIE-based NAND Flash particle testing system according to claim 1, characterized in that: The NAND flash to be tested is plugged into the socket on the base.

3. The PCIE-based NAND Flash particle testing system according to claim 1, characterized in that: The temperature control module includes a temperature probe, a heating plate, a fan and a microclimate chamber. The temperature probe, the heating plate and the fan are arranged in the microclimate chamber, and the microclimate chamber is buckled on the NAND flash to be tested. The temperature probe, the heating plate and the fan are respectively connected to the main control MCU.

4. The PCIE-based NAND Flash particle testing system according to claim 1, characterized in that: The number of base sockets is 16.

5. The PCIE-based NAND Flash particle testing system according to claim 1, characterized in that: The test commands sent by the host to the main control MCU include write and read commands and temperature settings.

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