Multi-layer epitaxial trench gate super-junction MOS (Metal Oxide Semiconductor) structure

Abstract

The utility model relates to a multi-layer epitaxial trench gate super-junction MOS (Metal Oxide Semiconductor) structure, which comprises a first conductive type substrate, a first conductive type epitaxial layer, a second conductive type body region, a first conductive type source region 4, a second conductive type column, a gate structure and a second conductive type floating region, the second conductive type body region is arranged on the front surface of the first conductive type epitaxial layer and is positioned in the first conductive type epitaxial layer; the first conductive type source region is arranged on the front surface of the second conductive type body region and is located in the second conductive type body region; the second conductive type columns extend from the front surface to the back surface of the first conductive type epitaxial layer; the gate structure is arranged on the front surface of the first conductive type epitaxial layer and is arranged between two adjacent second conductive type columns; and the second conductive type floating region is arranged in the first conductive type epitaxial layer, is positioned on one side, facing the first conductive type substrate, of the gate structure, and is arranged at an interval with the gate structure.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductor devices, in particular to a multi-layer epitaxial trench gate super junction MOS structure. Background Art

[0002] MOS is one of the basic components in integrated circuit technology. Its main advantages include high integrability, fast switching speed, low power consumption, good electrical isolation and stability, which make it widely used in various applications such as digital circuits, analog circuits, microprocessors, memories and power amplifiers. The key innovation of planar MOS lies in the application of metal, oxide and semiconductor structures to transistor design. By forming a layer of oxide (usually silicon dioxide) on the semiconductor surface and using metal as the gate above it, the gate voltage is used to control the resistance of the conductive channel on the semiconductor surface between the source and drain to control the conductivity of the channel, thereby realizing the switching and amplification functions of the device.

[0003] In modern electronic devices, especially in high-frequency and high-power applications, reducing on-resistance is one of the key factors to improve device performance and power efficiency. The on-resistance of power MOS devices is mainly determined by the length and doping concentration of the epitaxial layer.

[0004] In the existing technology, the on-resistance is mainly reduced by reducing the length of the epitaxial layer and increasing the doping concentration of the epitaxial layer. However, this change will lead to a decrease in the breakdown voltage of the device. Therefore, the on-resistance and the breakdown voltage are in a contradictory or compromise relationship, that is, the reduction of the on-resistance is limited by the breakdown voltage. The method of reducing the on-resistance in the existing technology will limit the voltage resistance of the MOS device. Therefore, it is necessary to design a MOS structure that can improve the voltage resistance of the device and reduce the on-resistance. Utility Model Content

[0005] In view of this, the purpose of the present invention is to provide a multi-layer epitaxial trench gate super junction MOS structure to solve the technical problem in the prior art that it is impossible to improve the voltage withstand capability of the device while reducing the on-resistance.

[0006] The utility model provides a multi-layer epitaxial trench gate super junction MOS structure, comprising:

[0007] a first conductive type substrate;

[0008] A first conductive type epitaxial layer is provided on the front surface of the first conductive type substrate;

[0009] A second conductive type body region is provided on the front surface of the first conductive type epitaxial layer and is located within the first conductive type epitaxial layer;

[0010] A first conductive type source region is disposed on the front side of the second conductive type body region and is located within the second conductive type body region;

[0011] At least two second conductive type columns are provided, and the second conductive type columns extend from the front side to the back side of the first conductive type epitaxial layer;

[0012] a gate structure, disposed on the front surface of the first conductive type epitaxial layer and between two adjacent second conductive type pillars;

[0013] The second conductive type floating region is disposed in the first conductive type epitaxial layer and is located on a side of the gate structure facing the first conductive type substrate and is spaced apart from the gate structure.

[0014] Optionally, at least two second conductive type floating regions are provided, and the plurality of second conductive type floating regions are sequentially arranged toward the first conductive type substrate, with a gap provided between two adjacent second conductive type floating regions.

[0015] Optionally, the first conductivity type epitaxial layer includes a plurality of stacked sub-epitaxial layers.

[0016] Optionally, a plurality of the second conductivity type floating regions are respectively arranged in different sub-epitaxial layers, and two adjacent second conductivity type floating regions are separated by a layer of the sub-epitaxial layer.

[0017] Optionally, the concentration of the second conductive type ions in the second conductive type floating region is greater than the concentration of the second conductive type ions in the second conductive type pillars.

[0018] Optionally, multiple sub-epitaxial layers are stacked in sequence of n layers from the front side of the first conductive type substrate toward the second conductive type body region, wherein the thickness of the nth sub-epitaxial layer is not greater than the thickness of the n-1th sub-epitaxial layer, and the thickness of the nth sub-epitaxial layer is less than the thickness of the 1st sub-epitaxial layer.

[0019] Optionally, a first conductive type buffer layer is provided between the first conductive type epitaxial layer and the first conductive type substrate;

[0020] The first conductivity type ion concentration in the first conductivity type buffer layer is between the first conductivity type ion concentration in the first conductivity type substrate and the first conductivity type epitaxial layer.

[0021] Optionally, the gate structure includes a first trench opened on the front surface of the first conductive type epitaxial layer, a gate is arranged in the first trench, and a gate oxide layer is arranged between the gate and the inner wall of the first trench.

[0022] Optionally, the trench gate further includes a shielding gate disposed in the first trench, and a gate oxide layer is disposed between the shielding gate and an inner wall of the first trench.

[0023] Optionally, one or at least two gates may be provided in the first trench.

[0024] The technical solution of the utility model has the following advantages:

[0025] The multi-layer epitaxial trench gate super junction MOS structure provided by the present invention has lateral charge-assisted depletion by setting a second conductive type column or a second conductive type floating area, which greatly optimizes the electric field distribution and makes the electric field in the first conductive type epitaxial layer present a rectangular or trapezoidal distribution, thereby improving the device's withstand voltage. In addition, by setting the second conductive type column and the second conductive type floating area at the same time, the electric field distribution can be further optimized. Compared with the single setting of the second conductive type column or the second conductive type floating area, the device's withstand voltage is further improved. Due to the optimization of the electric field, when obtaining a high withstand voltage, a first conductive type epitaxial layer with lower resistivity and higher doping concentration can be used to further reduce the on-resistance, thereby achieving high withstand voltage while reducing the on-resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0027] Figure 1 A schematic cross-sectional view of a multi-layer epitaxial trench gate superjunction MOS structure of the present invention;

[0028] Figure 2 It is a schematic diagram of another embodiment of the gate structure in the present invention.

[0029] Description of reference numerals:

[0030] 1. First conductive type substrate; 2. First conductive type epitaxial layer; 21. Sub-epitaxial layer; 3. Second conductive type body region; 4. First conductive type source region; 5. Second conductive type column; 51. Second conductive type column region; 6. Gate structure; 61. Gate; 62. Shielding gate; 63. Gate oxide layer; 64. First trench; 7. Second conductive type floating region; 8. First conductive type buffer layer; 9. Insulating dielectric layer; 10. Metal contact through hole; 11. Front metal layer; 12. Back metal layer. DETAILED DESCRIPTION

[0031] Specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only some of the embodiments of the present invention, and not all of them. Based on the description of the present invention, all other embodiments derived by persons of ordinary skill in the art without inventive effort are also within the scope of protection of the present invention.

[0032] Unless otherwise specified or limited, the terms "disposed," "installed," and "connected" should be interpreted broadly. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; and direct or indirect connections through an intermediary. Those skilled in the art will understand the specific meanings of these terms based on the specific circumstances.

[0033] The directions or positional relationships indicated by terms such as "upper", "lower", "left", "right", "front", "back", "top", "bottom", "inside" and "outside" are based on the directions or positional relationships shown in the accompanying drawings, or are the directions or positional relationships in which the utility model product is usually placed when in use. They are only for the convenience and simplification of description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction. Therefore, they should not be understood as limitations on the utility model.

[0034] The terms "first," "second," "third," etc. are merely used to distinguish elements of similar nature and do not indicate or imply relative importance or a particular order.

[0035] The terms "comprises," "comprising," or any other variations thereof, are intended to cover a non-exclusive inclusion of elements other than the listed elements and may also include additional elements not specifically listed.

[0036] Example

[0037] For an N-type multi-layer epitaxial trench gate super junction MOS structure, the first conductivity type is N-type conductivity and the second conductivity type is P-type conductivity; for a P-type multi-layer epitaxial trench gate super junction MOS structure, the first conductivity type is P-type conductivity and the second conductivity type is N-type conductivity. In this embodiment, an N-type multi-layer epitaxial trench gate super junction MOS structure is taken as an example.

[0038] Reference Figure 1As shown, the utility model provides a multi-layer epitaxial trench gate super junction MOS structure, including a first conductive type substrate 1, a first conductive type epitaxial layer 2, a second conductive type body region 3, a first conductive type source region 4, a second conductive type column 5, a gate structure 6, and a second conductive type floating region 7. In this embodiment, the top surface is set as the front surface and the bottom surface is set as the back surface, wherein the first conductive type substrate 1 selects N-type silicon as the substrate, the first conductive type epitaxial layer 2 is provided on the front surface of the first conductive type substrate 1, the second conductive type body region 3 is provided on the front surface of the first conductive type epitaxial layer 2 and is located in the first conductive type epitaxial layer 2, at least two second conductive type columns 5 are provided, and the second conductive type columns 5 extend from the front surface of the first conductive type epitaxial layer 2 having the second conductive type body region 3 to the back surface of the first conductive type epitaxial layer 2, until extending from the second conductive type body region 3 to the first conductive type epitaxial layer 2 below the second conductive type body region 3;

[0039] The gate structure 6 is arranged on the front surface of the first conductive type epitaxial layer 2 and between two adjacent second conductive type pillars 5. Specifically, at least one gate structure 6 is provided, and a gate structure 6 is provided between two adjacent second conductive type pillars 5. The gate structure 6 also extends from the front surface of the first conductive type epitaxial layer 2 having the second conductive type body region 3 to the back surface of the first conductive type epitaxial layer 2, until it extends from the second conductive type body region 3 to the first conductive type epitaxial layer 2 below the second conductive type body region 3. The gate structure 6 is not limited to being set as a trench gate, but can also be set as a planar gate, which can be directly provided on the front surface of the first conductive type epitaxial layer 2. The first conductive type source region 4 is provided on the front surface of the second conductive type body region 3 and is located in the second conductive type body region 3. In this embodiment, a plurality of first conductive type source regions 4 are provided, and two first conductive type source regions 4 are correspondingly provided at each gate structure 6, which are respectively located on both sides of the gate structure 6 facing the second conductive type pillar 5 and extend toward the second conductive type pillar 5;

[0040] The second conductive type floating region 7 is arranged in the first conductive type epitaxial layer 2, and is located on the side of the gate structure 6 facing the first conductive type substrate 1 and is spaced apart from the gate structure 6. Specifically, a second conductive type floating region 7 is arranged under each gate structure 6, and there is a gap between the second conductive type floating region 7 and the gate structure 6. There is also a gap between the second conductive type floating region 7 and the second conductive type column 5.

[0041] By setting the second conductive type column 5 or the second conductive type floating area 7, there will be lateral charge-assisted depletion, which greatly optimizes the electric field distribution, so that the electric field in the first conductive type epitaxial layer 2 presents a rectangular or trapezoidal distribution, thereby improving the device's withstand voltage. In addition, setting the second conductive type column 5 and the second conductive type floating area 7 at the same time can further optimize the electric field distribution. Compared with setting a single second conductive type column 5 or a second conductive type floating area 7, the device's withstand voltage is further improved. Due to the optimization of the electric field, when obtaining high withstand voltage, a first conductive type epitaxial layer 2 with lower resistivity and higher doping concentration can be used to further reduce the on-resistance, thereby achieving high withstand voltage while reducing the on-resistance.

[0042] As a specific embodiment, the first conductive type epitaxial layer 2 includes a plurality of sub-epitaxial layers 21 stacked in sequence. The sub-epitaxial layers 21 are grown layer by layer through an epitaxial process. After epitaxially growing one layer of sub-epitaxial layer 21, second conductive type ions are injected into a partial area of ​​the sub-epitaxial layer 21 through photolithography shielding to form a second conductive type column area 51. Several sub-epitaxial layers 21 are epitaxially grown in connection, and second conductive type ions are injected into the same partial area of ​​each sub-epitaxial layer 21 to form a second conductive type column area 51. The second conductive type column areas 51 will be arranged in a vertical direction to form multiple rows. After completion, another layer of sub-epitaxial layer 21 is extended outward to form a first conductive type epitaxial layer 2, and high temperature is applied. At this time, the second conductive type column areas 51 in the same row are diffused and connected to form a second conductive type column 5.

[0043] In this embodiment, the second conductivity type floating region 7 has a greater concentration of second conductivity type ions in the second conductivity type floating region 7 than in the second conductivity type pillar 5. At least two second conductivity type floating regions 7 are provided at each gate structure 6. The plurality of second conductivity type floating regions 7 are sequentially arranged toward the first conductivity type substrate 1, with a gap provided between two adjacent second conductivity type floating regions 7.

[0044] The multiple second conductive type floating regions 7 at each gate structure 6 are respectively arranged in different sub-epitaxial layers 21, and two adjacent second conductive type floating regions 7 are separated by a layer of sub-epitaxial layer 21. Specifically, after the first layer of sub-epitaxial layer 21 is epitaxially grown, second conductive type ions are injected into a part of the sub-epitaxial layer 21 through photolithography shielding to form a second conductive type column region 51. At the same time, second conductive type ions can also be injected into a part of the sub-epitaxial layer 21 to form a second conductive type floating region 7. At this time, a second conductive type floating region 7 is provided between adjacent second conductive type column regions 51, and a gap is left between the second conductive type column region 51. When the second conductive type column region 51 is formed, the second conductive type floating region 7 is formed. When growing the second sub-epitaxial layer 21 of the first conductivity type epitaxial layer 2, only a portion of the sub-epitaxial layer 21 is masked by photolithography, and second conductivity type ions are implanted into the sub-epitaxial layer 21 to form a second conductivity type column region 51. When epitaxially growing the third sub-epitaxial layer 21, second conductivity type ions are implanted into the third sub-epitaxial layer 21 again by photolithography, forming a second conductivity type column region 51 and a second conductivity type floating region 7. This is repeated to form multiple sub-epitaxial layers 21. In this case, the second conductivity type floating region 7 does not require additional steps to be generated; it can be formed simultaneously with the formation of the second conductivity type column region 51, thus reducing process steps and improving production efficiency. For each of the multiple second conductivity type floating regions 7 at the gate structure 6, adjacent second conductivity type floating regions 7 are not limited to being separated by only one sub-epitaxial layer 21; they can also be separated by two or even three sub-epitaxial layers 21, and this can be adjusted according to actual conditions.

[0045] As a specific embodiment, the sub-epitaxial layer 21 is stacked in sequence from the front side of the first conductive type substrate 1 to the second conductive type body region 3, that is, from bottom to top, with n layers, wherein the thickness of the nth sub-epitaxial layer 21 is not greater than the thickness of the n-1th sub-epitaxial layer 21, and the thickness of the nth sub-epitaxial layer 21 is less than the thickness of the 1st sub-epitaxial layer 21; in this embodiment, the sub-epitaxial layer 21 is provided with 7-13 layers, and further, in this embodiment, the sub-epitaxial layer 21 is provided with 8 layers. By gradually reducing the thickness of multiple sub-epitaxial layers 21 from bottom to top, the electric field is evenly distributed, so that the electric field is more evenly distributed in the entire first conductive type epitaxial layer 2, thereby improving the voltage resistance of the device, effectively controlling the electric field gradient of each sub-epitaxial layer 21, and making the electric field gradually change between different layers, thereby avoiding the electric field mutation that may occur in the single-layer sub-epitaxial layer 21, refining the flow capacity, and achieving charge balance.

[0046] As a specific embodiment, the first conductive type ion concentration in the first conductive type substrate 1 is greater than the first conductive type ion concentration in the first conductive type epitaxial layer 2. At the same time, there is a first conductive type buffer layer 8 between the first conductive type substrate 1 and the first conductive type epitaxial layer 2. The first conductive type ion concentration in the first conductive type buffer layer 8 is between the first conductive type ion concentration in the first conductive type substrate 1 and the first conductive type epitaxial layer 2, which is used to prevent the ions of the first conductive type substrate 1 from diffusing into the first conductive type epitaxial layer 2, resulting in an increase in the on-resistance of the MOS structure. When the first conductive type buffer layer 8 is formed, the second conductive type column 5 can extend all the way to the back side of the first conductive type epitaxial layer 2 until it contacts the first conductive type buffer layer 8 or penetrates into the first conductive type buffer layer 8.

[0047] As a specific embodiment, specifically, the gate structure 6 includes a first trench 64 opened on the front side of the first conductive type epitaxial layer 2, and the first trench 64 extends from the front side of the first conductive type epitaxial layer 2 having the second conductive type body region 3 to the back side of the first conductive type epitaxial layer 2 until it extends to the sub-epitaxial layer 21 on the back side of the second conductive type body region 3. A gate 61 is arranged in the first trench 64, and a gate oxide layer 63 is arranged between the gate 61 and the inner wall of the first trench 64. The gate 61 is separated by the gate oxide layer 63 and the inner wall of the first trench 64. The gate 61 is conductive polysilicon, and the thickness of the gate oxide layer 63 between the gate 61 and the bottom wall of the first trench 64 is greater than the thickness of the gate oxide layer 63 between the gate 61 and the inner side wall of the first trench 64. The thicker gate oxide layer 63 at the bottom can improve the gate oxygen reliability of the device.

[0048] As another embodiment, the gate structure 6 also includes a shielding gate 62 arranged in the first trench 64. The shielding gate 62 is located below the gate 61. The depth of the shielding gate 62 in the first trench 64 is greater than the depth of the gate 61 in the first trench 64. The shielding gate 62 and the inner wall of the first trench 64 are also separated by the gate oxide layer 63. There is a gap between the shielding gate 62 and the gate 61 and they are also separated by the gate oxide layer 63. By setting the shielding gate 62, faster switching speed and lower switching loss can be achieved, further reducing the on-resistance and Miller capacitance, and improving the switching speed.

[0049] As another embodiment, referring to Figure 2As shown, two gates 61 are provided in the gate structure 6, and the shielding gate 62 is located between the two gates 61. Both the gate 61 and the shielding gate 62 extend from the notch of the first trench 64 to the inside of the first trench 64. Gaps are left between the gate 61 and the inner wall of the first trench 64 and the shielding gate 62. A gate oxide layer 63 is provided between the shielding gate 62 and the gate 61, between the gate 61 and the inner side wall of the first trench 64, and between the shielding gate 62 and the inner bottom wall of the first trench 64. The gate oxide layer 63 is used to separate them. The depth of the first trench 64 is set to 1.5μm-3μm. The depth of the shielding gate 62 in the first trench 64 is greater than the depth of the gate 61 in the first trench 64. In other embodiments, the number of gates 61 is not limited to a single number and can also be set to multiple.

[0050] As a specific embodiment, it also includes an insulating dielectric layer 9, a front metal layer 11 and a back metal layer 12, wherein the insulating dielectric layer 9 is arranged on the front side of the second conductive type body region 3 and covers the entire second conductive type body region 3, and a plurality of metal contact holes 10 are opened in the insulating dielectric layer 9, and the metal contact holes 10 are arranged corresponding to the second conductive type columns 5. The metal contact holes 10 penetrate into the second conductive type body region 3 above the second conductive type columns 5 and are connected to the first conductive type source region 4; the front metal layer 11 is arranged on the front side of the insulating dielectric layer 9, and the front metal layer 11 is located at the metal contact hole 10 and partially extends into the metal contact hole 10 until the metal contact hole 10 is filled. At this time, part of the front metal layer 11 in the metal contact hole 10 corresponding to the second conductive type column 5 will contact the second conductive type body region 3 and the first conductive type source region 4, and the back metal layer 12 is arranged on the back side of the first conductive type substrate 1 and covers the entire back side of the first conductive type substrate 1.

[0051] When a shielding gate 62 is provided and two gates 61 are provided, a metal contact through-hole 10 is also provided in the insulating dielectric layer 9 directly above the shielding gate 62, and the front metal layer 11 will also extend into the metal contact through-hole 10 there, filling the metal contact through-hole 10 there.

[0052] The method for preparing the above-mentioned multi-layer epitaxial trench gate super junction MOS structure includes the following steps:

[0053] S1, select a first conductive type substrate 1, and grow a first sub-epitaxial layer 21 on the front surface of the first conductive type substrate 1, wherein the first conductive type substrate 1 selects N-type silicon as the substrate, and the sub-epitaxial layer 21 is grown by an epitaxial process.

[0054] S2 , implanting second conductivity type ions into a portion of the sub-epitaxial layer 21 through photolithography masking to form a second conductivity type column region 51 .

[0055] S3, continuously epitaxially growing multiple sub-epitaxial layers 21 and implanting second conductive type ions into partial regions of the multiple sub-epitaxial layers 21 to form multiple rows of second conductive type column regions 51. In addition, while implanting second conductive type ions into partial sub-epitaxial layers 21 to form second conductive type column regions 51, second conductive type ions are further implanted into other partial regions to form multiple rows of vertically arranged second conductive type floating regions 7, with adjacent second conductive type floating regions 7 in each row separated by a layer of sub-epitaxial layer 21. After completion, epitaxially growing another layer of sub-epitaxial layer 21 to form the first conductive type epitaxial layer 2. At this time, the second conductive type floating regions 7 do not need to be generated in an additional step. The second conductive type floating regions 7 can be formed simultaneously with the formation of the second conductive type column regions 51, thereby reducing process steps and improving production efficiency.

[0056] S4, high temperature advancement, diffusing the second conductive type column regions 51, so that the second conductive type column regions 51 in each row are diffused and connected to form second conductive type columns 5;

[0057] S5, directly perform general implantation on the front surface of the first conductive type epitaxial layer 2, inject the second conductive type ions, and advance at high temperature, so as to form a second conductive type body region 3 on the front surface of the first conductive type epitaxial layer 2, and the second conductive type body region 3 covers the entire front surface of the first conductive type epitaxial layer 2.

[0058] S6. Through photolithography masking, a first trench 64 is etched in a partial area of ​​the front surface of the first conductive type epitaxial layer 2. The first trench 64 is located between two adjacent second conductive type columns 5 and above each row of second conductive type floating areas 7. The first trench 64 extends from the front surface of the first conductive type epitaxial layer 2 having the second conductive type body region 3 to the back surface of the first conductive type epitaxial layer 2 until it extends from the second conductive type body region 3 to the sub-epitaxial layer 2 below. The depth of the first trench 64 is set to 1.5μm-3μm.

[0059] S7, depositing a gate oxide layer 63 and conductive polysilicon in the first trench 64 to form a gate oxide layer 63, a gate 61 and a shield gate 62; in this embodiment, the gate oxide layer 63 is prepared by deposition, so that the thickness of the gate oxide layer 63 can be more accurately controlled without being limited by the growth rate and events. At the same time, the deposition technology can be carried out on different substrates and manufacturing conditions, so that it is suitable for large-scale production, and can be prepared more quickly, thereby improving production efficiency.

[0060] S8, through photolithography blocking, first conductive type ions are injected into a partial area on the front side of the second conductive type body region 3, and high temperature is promoted, so as to form a first conductive type source region 4 in the second conductive type body region 3. Specifically, through the blocking of the photolithography plate, two unblocked areas are formed in the second conductive type body region 3 on both sides of the gate structure 6 facing the second conductive type column 5, and first conductive type ions are injected into the unblocked areas. At this time, two undiffused first conductive type source regions 4 are formed in the second conductive type body region 3, and then high temperature promotion is performed to diffuse to form the first conductive type source region 4. The first conductive type source region 4 is provided on both sides of the gate structure 6, and the first conductive type source region 4 is in contact with the gate structure 6.

[0061] S9, an insulating dielectric layer 9 is deposited on the surface of the side of the first conductive type epitaxial layer 2 having the second conductive type body region 3, so that the insulating dielectric layer 9 covers the entire front surface of the first conductive type epitaxial layer 2, and then the insulating dielectric layer 9 is etched to etch a plurality of through holes on the insulating dielectric layer 9 to form a metal contact through hole 10. The metal contact through hole 10 is located directly above the second conductive type column 5, and during etching, an additional 0.3 mm to 0.4 mm is etched into the second conductive type body region 3 to ensure that the insulating dielectric layer 9 can be completely removed, so that the metal contact point is exposed, thereby ensuring the stability and reliability of the electrical connection.

[0062] S10 , depositing metal on the front surface of the insulating dielectric layer 9 and filling the metal contact through-holes 10 to form a front metal layer 11 , and depositing metal on the back surface of the first conductive type substrate 1 to form a back metal layer 12 .

[0063] As another embodiment, after selecting the first conductive type substrate 1, before forming the first conductive type epitaxial layer 2, a first conductive type buffer layer 8 will be grown on the first conductive type substrate 1. The first conductive type ion concentration in the first conductive type buffer layer 8 is between the first conductive type ion concentration in the first conductive type substrate 1 and the first conductive type epitaxial layer 2, which is used to prevent the ions of the first conductive type substrate 1 from diffusing into the first conductive type epitaxial layer 2, resulting in an increase in the on-resistance of the MOS structure.

[0064] The above is only a specific implementation method of the present invention, but the protection scope of the present invention is not limited to this. Any changes or replacements that can be easily thought of by any technician familiar with this technical field within the technical scope disclosed in the present invention should be included in the protection scope of the present invention.

Claims

1. A multi-layer epitaxial trench gate super junction MOS structure, characterized in that: include: a first conductive type substrate; A first conductive type epitaxial layer is provided on the front surface of the first conductive type substrate; A second conductive type body region is provided on the front surface of the first conductive type epitaxial layer and is located within the first conductive type epitaxial layer; A first conductive type source region is disposed on the front side of the second conductive type body region and is located within the second conductive type body region; At least two second conductive type columns are provided, and the second conductive type columns extend from the front side to the back side of the first conductive type epitaxial layer; a gate structure, disposed on the front surface of the first conductive type epitaxial layer and between two adjacent second conductive type pillars; The second conductive type floating region is disposed in the first conductive type epitaxial layer and is located on a side of the gate structure facing the first conductive type substrate and is spaced apart from the gate structure.

2. The multi-layer epitaxial trench gate super junction MOS structure according to claim 1, characterized in that: At least two second conductive type floating regions are provided. The plurality of second conductive type floating regions are sequentially arranged toward the first conductive type substrate, and a gap is provided between two adjacent second conductive type floating regions.

3. The multi-layer epitaxial trench gate super junction MOS structure according to claim 2, wherein: The first conductive type epitaxial layer includes a plurality of stacked sub-epitaxial layers.

4. The multi-layer epitaxial trench gate super junction MOS structure according to claim 3, characterized in that: A plurality of second conductive type floating regions are respectively arranged in different sub-epitaxial layers, and two adjacent second conductive type floating regions are separated by a layer of the sub-epitaxial layer.

5. The multi-layer epitaxial trench gate super junction MOS structure according to claim 1, wherein: The concentration of the second conductive type ions in the second conductive type floating region is greater than the concentration of the second conductive type ions in the second conductive type pillars.

6. The multi-layer epitaxial trench gate super junction MOS structure according to claim 3, wherein: Multiple sub-epitaxial layers are stacked in sequence from the front side of the first conductive type substrate toward the second conductive type body region, wherein the thickness of the nth sub-epitaxial layer is not greater than the thickness of the n-1th sub-epitaxial layer, and the thickness of the nth sub-epitaxial layer is less than the thickness of the 1st sub-epitaxial layer.

7. The multi-layer epitaxial trench gate super junction MOS structure according to claim 1, wherein: A first conductive type buffer layer is provided between the first conductive type epitaxial layer and the first conductive type substrate; The first conductivity type ion concentration in the first conductivity type buffer layer is between the first conductivity type ion concentration in the first conductivity type substrate and the first conductivity type epitaxial layer.

8. The multi-layer epitaxial trench gate super junction MOS structure according to any one of claims 1 to 7, characterized in that: The gate structure includes a first trench opened on the front surface of the first conductive type epitaxial layer, a gate is arranged in the first trench, and a gate oxide layer is arranged between the gate and the inner wall of the first trench.

9. The multi-layer epitaxial trench gate super junction MOS structure according to claim 8, characterized in that: The trench gate further includes a shielding gate disposed in the first trench, and a gate oxide layer is disposed between the shielding gate and an inner wall of the first trench.

10. The multi-layer epitaxial trench gate super junction MOS structure according to claim 9, characterized in that: There may be one or at least two gates disposed in the first trench.

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