Display device

Abstract

The display device includes: a partition wall disposed on a base layer; a light emitting portion disposed adjacent to the partition wall; an upper light emitting portion disposed on the partition wall; a first protective layer disposed on the light emitting portion; and a second protective layer disposed on the first protective layer. The first protective layer completely overlaps the light emitting portion in a plan view, and the second protective layer does not overlap at least a portion of the light emitting portion and at least a portion of the first protective layer in the plan view.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0132812 filed on October 5, 2023, in the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device and a method of manufacturing the same. Background Art

[0004] With the development of information technology, the importance of display devices as a connection medium between users and information is increasing. Therefore, research and development of display devices are continuously underway.

[0005] The display device may include a partition wall defining an area in which a light-emitting portion is provided and a protective layer covering at least a portion of the partition wall. If the protective layer is not properly formed in the display device, the risk of impurities (e.g., moisture) penetrating from the outside into the display device may increase. Utility Model Content

[0006] A technical problem to be solved by the present disclosure is to provide a display device having a protection structure capable of stably covering a partition wall while reducing the risk of infiltration of impurities from the outside, and a method of manufacturing the display device.

[0007] To solve the above technical problems, a display device according to an embodiment of the present disclosure may include: a partition wall disposed on a base layer; a light-emitting portion disposed adjacent to the partition wall; an upper light-emitting portion disposed on the partition wall; a first protective layer disposed on the light-emitting portion; and a second protective layer disposed on the first protective layer. The first protective layer may completely overlap with the light-emitting portion in a plan view, and the second protective layer may not overlap with at least a portion of the light-emitting portion and at least a portion of the first protective layer in a plan view.

[0008] According to an embodiment, the first protective layer may include at least one of silicon nitride and silicon oxide, and the second protective layer may include an amorphous material.

[0009] According to an embodiment, the second protective layer may include at least one of amorphous silicon, silicon carbide, and silicon nitride.

[0010] According to an embodiment, the display device may further include a pixel defining layer disposed on the base layer, a partition wall may be disposed on the pixel defining layer, and the light emitting portion may include an area that does not overlap with the second protective layer and the pixel defining layer in a plan view.

[0011] According to an embodiment, end portions of each of the upper light emitting portion, the first protective layer, and the second protective layer may coincide with each other.

[0012] According to an embodiment, at least a portion of the first protective layer may be bent to form an opening.

[0013] According to an embodiment, the opening and the second protective layer may overlap each other in a plan view.

[0014] According to an embodiment, the opening formed by the first protective layer and the second protective layer may be in contact with each other.

[0015] According to an embodiment, the partition wall may include a first partition wall layer disposed on the pixel defining layer and a second partition wall layer disposed on the first partition wall layer, and the second partition wall layer may protrude further outward than the first partition wall layer.

[0016] According to an embodiment, the first partition wall layer may include aluminum (Al), and the second partition wall layer may include titanium (Ti).

[0017] According to an embodiment, the first protective layer and the second protective layer may expose at least a portion of the second partition wall layer.

[0018] According to an embodiment, the thickness of the first protective layer may be about to about and the thickness of the second protective layer may be less than the thickness of the first protective layer.

[0019] To address the above technical issues, a display device according to another embodiment of the present disclosure may include: a partition wall disposed on a base layer; a light-emitting portion disposed adjacent to the partition wall; an upper light-emitting portion disposed on the partition wall; a first protective layer disposed on the light-emitting portion; and a second protective layer disposed on the first protective layer. The first protective layer may completely overlap the light-emitting portion in a plan view, and the second protective layer may include silicon nitride.

[0020] According to an embodiment, the second protective layer may completely overlap with the light emitting portion in a plan view.

[0021] According to an embodiment, the thickness of the first protective layer may be about to about and the thickness of the second protective layer may be less than the thickness of the first protective layer.

[0022] To address the above technical issues, a method for manufacturing a display device according to an embodiment of the present disclosure may include: forming a partition wall on a base layer; forming a light-emitting portion adjacent to the partition wall and an upper light-emitting portion on the partition wall; and forming a protective structure on the light-emitting portion. Forming the protective structure on the light-emitting portion may include: forming a first protective layer on the light-emitting portion; and forming a second protective layer on the first protective layer. Forming the first protective layer on the light-emitting portion may include depositing the first base protective layer on the light-emitting portion such that a surface of the first base protective layer is curved to form an opening, and forming the second protective layer on the first protective layer may include depositing the second base protective layer including an amorphous material.

[0023] According to an embodiment, the first base protective layer may include at least one of silicon nitride and silicon oxide, the second base protective layer may include at least one of amorphous silicon, silicon carbide and silicon nitride, and forming the first protective layer on the light-emitting portion may include depositing the first base protective layer through a CVD (chemical vapor deposition) process.

[0024] According to an embodiment, when forming a protective structure on the light-emitting portion, a photoresist may be provided on the second base protective layer, and the first base protective layer and the second base protective layer may be etched. Forming the second protective layer on the first protective layer may include depositing the second base protective layer to cover the surface of the first base protective layer except for the opening, and the photoresist may include a first portion and a second portion having different thicknesses, and may be provided on at least a portion of the second base protective layer.

[0025] According to an embodiment, the method of manufacturing a display device may further include forming a pixel defining layer on the base layer. Forming a partition wall on the base layer may include forming the partition wall on the pixel defining layer, a first portion of which may overlap with the upper light emitting portion in a plan view, and a second portion of which may not overlap with the pixel defining layer in a plan view.

[0026] According to an embodiment, the first and second base protective layers overlapping the first portion in plan view may not be etched, and the second base protective layer overlapping the second portion in plan view may be etched.

[0027] According to an embodiment, the first base protective layer may include at least one of silicon nitride and silicon oxide, the second base protective layer may include silicon nitrogen hydride, and when a protective structure is formed on the light-emitting portion, a photoresist may be set on the first base protective layer so that the photoresist contacts the first base protective layer.

[0028] According to an embodiment, the second base protective layer may be deposited to completely overlap the light emitting portion in a plan view. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a plan view schematically showing a display device according to an embodiment.

[0030] Figure 2 and Figure 3 is a schematic cross-sectional view of a display device according to an embodiment.

[0031] Figure 4 is a schematic cross-sectional view of a light emitting element according to an embodiment.

[0032] Figure 5 and Figure 6 is a schematic cross-sectional view of a display device according to an embodiment.

[0033] Figure 7 is a schematic block diagram schematically illustrating an electrical connection structure of a light emitting element according to an embodiment.

[0034] Figure 8 is a flowchart schematically illustrating a method of manufacturing a display device according to an embodiment.

[0035] Figure 9 and Figure 10 2 is a schematic cross-sectional view schematically illustrating a method of manufacturing a display device according to an embodiment in each process step.

[0036] Figure 11 is a schematic diagram showing the formation Figure 8 Flowchart of the steps of protecting the structure.

[0037] Figure 12 、 Figure 13 、 Figure 14 and Figure 15 2 is a schematic cross-sectional view schematically illustrating a method of manufacturing a display device according to an embodiment in each process step.

[0038] Figure 16 2 is a schematic cross-sectional view schematically illustrating a method of manufacturing a display device according to an embodiment in each process step.

[0039] Figure 17 is a schematic block diagram of a display system according to an embodiment.

[0040] Figure 18 is an application according to the implementation Figure 17 A schematic perspective view of an apparatus of a display system. DETAILED DESCRIPTION

[0041] Since the present disclosure allows for various changes and multiple embodiments, specific embodiments will be shown in the drawings and described in detail in the written description. However, this is not intended to limit the present disclosure to a specific mode of practice, and it should be understood that all changes, equivalents, and substitutions that do not depart from the spirit and technical scope of the present disclosure are included in the present disclosure.

[0042] It will be understood that although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this disclosure, the first element discussed below may be referred to as the second element. Similarly, the second element may also be referred to as the first element. In this disclosure, unless the context clearly indicates otherwise, singular expressions are intended to also include plural expressions.

[0043] It will also be understood that the terms “comprises,” “includes,” “has,” etc. used in this disclosure specify the presence of stated features, integers, steps, operations, elements, components, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

[0044] When an element, such as a layer, is referred to as being "on," "connected to," or "coupled to" another element or layer, it can be directly on, directly connected to, or directly coupled to the other element or layer, or there can be intervening elements or layers. However, when an element or layer is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. For this purpose, the term "connected" can refer to a physical connection, an electrical connection, and / or a fluid connection, with or without intervening elements. Furthermore, when an element is referred to as being "in contact," "contacted," etc., with another element, the element can be "electrically in contact" or "physically in contact" with the other element; or "indirectly in contact" or "directly in contact" with the other element.

[0045] For descriptive purposes, spatially relative terms such as "below," "beneath," "under," "down," "above," "up," "above," "higher," "side" (e.g., as in "sidewall"), etc. may be used herein to describe the relationship of one element to another element(s) as shown in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, elements described as being "below" or "beneath" other elements or features will then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both above and below orientations. Furthermore, the device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and therefore, the spatially relative descriptors used herein are interpreted accordingly.

[0046] Throughout the specification and claims, for purposes of its meaning and interpretation, the phrase “at least one of” is intended to include the meaning of “at least one selected from the group of”. For example, “at least one of A and B” may be understood to mean “A, B, or A and B.” Throughout the specification and claims, for purposes of its meaning and interpretation, the term “and / or” is intended to include any combination of the terms “and” and “or.” For example, “A and / or B” may be understood to mean “A, B, or A and B.” The terms “and” and “or” may be used in conjunction or separately and may be understood to be equivalent to “and / or.”

[0047] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense unless explicitly defined in the specification.

[0048] The present disclosure relates to a display device and a method for manufacturing the same. Hereinafter, a display device and a method for manufacturing the same according to embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0049] Figure 1 is a plan view schematically showing a display device according to an embodiment.

[0050] refer to Figure 1 The display device DD may be configured to emit light. The display device DD may include a light emitting element LD (see Figure 2). Depending on the embodiment, the display device DD may be a device that displays moving images or still images. The display device DD can be used as a display screen for various products such as televisions, laptops, monitors, billboards, and Internet of Things (IoT) devices, as well as portable electronic devices such as mobile phones, smartphones, tablet PCs (personal computers), smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, PMPs (portable multimedia players), navigation devices, and UMPCs (ultra-mobile PCs). However, the application fields of the display device DD are not limited to the specific examples.

[0051] The display device DD may have a rectangular flat plate shape in a plan view having short sides in a first direction DR1 and long sides in a second direction DR2 intersecting the first direction DR1. A corner portion where the short sides in the first direction DR1 and the long sides in the second direction DR2 intersect may be rounded to have a curvature, or may be formed at a right angle. The planar shape of the display device DD is not limited to a square shape, and may be formed into other polygonal shapes or rounded shapes such as a circle or an ellipse. The display device DD may be formed to be flat, but the present disclosure is not limited thereto. For example, the display device DD may include curved portions formed at the left and right end portions and having a constant curvature or a varying curvature. In an embodiment, the display device DD may be flexible so that it can be bent, folded, or curled.

[0052] In the present disclosure, the first direction DR1 may be a row direction of pixels PXL and may be a "horizontal" direction. The second direction DR2 may be a column direction of pixels PXL. The third direction DR3 may be a display direction of the display device DD or a normal direction of a plane on which the base layer BSL is disposed.

[0053] The display device DD may include a display area DA and a non-display area NDA. The non-display area NDA may be an area other than the display area DA. The non-display area NDA may surround at least a portion of the display area DA in a plan view.

[0054] The display area DA may be an area where the pixels PXL are disposed. The non-display area NDA may be an area where no pixels PXL are disposed. A driving circuit unit, wirings, and pads connected to the pixels PXL in the display area DA may be disposed in the non-display area NDA.

[0055] According to an embodiment, a pixel PXL (or subpixel SPX) may include a first subpixel SPX1, a second subpixel SPX2, and a third subpixel SPX3. At least one first subpixel SPX1, at least one second subpixel SPX2, and at least one third subpixel SPX3 may form a pixel unit PXU capable of emitting light of various colors. Figure 1An embodiment is illustrated in which each pixel PXL includes three sub-pixels SPX1 , SPX2 , and SPX3 (eg, a first sub-pixel SPX1 , a second sub-pixel SPX2 , and a third sub-pixel SPX3 ), but the present disclosure is not limited thereto.

[0056] According to an embodiment, the pixels PXL (or sub-pixels SPX) may be arranged in stripes or However, the present disclosure is not necessarily limited thereto.

[0057] The first subpixel SPX1 may emit a first light, the second subpixel SPX2 may emit a second light, and the third subpixel SPX3 may emit a third light. In an embodiment, the first light may be light in a red wavelength band, the second light may be light in a green wavelength band, and the third light may be light in a blue wavelength band. The red wavelength band may be a wavelength band within a range of approximately 600 nm to approximately 750 nm, the green wavelength band may be a wavelength band within a range of approximately 480 nm to approximately 560 nm, and the blue wavelength band may be a wavelength band within a range of approximately 370 nm to approximately 460 nm, but the present disclosure is not limited thereto.

[0058] Each of the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 may include an organic light emitting diode (OLED) or an inorganic light emitting element including an inorganic semiconductor as a light emitting element that emits light. Although the present disclosure is not limited to specific embodiments, for ease of description, an embodiment in which each of the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 includes an organic light emitting element will be described below.

[0059] Figure 2 and Figure 3 is a schematic cross-sectional view of a display device according to an embodiment. Figure 3 It is magnified Figure 2 Schematic cross-sectional view of the region. Figure 3 Can be set in Figure 1 Schematic cross-sectional view of one of the sub-pixels SPX on the base layer BSL. Figure 4 is a schematic cross-sectional view of a light emitting element according to an embodiment.

[0060] refer to Figures 2 to 4 , the display device DD may include a pixel circuit layer PCL and a light emitting element layer LEL.

[0061] The pixel circuit layer PCL may include a pixel circuit PXC (see FIG. Figure 7 The pixel circuit layer PCL may include a base layer BSL, conductive layers forming the pixel circuits PXC, and insulating layers disposed between the conductive layers.

[0062] According to an embodiment, the pixel circuit PXC may include circuit elements (eg, a driving transistor, etc.), and may be electrically connected to the light emitting element LD to provide an electrical signal so that the light emitting element LD emits light.

[0063] The light emitting element layer LEL may be disposed on the pixel circuit layer PCL. According to an embodiment, the light emitting element layer LEL may include a pixel defining layer PDL, a partition wall PW, a light emitting element LD, a protection structure 1000 and an encapsulation layer TFE.

[0064] The light emitting element LD may be provided on the pixel circuit layer PCL (or the base layer BSL). According to an embodiment, the light emitting element LD may include a first electrode ELT1, a light emitting portion EL, and a second electrode ELT2.

[0065] According to an embodiment, the light emitting portion EL may be provided in a region (eg, Figure 2 The light emitting portion EL may be disposed in the first sub-pixel region SPXA1, the second sub-pixel region SPXA2, or the third sub-pixel region SPXA3 as shown in FIG. The light emitting portion EL may be disposed between the partition walls PW. The light emitting portion EL may be disposed adjacent to the partition wall PW. The light emitting portion EL may include a first light emitting portion EL1 for forming a first sub-pixel SPX1 that emits light of a first color, a second light emitting portion EL2 for forming a second sub-pixel SPX2 that emits light of a second color, and a third light emitting portion EL3 for forming a third sub-pixel SPX3 that emits light of a third color.

[0066] One side of the light emitting portion EL may be electrically connected to the first electrode ELT1 , and the other side of the light emitting portion EL may be electrically connected to the second electrode ELT2 .

[0067] The first electrode ELT1 may be an anode electrode ANO for the light emitting portion EL, and the second electrode ELT2 may be a cathode electrode CAT for the light emitting portion EL. Depending on the embodiment, the first electrode ELT1 and the second electrode ELT2 may include a conductive material. For example, the first electrode ELT1 may include a reflective conductive material, and the second electrode ELT2 may include a transparent conductive material, but the present disclosure is not necessarily limited thereto. In another embodiment, the first electrode ELT1 may be a cathode electrode CAT for the light emitting portion EL, and the second electrode ELT2 may be an anode electrode ANO for the light emitting portion EL.

[0068] The light-emitting portion EL may have a multi-layer thin film structure including a light-generating layer (e.g., an emission layer EML). The light-emitting portion EL may include a hole injection layer HIL, a hole transport layer HTL, an emission layer EML, an electron transport layer ETL, and an electron injection layer EIL. The hole injection layer HIL injects holes, the hole transport layer HTL has excellent hole transport properties and suppresses the movement of electrons not bound in the emission layer EML to increase the chance of recombination of holes and electrons, the emission layer EML emits light through the recombination of injected electrons and holes, the electron transport layer ETL is used to easily transport electrons to the emission layer EML, and the electron injection layer EIL injects electrons. The light-emitting portion EL may emit light based on an electrical signal provided from an anode electrode ANO (e.g., a first electrode ELT1) and a cathode electrode CAT (e.g., a second electrode ELT2).

[0069] The pixel defining layer PDL may be disposed on the pixel circuit layer PCL. The pixel defining layer PDL may define a location where the light emitting portion EL is disposed. At least some portions of the pixel defining layer PDL may be spaced apart from each other, with the light emitting portion EL interposed between such portions of the pixel defining layer PDL. At least a portion of the pixel defining layer PDL may be disposed on the first electrode ELT1. The pixel defining layer PDL may be disposed adjacent to the first electrode ELT1. At least a portion of the pixel defining layer PDL may expose at least a portion of the first electrode ELT1. At least a portion of the pixel defining layer PDL may overlap with the first electrode ELT1 in a plan view. The pixel defining layer PDL may cover an end portion of the first electrode ELT1.

[0070] The pixel defining layer PDL may include an inorganic material. For example, the pixel defining layer PDL may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) and aluminum oxide (AlO x ). However, the present disclosure is not limited thereto. The pixel defining layer PDL may include an organic material. For example, the pixel defining layer PDL may include at least one of acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0071] A partition wall PW may be provided on the pixel defining layer PDL. The partition wall PW may be provided between the light emitting portions EL. The partition wall PW may be provided between adjacent sub-pixels SPX1, SPX2, and SPX3 or at the boundaries of adjacent sub-pixels SPX1, SPX2, and SPX3 to define a first sub-pixel region SPXA1, a second sub-pixel region SPXA2, and a third sub-pixel region SPXA3.

[0072] The partition wall PW may include a multilayer structure. Depending on the embodiment, the partition wall PW may include a double-layer structure. For example, the partition wall PW may include a first partition wall layer PW1 and a second partition wall layer PW2. However, the present disclosure is not necessarily limited thereto. Hereinafter, an embodiment in which the partition wall PW has a double-layer structure including the first partition wall layer PW1 and the second partition wall layer PW2 will be described.

[0073] The first partition wall layer PW1 and the second partition wall layer PW2 may be stacked in the thickness direction (eg, third direction DR3) of the base layer BSL. For example, the first partition wall layer PW1 may be disposed on the pixel defining layer PDL. The second partition wall layer PW2 may be disposed on the first partition wall layer PW1.

[0074] The first partition wall layer PW1 may have a width narrower than that of the second partition wall layer PW2. For example, the second partition wall layer PW2 may protrude further outward than the first partition wall layer PW1 in the first direction DR1 or the second direction DR2. For example, the partition wall PW may have a "T"-shaped structure in a cross-sectional view. For example, the partition wall PW may have a pointed structure in which the first partition wall layer PW1 is further recessed inward than the second partition wall layer PW2. Since the partition wall PW has a pointed structure, the light emitting portion EL may not cover at least a portion of the side surface of the first partition wall layer PW1.

[0075] When the organic material is deposited to form the light emitting portion EL, the light emitting portions EL can be separated from each other due to the pointed structure of the partition wall PW, and the sub-pixels SPX1, SPX2, and SPX3 can be separated from each other. For example, the light emitting portion EL can be divided into a first light emitting portion EL1, a second light emitting portion EL2, and a third light emitting portion EL3.

[0076] The first partition wall layer PW1 may have a thickness greater than that of the second partition wall layer PW2. For example, since the first partition wall layer PW1 is formed thicker than the second partition wall layer PW2, when the light emitting portion EL is formed, the light emitting portion EL may cover the side surface of the first partition wall layer PW1 and not cover the side surface of the second partition wall layer PW2.

[0077] In the present disclosure, the width may be defined based on a direction in which a plane in which the base layer BSL is provided extends (eg, the first direction DR1 or the second direction DR2 ), and the thickness may be defined based on a thickness direction of the base layer BSL (eg, the third direction DR3 ).

[0078] The partition wall PW may include a metal material. For example, the partition wall PW may include at least one of gold (Au), silver (Ag), aluminum (Al), molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and platinum (Pt).

[0079] According to an embodiment, the first partition wall layer PW1 may include aluminum (Al). According to an embodiment, the second partition wall layer PW2 may include titanium (Ti). However, the present disclosure is not limited thereto.

[0080] According to an embodiment, the display device DD may further include an upper light-emitting portion UEL. The upper light-emitting portion UEL may be disposed on the partition wall PW. In an embodiment of the present disclosure, the upper light-emitting portion UEL and the light-emitting portion EL that emits light may be formed in the same deposition process. The upper light-emitting portion UEL may be disposed on the second partition wall layer PW2. The upper light-emitting portion UEL may cover at least a portion of the second partition wall layer PW2. The upper light-emitting portion UEL may expose at least a portion of the second partition wall layer PW2.

[0081] According to an embodiment, the display device DD may further include an upper second electrode UELT2. The upper second electrode UELT2 may be disposed on the upper light emitting portion UEL. In an embodiment of the present disclosure, the upper second electrode UELT2 and the second electrode ELT2 disposed between the partition walls PW may be formed in the same deposition process. The upper second electrode UELT2 may be disposed on the second partition wall layer PW2. In a plan view, the upper second electrode UELT2 may overlap with at least a portion of the second partition wall layer PW2. The upper light emitting portion UEL may expose at least a portion of the second partition wall layer PW2.

[0082] The protection structure 1000 may be disposed on the second electrode ELT2. The protection structure 1000 may protect the second electrode ELT2, components disposed under the second electrode ELT2, and at least a portion of the partition wall PW.

[0083] The protective structure 1000 may include a multi-layer structure. For example, the protective structure 1000 may have a double-layer structure including a first protective layer L1 and a second protective layer L2. However, the present disclosure is not limited thereto. Hereinafter, an embodiment in which the protective structure 1000 has a double-layer structure including a first protective layer L1 and a second protective layer L2 will be described.

[0084] A first protective layer L1 may be disposed on the second electrode ELT2. The first protective layer L1 may be in contact with the second electrode ELT2. At least a portion of the first protective layer L1 may be in contact with the second electrode ELT2, and at least another portion of the first protective layer L1 may be in contact with the upper second electrode UELT2. At least a portion of the first protective layer L1 may cover side surfaces of the first partition wall layer PW1, the second partition wall layer PW2, the upper light emitting portion UEL, and the upper second electrode UELT2.

[0085] The first protective layer L1 may completely overlap the light emitting portion EL in a plan view. The first protective layer L1 may not be disposed on at least a portion of the second partition wall layer PW2. The first protective layer L1 may not contact at least a portion of the second partition wall layer PW2. The first protective layer L1 may expose at least a portion of the second partition wall layer PW2.

[0086] The thickness of the first protective layer L1 can be about to about However, the present disclosure is not limited thereto. The thickness of the first protective layer L1 may vary.

[0087] According to an embodiment, the first protective layer L1 may include an inorganic material. For example, the first protective layer L1 may include silicon nitride (SiN x )(x is a natural number from 1 to 5) and silicon oxide (SiO x )(x is a natural number from 1 to 5).

[0088] Experimentally, the first protective layer L1 includes silicon nitride (SiN x ) and silicon oxide (SiO x ), when the first protective layer L1 is deposited, the surface of the first protective layer L1 may be curved. At least a portion of the surface of the first protective layer L1 may be an inclined surface. The surface of the first protective layer L1 may be curved to define an opening H. For example, the surface of the first protective layer L1 may be curved to form an area A1 where the surfaces of the first protective layer L1 contact each other, and an opening H may be formed. The opening H may be defined by the surface of the first protective layer L1. The opening H may be an area where a discontinuous surface (e.g., a seam area) is formed when the first protective layer L1 is curved. The opening H may be disposed adjacent to the first partition wall layer PW1. The first protective layer L1 is interposed between the opening H and the first partition wall layer PW1.

[0089] The second protective layer L2 may be disposed on the first protective layer L1. The second protective layer L2 may be in contact with the first protective layer L1. The second protective layer L2 may expose at least a portion of the first protective layer L1. The second protective layer L2 may not overlap with at least a portion of the first protective layer L1 in a plan view. The second protective layer L2 may overlap with the opening H in a plan view. The second protective layer L2 may cover an area A1 where the surfaces of the first protective layer L1 are in contact with each other. For example, the second protective layer L2 may be in contact with a portion of the surfaces of the first protective layer L1 that are in contact with each other. For example, the second protective layer L2 may be in contact with the opening H.

[0090] The second protective layer L2 may overlap with the pixel defining layer PDL in a plan view. The second protective layer L2 may not overlap with at least a portion of the light emitting portion EL in a plan view. For example, at least a portion of the light emitting portion EL that does not overlap with the pixel defining layer PDL and the second protective layer L2 may not overlap with each other in a plan view.

[0091] The second protective layer L2 may not be disposed on at least a portion of the second partition wall layer PW2. The second protective layer L2 may not contact at least a portion of the second partition wall layer PW2. The second protective layer L2 may expose at least a portion of the second partition wall layer PW2.

[0092] The end of the second protective layer L2 and the end of the first protective layer L1 may overlap with each other. The end of the second protective layer L2 and the end of each of the upper second electrode UELT2 and the upper light emitting portion UEL may overlap with each other. The end of each of the second protective layer L2, the first protective layer L1, the upper second electrode UELT2, and the upper light emitting portion UEL may overlap with each other in a plan view. The edges of the second protective layer L2, the first protective layer L1, the upper second electrode UELT2, and the upper light emitting portion UEL may correspond to each other.

[0093] Since the display device DD according to an embodiment of the present disclosure includes the second protective layer L2, the risk of impurities (e.g., moisture) penetrating into the display device DD can be reduced. In conventional display devices, the protective layer provided on the second electrode ELT2 includes only the first protective layer L1. Therefore, moisture may penetrate into the opening H formed by the first protective layer L1. On the other hand, in the display device DD according to an embodiment of the present disclosure, since the second protective layer L2 covers the area A1 where the surfaces of the first protective layer L1 are in contact with each other, the risk of impurities (e.g., moisture) penetrating into the opening H can be reduced.

[0094] The thickness of the second protective layer L2 may be less than that of the first protective layer L1. For example, the thickness of the second protective layer L2 may be about to about However, the present disclosure is not limited thereto. The thickness of the second protective layer L2 may vary.

[0095] The second protective layer L2 may be an amorphous thin film layer. The second protective layer L2 may include an amorphous material. For example, the second protective layer L2 may include amorphous silicon. However, the present disclosure is not limited thereto. The second protective layer L2 may include various materials capable of forming an amorphous thin film layer. For example, the second protective layer L2 may include silicon carbide (SiC). For example, the second protective layer L2 may include silicon nitride (SiN x H y )(x is a natural number from 1 to 5, and y is a natural number from 1 to 5).

[0096] When the second protective layer L2 includes amorphous silicon, the extinction coefficient of the second protective layer L2 may be greater than or equal to about 0.1. In the present disclosure, the extinction coefficient may be a molecular extinction coefficient (k). The second protective layer L2 may absorb light to reduce scattering of external light incident on the partition wall PW. The second protective layer L2 may block light to reduce reflection of external light.

[0097] Because the second protective layer L2 exposes at least a portion of the first protective layer L1, light emitted from the light-emitting portion EL can be emitted into the emission region E1. The emission region E1 may be a region where light can be emitted outside the display device DD. The emission region E1 may be a region of the light-emitting portion EL that does not overlap with the pixel-defining layer PDL. The second protective layer L2 may not be disposed in a region overlapping with the emission region E1. Therefore, in the region overlapping with the emission region E1, light emitted from the light-emitting portion EL may not be blocked by the second protective layer L2.

[0098] The encapsulation layer TFE may be provided on the light emitting element LD (e.g., the second electrode ELT2). The encapsulation layer TFE may eliminate the step difference caused by the light emitting element LD and the pixel defining layer PDL. The encapsulation layer TFE may include a plurality of insulating layers covering the protective structure 1000 and the light emitting element LD. According to an embodiment, the encapsulation layer TFE may have a structure in which inorganic layers and organic layers are alternately stacked with each other. According to an embodiment, the encapsulation layer TFE may be a thin film encapsulation layer.

[0099] According to an embodiment, although not shown in the drawings, the display device DD may further include an optical functional layer, an overcoat layer, and a cover window provided on the encapsulation layer TFE. However, the structure of the display device DD is not necessarily limited to the above-described embodiment.

[0100] Figure 5 and Figure 6 is a schematic cross-sectional view of a display device according to an embodiment. Figure 6 It is magnified Figure 5 Schematic cross-sectional view of the region. Figure 6 Can be Figure 1 Schematic cross-sectional view of one of the sub-pixels SPX disposed on the base layer BSL. Figure 5 and Figure 6 A display device DD according to an embodiment is described.

[0101] and Figure 2 and Figure 3 Compared with the implementation method, Figure 5 and Figure 6 The embodiment may differ in that the second protection layer L2 completely covers the first protection layer L1 in the emission area E1.

[0102] The second protective layer L2 may be disposed on the first protective layer L1. The second protective layer L2 may completely cover the first protective layer L1 in the emission area E1. The second protective layer L2 may completely overlap the first protective layer L1 in the emission area E1 in a plan view.

[0103] The second protective layer L2 may be disposed on at least a portion of the second partition wall layer PW2. The second protective layer L2 may contact at least a portion of the second partition wall layer PW2. The second protective layer L2 may cover at least a portion of the second partition wall layer PW2. The second protective layer L2 may contact the upper light emitting portion UEL and the upper second electrode UELT2.

[0104] The second protective layer L2 may completely cover the light-emitting portion EL in a plan view. The second protective layer L2 may completely overlap the light-emitting portion EL in a plan view. At least a portion of the light-emitting portion EL that does not overlap with the pixel defining layer PDL and the second protective layer L2 may overlap each other in a plan view. The second protective layer L2 and the emission region E1 may overlap each other.

[0105] The second protective layer L2 of the display device DD according to the embodiment may include silicon nitride (SiN x H y ). Experimentally, compared with amorphous silicon, silicon nitride (SiN x H y ) can have a relatively low extinction coefficient. Therefore, even if the second protective layer L2 is deposited to completely cover the light-emitting portion EL, light emitted from the light-emitting portion EL in the emission area E1 may not be blocked by the second protective layer L2. Therefore, even if the second protective layer L2 completely overlaps the light-emitting portion EL, the luminous efficiency of the display device DD may not be reduced.

[0106] Figure 7 Schematic block diagram schematically showing the electrical connection structure of the light emitting element according to the embodiment. Figure 7 An electrical connection structure including a pixel circuit PXC corresponding to each sub-pixel SPX may be shown.

[0107] refer to Figure 7 , the sub-pixel SPX may include a pixel circuit PXC configured to drive the light emitting element LD.

[0108] The pixel circuit PXC may include one or more circuit elements. For example, the pixel circuit PXC may include a transistor and a storage capacitor. For example, the pixel circuit PXC may include a driving transistor, a switching transistor, and a storage capacitor. However, the present disclosure is not necessarily limited thereto.

[0109] The pixel circuit PXC may be electrically connected to a scan line SL and a data line DL. The scan line SL may provide a scan signal to the pixel circuit PXC. Depending on the embodiment, the scan line SL may be electrically connected to a gate electrode of a switching transistor of the pixel circuit PXC. The light emitting element LD may be configured to emit light corresponding to a data signal provided from the data line DL.

[0110] The pixel circuit PXC may be electrically connected to the first power line PL1 and the second power line PL2. For example, the first electrode ELT1 of the light emitting element LD may be electrically connected to the pixel circuit PXC and the first power line PL1, and the second electrode ELT2 of the light emitting element LD may be electrically connected to the second power line PL2. According to an embodiment, the second power line PL2 may be in the display area DA (see Figure 1 ) is formed in the pixel circuit layer PCL (see Figure 2 In another embodiment, the second power line PL2 may be disposed in the non-display area NDA (see Figure 1 Therefore, the second power line PL2 may be configured to provide the second power to the light emitting element LD.

[0111] The power supply of the first power line PL1 and the power supply of the second power line PL2 may have different potentials. For example, the power supply of the first power line PL1 may be a high-potential pixel power supply provided from the first voltage potential VDD, and the power supply of the second power line PL2 may be a low-potential pixel power supply provided from the second voltage potential VSS. The potential difference between the power supply of the first power line PL1 and the power supply of the second power line PL2 may be set to be higher than the threshold voltage of the light-emitting element LD.

[0112] The first power line PL1 may be electrically connected to the pixel circuit PXC (eg, a driving transistor). The second power line PL2 may be electrically connected to a cathode electrode (eg, a second electrode ELT2 ) of the light emitting element LD.

[0113] According to an embodiment, the second power line PL2 may be electrically connected to the second electrode ELT2 through the partition wall PW. For example, the partition wall PW may electrically connect the second electrode ELT2 and the second power line PL2.

[0114] Each light emitting element LD may be connected in a forward direction between the first power line PL1 and the second power line PL2 and form each effective light source. These effective light sources may be gathered together to form the light emitting element LD of the sub-pixel SPX.

[0115] The light emitting element LD may emit light having a brightness corresponding to the driving current provided by the pixel circuit PXC. During each frame period, the pixel circuit PXC may provide the light emitting element LD with a driving current corresponding to the data signal. The light emitting element LD may emit light having a brightness corresponding to the driving current.

[0116] In the following, reference will be made to Figures 8 to 15 A method of manufacturing the display device DD is described.

[0117] Figure 8 is a flowchart schematically illustrating a method of manufacturing a display device according to an embodiment. Figure 9 and Figure 10 2 is a schematic cross-sectional view schematically illustrating a method of manufacturing a display device according to an embodiment in each process step. Figure 11 is a schematic diagram showing the formation Figure 8 Flowchart of the steps of protecting the structure. Figure 12 、 Figure 13 、 Figure 14 and Figure 15 2 is a schematic cross-sectional view schematically illustrating a method of manufacturing a display device according to an embodiment in each process step.

[0118] refer to Figure 8 , a method of manufacturing a display device DD may include: forming a first electrode (S100); forming a pixel defining layer (S200); forming a partition wall (S300); forming a light emitting portion (S400); forming a second electrode (S500); and forming a protection structure (S600).

[0119] refer to Figure 9 Before forming the first electrode (S100), a pixel circuit PXC (see FIG. 1 ) for driving the light emitting element LD may be formed on the base layer BSL. Figure 7 ). The pixel circuit layer PCL may be formed to include a conductive layer and an insulating layer disposed between the conductive layers.

[0120] According to embodiments, components disposed on the base layer BSL may be formed through a conventional patterning process (eg, a photolithography process, etc.) using a mask.

[0121] In forming the first electrode ( S100 ), the first electrode ELT1 may be formed on the pixel circuit layer PCL. According to an embodiment, the first electrode ELT1 may be deposited on the pixel circuit layer PCL and etched to expose at least a portion of the pixel circuit layer PCL.

[0122] In the present disclosure, as a process for depositing components of the display device DD, one or more of a chemical vapor deposition (CVD) process and an atomic layer deposition (ALD) process may be used. In the present disclosure, as an etching process, one or more of a wet etching process and a dry etching process may be used. However, the present disclosure is not limited to specific examples.

[0123] Although not shown in the drawings, according to an embodiment, after the first electrode ELT1 is formed, the first electrode ELT1 may be electrically connected to the driving transistor through a hole passing through the protective layer of the pixel circuit layer PCL.

[0124] In forming the pixel defining layer (S200), a pixel defining layer (PDL) may be formed on the pixel circuit layer (PCL). The pixel defining layer (PDL) may be deposited on the pixel circuit layer (PCL) and the first electrode (ELT1), and may be etched to expose at least a portion of the first electrode (ELT1). The pixel defining layer (PDL) may be etched to overlap with the remaining portion of the first electrode (ELT1) in a plan view.

[0125] In forming the partition wall (S300), a partition wall PW may be formed on the pixel defining layer PDL. The partition wall PW may be deposited to have a multi-layer structure. For example, a first partition wall layer PW1 and a second partition wall layer PW2 may be deposited on the pixel defining layer PDL based on the third direction DR3.

[0126] The first partition wall layer PW1 may include aluminum (Al). According to an embodiment, the second partition wall layer PW2 may include titanium (Ti). However, the present disclosure is not limited thereto.

[0127] In forming the partition wall ( S300 ), after depositing the first and second partition wall layers PW1 and PW2 , an etching process may be performed on the first and second partition wall layers PW1 and PW2 in consideration of the material of each layer.

[0128] The first partition wall layer PW1 can be etched relatively deeper than the second partition wall layer PW2. The second partition wall layer PW2 can be etched to protrude further from the edge than the first partition wall layer PW1. The second partition wall layer PW2 can be etched to form a tip structure. According to an embodiment, the side surface of the first partition wall layer PW1 can form an inclined surface. For example, the cross-section of the first partition wall layer PW1 can have a trapezoidal shape that gradually narrows from the bottom to the top (for example, in the third direction DR3). However, the present disclosure is not limited thereto. The cross-section of the first partition wall layer PW1 can have a rectangular shape or a square shape.

[0129] refer to Figure 10 In forming the light emitting portion (S400), the light emitting portion EL may be patterned (e.g., deposited). The light emitting portion EL may be deposited to be formed between the partition walls PW. When depositing the light emitting portion EL, an upper light emitting portion UEL may also be formed in the same deposition process. For example, the upper light emitting portion UEL may be formed on the second partition wall layer PW2.

[0130] The light emitting portion EL may be deposited on the first electrode ELT1 between the pixel defining layer PDL and the first partition wall layer PW1 and may cover at least a portion of the pixel defining layer PDL and at least a portion of a side surface of the first partition wall layer PW1.

[0131] An upper light emitting portion UEL may be deposited on the second partition wall layer PW2. The upper light emitting portion UEL may cover at least a portion of the second partition wall layer PW2. The upper light emitting portion UEL may expose at least a portion of the second partition wall layer PW2.

[0132] In forming the second electrode (S500), the second electrode ELT2 may be deposited on the light emitting portion EL. The second electrode ELT2 may be deposited to be formed between the partition walls PW. When the second electrode ELT2 is formed, an upper second electrode UELT2 may also be formed in the same deposition process.

[0133] The second electrode ELT2 may be deposited on the light emitting portion EL between the first partition wall layers PW1. The second electrode ELT2 may cover at least a portion of the pixel defining layer PDL and at least a portion of a side surface of the first partition wall layer PW1.

[0134] The upper second electrode UELT2 may be deposited on the second partition wall layer PW2. The upper second electrode UELT2 may be deposited on the upper light emitting portion UEL. The upper second electrode UELT2 may cover at least a portion of the upper light emitting portion UEL. The upper light emitting portion UEL may expose at least a portion of the second partition wall layer PW2.

[0135] According to an embodiment, after forming the second electrode ELT2, forming a protection structure (S600) may be performed to manufacture the protection structure 1000. Forming the protection structure (S600) may include forming a first protection layer L1 and forming a second protection layer L2.

[0136] refer to Figure 11 , forming the protection structure (S600) may include: depositing a first base protection layer (S601); depositing a second base protection layer (S603); setting a photoresist (S605); and etching the first base protection layer and the second base protection layer (S607).

[0137] refer to Figure 12, in depositing the first basic protective layer (S601), a first basic protective layer B_L1 may be deposited. The first basic protective layer B_L1 may be deposited to completely cover the partition wall PW and the second electrode ELT2. For example, the first basic protective layer B_L1 may completely cover the first partition wall layer PW1, the second partition wall layer PW2, and the second electrode ELT2. In the present disclosure, the first basic protective layer B_L1 may be the first protective layer L1 before being etched, and the first basic protective layer B_L1 and the first protective layer L1 may include the same material. For example, the first basic protective layer B_L1 may include silicon nitride (SiN x ) and silicon oxide (SiO x ) at least one of .

[0138] The first base protective layer B_L1 may be deposited to have a to about The first base protection layer B_L1 may be deposited by a CVD process. Experimentally, when the first base protection layer B_L1 is deposited by a CVD process, due to the silicon nitride (SiN x ) and silicon oxide (SiO x ), at least a portion of the surface (e.g., top surface) of the first base protective layer B_L1 may be bent (e.g., folded) to form an opening H. Since at least a portion of the surface (e.g., top surface) of the first base protective layer B_L1 is curved, a region A1 where the surfaces of the first base protective layer B_L1 contact each other may be formed. Since the surface of the first base protective layer B_L1 is curved, a discontinuous surface (e.g., a seam region) may be formed. The region A1 where the surfaces of the first base protective layer B_L1 contact each other may provide a path through which impurities (e.g., moisture) can penetrate into the display device DD.

[0139] refer to Figure 13 , in depositing the second base protective layer (S603), a second base protective layer B_L2 may be deposited. The second base protective layer B_L2 may be deposited on the first base protective layer B_L1. The second base protective layer B_L2 may be deposited so as not to expose the first base protective layer B_L1. The second base protective layer B_L2 may be the second protective layer L2 before being etched, and the second base protective layer B_L2 and the second protective layer L2 may include the same material. For example, the second base protective layer B_L2 may include various materials capable of forming an amorphous thin film layer. For example, the second base protective layer B_L2 may include an amorphous material. For example, the second base protective layer B_L2 may include amorphous silicon, silicon carbide (SiC), and silicon nitride (SiN x H y ) at least one of .

[0140] Since the second base protective layer B_L2 includes an amorphous material, the second base protective layer B_L2 may not be bent when deposited, and thus, the second base protective layer B_L2 may not form an opening.

[0141] The second base protective layer B_L2 may be deposited to have a thickness thinner than that of the first base protective layer B_L1. For example, the second base protective layer B_L2 may be deposited to have a thickness of about to about The thickness is within the range of .

[0142] The second base protective layer B_L2 may completely cover the surface of the first base protective layer B_L1 except for the discontinuous surface. For example, the second base protective layer B_L2 may not contact the opening H defined by the first base protective layer B_L1.

[0143] The second base protective layer B_L2 may cover the area A1 where the surfaces of the first base protective layer B_L1 are in contact with each other. Since the second base protective layer B_L2 covers the area A1 where the surfaces of the first base protective layer B_L1 are in contact with each other, a path through which moisture may penetrate into the display device DD may be blocked, and the risk of moisture penetrating into the display device DD may be reduced.

[0144] refer to Figure 14 In the process of providing the photoresist (S605), a photoresist PR may be provided on the second base protective layer B_L2. The photoresist PR may expose at least a portion of the second base protective layer B_L2. The photoresist PR may not be provided on at least a portion of the second base protective layer B_L2. For example, in the region where the second partition wall layer PW2 is provided, if the region that does not overlap with the upper light emitting portion UEL or the upper second electrode UELT2 in plan view is defined as the partition wall central region S1, the photoresist PR may not be provided on at least a portion of the partition wall central region S1. For example, the photoresist PR may not overlap with at least a portion of the partition wall central region S1 in plan view.

[0145] The photoresist PR may include a first portion P1 and a second portion P2 having different thicknesses. The first portion P1 may be a portion of the photoresist PR that overlaps with the pixel defining layer PDL in a plan view. The second portion P2 may be a remaining portion of the photoresist PR that does not overlap with the pixel defining layer PDL in a plan view.

[0146] The photoresist PR may be configured such that the first portion P1 has a thickness greater than that of the second portion P2. The thickness of the first portion P1 may be the thickest of the photoresist PR overlapping both the pixel defining layer PDL and the upper light emitting portion UEL. The thickness of the second portion P2 may be the thickest of the photoresist PR that does not overlap with the pixel defining layer PDL in a plan view. Since the first portion P1 is thicker than the second portion P2, the second portion P2 may be exposed to a greater amount of light than the first portion P1.

[0147] refer to Figure 15 In etching the first and second base protective layers (S607), at least a portion of each of the first and second base protective layers B_L1 and B_L2 may be etched to form the first and second protective layers L1 and L2. In etching the first and second base protective layers (S607), the photoresist PR may be removed.

[0148] For example, in an area overlapping with the central area S1 of the partition wall where no photoresist PR is provided, the first base protective layer B_L1 and the second base protective layer B_L2 may be entirely etched. In an area overlapping with the second portion P2 of the photoresist PR that is provided thinner than the first portion P1 of the photoresist PR, in the first base protective layer B_L1 and the second base protective layer B_L2, the second base protective layer B_L2 may be etched and the first base protective layer B_L1 may not be etched. However, the present disclosure is not limited thereto. Depending on the thickness of the second portion P2, a portion of the first base protective layer B_L1 may be etched even in an area overlapping with the second portion P2. The first base protective layer B_L1 and the second base protective layer B_L2 that overlap with the first portion P1 of the photoresist PR may not be etched.

[0149] As the second base protective layer B_L2 is etched in the region overlapping with the second portion P2 of the photoresist PR, an emission region E1 may be formed. If the second base protective layer B_L2 includes amorphous silicon, the second base protective layer B_L2 may absorb light. However, since the second base protective layer B_L2 is removed from the region not overlapping with the pixel defining layer PDL, the emission region E1 may be secured to emit light outside the display device DD.

[0150] According to the method of manufacturing a display device DD disclosed herein, a photoresist PR for forming the second protective layer L2 may not be separately provided. For example, after depositing the first base protective layer B_L1 and the second base protective layer B_L2, a photoresist PR may be provided, and the second protective layer L2 may be formed through an etching process. Therefore, the same amount of photoresist PR as conventional methods may be used, and no additional photoresist PR may be required.

[0151] Figure 16 is a schematic cross-sectional view schematically illustrating a method for manufacturing a display device according to an embodiment in each process step. Figure 6 and Figure 16 A method of manufacturing the display device DD according to an embodiment is described.

[0152] The method of manufacturing the display device DD according to the present embodiment may have a difference in that the photoresist PR is provided before the second base protective layer is deposited. For example, the second base protective layer (S603) may be deposited after the photoresist is provided (S605).

[0153] A photoresist PR may be disposed on the first base protective layer B_L1 and may be in contact with at least a portion of the first base protective layer B_L1.

[0154] The photoresist PR may not be provided on at least a portion of the partition wall central region S1. For example, the photoresist PR may not overlap with at least a portion of the partition wall central region S1 in a plan view.

[0155] refer to Figure 6 and Figure 16 At least a portion of the first base protection layer B_L1 may be etched to form the first protection layer L1. When the first base protection layer B_L1 is etched, the photoresist PR may be removed.

[0156] In the region overlapping with the partition wall central region S1 where the photoresist PR is not provided, the entire first base protective layer B_L1 may be etched. In a plan view, the first base protective layer B_L1 may be etched less in the region overlapping with the second portion P2 of the photoresist PR than in the region overlapping with the first portion P1 of the photoresist PR. Since the first base protective layer B_L1 is etched less in the region overlapping with the second portion P2, the light emitting portion EL may not be exposed.

[0157] After etching the first base protective layer B_L1, in depositing the second base protective layer (S603), the second base protective layer may be deposited. The second base protective layer may be deposited on the first protective layer L1. The second base protective layer may completely cover the first protective layer L1. The second base protective layer may be deposited so that the first protective layer L1 is not exposed. The second base protective layer may completely overlap the light emitting portion EL in a plan view.

[0158] The second base protection layer may include silicon nitride (SiN x H y According to an embodiment, the second basic protection layer includes silicon nitride (SiN x H y), the second base protective layer may be deposited at a temperature lower than or equal to about 100°C.

[0159] According to an embodiment, the second base protective layer may not be removed from an area that does not overlap with the pixel defining layer PDL in a plan view. Experimentally, when the second base protective layer includes silicon nitride (SiN x H y ), the second base protective layer may have a relatively low extinction coefficient compared to an embodiment in which the second base protective layer includes amorphous silicon. Therefore, even when the second protective layer L2 is deposited to cover the light emitting portion EL, light emitted from the light emitting portion EL may not be blocked by the second protective layer L2.

[0160] According to an embodiment, the process of etching the second base protective layer may not be performed, and the second base protective layer may be used as the second protective layer L2.

[0161] In the above description, only a cross section of one of the first to third subpixels SPX1 to SPX3 is shown, and the method of manufacturing the display device DD is described. However, the above method of manufacturing the display device DD can be used to manufacture each of the first, second, and third subpixels SPX1, SPX2, and SPX3. For example, the protective structure 1000 can be formed in the region where the first, second, and third subpixels SPX1, SPX2, and SPX3 are provided. However, the present disclosure is not limited thereto.

[0162] Depending on the embodiment, some sub-pixels SPX may not include the second protective layer L2. For example, in the region where the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 are provided, the protective structure 1000 may be formed only in the region where the last pixel to be formed (e.g., the third sub-pixel SPX3) is provided. For example, the first sub-pixel SPX1 and the second sub-pixel SPX2 may not include the second protective layer L2, and the third sub-pixel SPX3 may include the second protective layer L2.

[0163] In the following, reference will be made to Figure 17 and Figure 18 A display system DS to which the display device DD can be applied is described.

[0164] Figure 17 is a schematic block diagram of a display system according to an embodiment. Figure 18 is an application according to the implementation Figure 17 A schematic perspective view of an apparatus of a display system.

[0165] refer to Figure 17 , the display system DS may include a processor 1100 and one or more display devices 1210 and 1220 .

[0166] The processor 1100 may perform various tasks and calculations. In an embodiment, the processor 1100 may include an application processor, a graphics processor, a microprocessor, a central processing unit (CPU), etc. The processor 1100 may be connected to other components of the display system DS through a bus system and control other components of the display system DS.

[0167] Figure 17 Schematically illustrated is an embodiment in which the display system DS includes a first display device 1210 and a second display device 1220. The processor 1100 may be connected to the first display device 1210 through a first channel CH1 and may be connected to the second display device 1220 through a second channel CH2.

[0168] The processor 1100 may transmit the first image data IMG1 and the first control signal CTRL1 to the first display device 1210 through the first channel CH1. The first display device 1210 may display an image based on the first image data IMG1 and the first control signal CTRL1. The first display device 1210 may be configured similarly to the reference image. Figure 1 A display device DD is described.

[0169] The processor 1100 may transmit the second image data IMG2 and the second control signal CTRL2 to the second display device 1220 through the second channel CH2. The second display device 1220 may display an image based on the second image data IMG2 and the second control signal CTRL2. The second display device 1220 may be configured similarly to the reference image. Figure 1 A display device DD is described.

[0170] The display system DS may include a computing system that provides image display functions, such as a portable computer, a mobile phone, a smartphone, a tablet personal computer, a smartwatch, a watch phone, a portable multimedia player (PMP), a navigation device, and an ultra-mobile personal computer (UMPC). The display system DS may be applied to at least one of a head-mounted display (HMD), a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.

[0171] refer to Figure 18 , Figure 17 The display system DS may be applied to a head-mounted display device 2000. The head-mounted display device 2000 may be a wearable electronic device that may be worn on a user's head.

[0172] The head-mounted display device 2000 may include a head-mounted strap 2100 and a display device storage box 2200. The head-mounted strap 2100 may be connected to the display device storage box 2200. The head-mounted strap 2100 may include a horizontal strap and / or a vertical strap for securing the head-mounted display device 2000 to the user's head. The horizontal strap may be configured to wrap around the sides of the user's head, and the vertical strap may be configured to wrap around the top of the user's head. However, the present disclosure is not limited thereto. For example, the head-mounted strap 2100 may be implemented in the form of eyeglass frames, a helmet, etc.

[0173] The display device storage box 2200 can accommodate Figure 17 The first display device 1210 and the second display device 1220. The display device storage box 2200 can also accommodate Figure 17 Processor 1100.

[0174] According to an embodiment of the present disclosure, a display device capable of reducing the risk of infiltration of impurities from the outside and having a protection structure capable of stably covering a partition wall and a method of manufacturing the display device are provided.

[0175] The above description is an example of the technical features of the present disclosure, and those skilled in the art will be able to make various modifications and changes. Therefore, the embodiments of the present disclosure described above can be implemented individually or in combination with each other.

[0176] Therefore, the embodiments disclosed in this disclosure are not intended to limit the technical spirit of this disclosure, but are intended to describe the technical spirit of this disclosure, and the scope of the technical spirit of this disclosure is not limited by these embodiments. The scope of protection of this disclosure should be interpreted by the appended claims, and it should be understood that all technical spirits within the scope of equivalents are included within the scope of this disclosure.

Claims

1. A display device, characterized in that: include: a partition wall provided on the base layer; a light-emitting portion, disposed adjacent to the partition wall; an upper light-emitting portion, disposed on the partition wall; a first protective layer, disposed on the light-emitting portion; as well as a second protective layer, disposed on the first protective layer; wherein the first protective layer completely overlaps with the light emitting portion in a plan view, and The second protective layer does not overlap at least a portion of the light emitting portion and at least a portion of the first protective layer in the plan view.

2. The display device according to claim 1, wherein The first protective layer includes at least one of silicon nitride and silicon oxide, and The second protection layer includes an amorphous material.

3. The display device according to claim 1, wherein Also includes: A pixel defining layer is provided on the base layer, Wherein, the partition wall is provided on the pixel defining layer, The light emitting portion includes a region that does not overlap with the second protective layer and the pixel defining layer in the plan view, and End portions of each of the upper light emitting portion, the first protective layer, and the second protective layer coincide with each other.

4. The display device according to claim 1, wherein At least a portion of the first protective layer is bent to form an opening, The opening and the second protective layer overlap each other in the plan view, and The opening formed by the first protective layer and the second protective layer are in contact with each other.

5. The display device according to claim 3, wherein The partition wall includes a first partition wall layer provided on the pixel defining layer and a second partition wall layer provided on the first partition wall layer, and The second partition wall layer protrudes further outward than the first partition wall layer.

6. The display device according to claim 5, wherein: The first partition wall layer includes aluminum, and The second partition wall layer includes titanium.

7. The display device according to claim 5, wherein: The first protective layer and the second protective layer expose at least a portion of the second partition wall layer.

8. The display device according to claim 1, wherein The thickness of the first protective layer is to within the scope, and The thickness of the second protective layer is smaller than the thickness of the first protective layer.

9. A display device, characterized in that: include: a partition wall provided on the base layer; a light-emitting portion, disposed adjacent to the partition wall; an upper light-emitting portion, disposed on the partition wall; a first protective layer, disposed on the light-emitting portion; as well as a second protective layer, disposed on the first protective layer; wherein the first protective layer completely overlaps with the light emitting portion in a plan view, and The second protective layer includes silicon nitride.

10. The display device according to claim 9, wherein The second protective layer completely overlaps the light emitting portion in the plan view.

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