Passive device and integrated passive device

Abstract

The utility model provides a passive device and an integrated passive device. The passive device comprises a substrate and an inductor located on one side of the substrate. The inductor comprises a first conductive layer and a second conductive layer, and the first conductive layer is arranged on one side of the substrate. The second conductive layer is arranged on the side, away from the substrate, of the first conductive layer, and the first conductive layer and the second conductive layer are different in thickness; the first insulating layer is arranged between the first conductive layer and the second conductive layer; and the at least one first connecting part penetrates through the first insulating layer and is electrically connected with the first conductive layer and the second conductive layer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a passive device and an integrated passive device. Background Art

[0002] With the development of communication technology, the requirements for the integration and performance of integrated passive devices prepared by semiconductor processes are becoming increasingly higher. Integrated passive devices include capacitors, inductors, resistors, etc. During operation, excessive loss will affect the operating effect of integrated passive devices. Therefore, improving the performance of devices is a problem that needs to be solved. Summary of the Invention

[0003] An embodiment of the present disclosure provides a passive device, including:

[0004] A substrate and an inductor located on one side of the substrate, wherein the inductor comprises:

[0005] A first conductive layer is provided on one side of the base substrate;

[0006] a second conductive layer, disposed on a side of the first conductive layer away from the base substrate, wherein the first conductive layer and the second conductive layer have different thicknesses;

[0007] a first insulating layer, disposed between the first conductive layer and the second conductive layer;

[0008] At least one first connecting portion passes through the first insulating layer and is electrically connected to the first conductive layer and the second conductive layer.

[0009] According to an embodiment of the present disclosure, at least one first via hole corresponding to the at least one first connecting portion is provided in the first insulating layer, and at least a portion of the first connecting portion is provided in the first via hole;

[0010] The aperture of the first via hole gradually increases in a direction away from the substrate.

[0011] According to an embodiment of the present disclosure, the first conductive layer is provided with at least one first blind hole corresponding one-to-one to the at least one first connecting portion on a side away from the base substrate, the orthographic projection of the first blind hole on the base substrate is within the orthographic projection of the first via hole on the base substrate, a portion of the first connecting portion is provided within the first via hole, and another portion of the first connecting portion is provided within the first blind hole.

[0012] According to an embodiment of the present disclosure, along a direction away from the substrate, the aperture change rate of the first via hole is smaller than the aperture change rate of the first blind hole.

[0013] According to an embodiment of the present disclosure, the first conductive layer and the second conductive layer are configured as a strip structure, and the aperture of the first via hole is positively correlated with the thickness or strip width of the second conductive layer.

[0014] According to an embodiment of the present disclosure, the passive device further includes a second transition layer.

[0015] The second transition layer is arranged on the sidewall of the first via hole, the bottom and sidewall of the first blind hole, and the side of the first insulating layer away from the substrate;

[0016] The second conductive layer covers the second transition layer.

[0017] According to an embodiment of the present disclosure, the first conductive layer and the second conductive layer are arranged in a strip structure, and the thickness of the second transition layer is positively correlated with the thickness of the second conductive layer or the strip width.

[0018] According to an embodiment of the present disclosure, the second transition layer includes a second adhesion layer and a second seed layer, and the second seed layer is disposed on a side of the second adhesion layer away from the base substrate.

[0019] According to an embodiment of the present disclosure, the orthographic projection of the first conductive layer on the base substrate is a first annular pattern having a first opening, and the orthographic projection of the second conductive layer on the base substrate is a second annular pattern having a second opening.

[0020] According to an embodiment of the present disclosure, the proportion of the first opening in the first annular pattern and the proportion of the second opening in the second annular pattern are both greater than one half.

[0021] According to an embodiment of the present disclosure, the first opening and the second opening face different directions.

[0022] According to an embodiment of the present disclosure, the first annular pattern and the second annular pattern are symmetrical patterns.

[0023] According to an embodiment of the present disclosure, the symmetrical pattern is a circle or a polygon.

[0024] According to an embodiment of the present disclosure, the inner angle of the polygon is greater than 90°.

[0025] According to an embodiment of the present disclosure, the first annular pattern and the second annular pattern have the same shape but different sizes.

[0026] According to an embodiment of the present disclosure, a width of the second annular pattern is greater than a width of the first annular pattern, and the width is the distance between an inner ring and an outer ring of the annular pattern.

[0027] According to an embodiment of the present disclosure, at least one of the first conductive layer and the second conductive layer has a protrusion in a direction parallel to the base substrate, and the protrusion is connected to the first connection portion.

[0028] According to an embodiment of the present disclosure, the passive component further includes:

[0029] a third conductive layer, disposed on a side of the second conductive layer away from the base substrate;

[0030] a second insulating layer, disposed between the second conductive layer and the third conductive layer;

[0031] at least one second connecting portion, penetrating the second insulating layer and electrically connecting to the second conductive layer and the third conductive layer;

[0032] A thickness of one of the first conductive layer, the second conductive layer, and the third conductive layer is different from thicknesses of the other two.

[0033] According to an embodiment of the present disclosure, an orthographic projection of the third conductive layer on the base substrate is a third annular pattern having a third opening, and a width of the third annular pattern is greater than a width of the second annular pattern.

[0034] According to an embodiment of the present disclosure, the thickness of the second conductive layer is greater than the thickness of the first conductive layer and the third conductive layer; or

[0035] The thickness of the first conductive layer is greater than that of the second conductive layer, and the thickness of the second conductive layer is greater than that of the third conductive layer.

[0036] According to an embodiment of the present disclosure, at least one second via hole corresponding to the second connecting portion is provided in the second insulating layer, and at least a portion of the second connecting portion is provided in the second via hole;

[0037] The orthographic projections of the first connecting portion and the second connecting portion on the substrate do not overlap.

[0038] The present disclosure also provides an integrated passive device, including:

[0039] The above-mentioned passive components and

[0040] A capacitor is electrically connected to the first conductive layer of the inductor.

[0041] According to an embodiment of the present disclosure, the capacitor includes a first electrode disposed on one side of a substrate, a second electrode disposed on a side of the first electrode away from the substrate, and a first dielectric layer disposed between the first electrode and the second electrode;

[0042] The orthographic projections of the first electrode, the first dielectric layer, and the second electrode on the substrate at least partially overlap;

[0043] The inductor and the capacitor are arranged on the same side of the base substrate, and the first conductive layer of the inductor and the first electrode of the capacitor are arranged on the same layer and are electrically connected.

[0044] According to an embodiment of the present disclosure, the thickness of the first electrode is the same as the thickness of the first conductive layer, and the thickness of the first electrode is greater than the thickness of the second electrode.

[0045] The beneficial effects of the present disclosure are to reduce the parasitic resistance of the inductor, improve the quality factor of the inductor, and at the same time avoid the phenomenon that the outermost conductive layer is easily peeled off as much as possible. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The accompanying drawings are used to further illustrate various embodiments and to explain all the various principles and advantages of the present disclosure. In the accompanying drawings, like reference numerals refer to the same or functionally similar elements throughout the different views, and the figures are not necessarily drawn to scale. The accompanying drawings, together with the detailed description below, are incorporated into this specification and form a part of this specification.

[0047] Figure 1 A partial structural diagram of an integrated passive integrated circuit is shown.

[0048] Figure 2 A cross-sectional view of a passive component according to an embodiment of the present disclosure is shown.

[0049] Figure 3 A cross-sectional view of a passive component according to another embodiment of the present disclosure is shown.

[0050] Figure 4 A cross-sectional view of a passive component according to another embodiment of the present disclosure is shown.

[0051] Figure 5 A perspective view of a passive component according to an embodiment of the present disclosure is shown.

[0052] Figure 6 A perspective view of a passive component according to another embodiment of the present disclosure is shown.

[0053] Figure 7 A cross-sectional view of a passive component according to an embodiment of the present disclosure is shown.

[0054] Figure 8 A partial cross-sectional view of a passive component according to an embodiment of the present disclosure is shown.

[0055] Figure 9 A partial cross-sectional view of a passive component according to another embodiment of the present disclosure is shown.

[0056] Figure 10 A partial cross-sectional view of a passive component according to another embodiment of the present disclosure is shown.

[0057] Figure 11 A cross-sectional view of a passive component according to another embodiment of the present disclosure is shown.

[0058] Figure 12 FIG2 shows a schematic cross-sectional view of a passive component according to another embodiment of the present disclosure.

[0059] Figure 13 A perspective view of a passive component according to another embodiment of the present disclosure is shown.

[0060] Figure 14 A perspective view of a passive component according to another embodiment of the present disclosure is shown.

[0061] Figure 15 A perspective view of a passive component according to another embodiment of the present disclosure is shown.

[0062] Figure 16 A perspective view of a passive component according to another embodiment of the present disclosure is shown.

[0063] Figure 17 A perspective view of a passive component according to another embodiment of the present disclosure is shown.

[0064] Figure 18 A perspective view of a passive component according to another embodiment of the present disclosure is shown.

[0065] Figure 19 A perspective view of a passive component according to another embodiment of the present disclosure is shown.

[0066] Figure 20 A cross-sectional view of an integrated passive device according to an embodiment of the present disclosure is shown.

[0067] Figure 21 A cross-sectional view of an integrated passive device according to another embodiment of the present disclosure is shown.

[0068] Figure 22 A cross-sectional view of an integrated passive device according to another embodiment of the present disclosure is shown.

[0069] Figure 23 A cross-sectional view of an integrated passive device according to another embodiment of the present disclosure is shown.

[0070] The markings of the components in the accompanying drawings are as follows:

[0071] 1. Substrate; 2. Capacitor; 2.1. First electrode; 2.2. First dielectric; 2.3. Second electrode; 3. Inductor; 3.1. First conductive layer; 3.2. Second conductive layer; 3.3. Third conductive layer; 3.4. Fourth conductive layer; 4. First trace 302; 5.2. Second trace 303; 5.4. Insulation layer; 5.5. Connecting portion; 5.1. First connecting portion; 5.2. Second connecting portion; 5.3. Third connecting portion; 5.4. Fourth connecting portion; 5.1. First via hole; 5.2. Second via hole; 5.0. First aperture; 5.0. Second aperture; 5.1. First blind hole; 5.2. Second blind hole; 5.4. First transition layer; 5.5. Second transition layer; 5.6. Second transition layer; 5.4. First adhesion layer; 5.4. First seed layer; 5.5. Second adhesion layer; 5.5. Second seed layer; 5.6. Third adhesion layer; 5.6. Third seed layer; 5.3. Protrusion; 5.3. First protrusion; 5.3. Second protrusion; 6. Bump; 7. Solder ball; 10. Integrated passive circuit DETAILED DESCRIPTION

[0072] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0073] Although relative terms such as "upper" and "lower" are used in this specification to describe the relationship of one illustrated component to another, these terms are used herein for convenience only, such as in accordance with the orientation of the illustrations in the accompanying drawings. It will be understood that if the illustrated device were flipped upside down, the component described as "upper" would become the component "lower." When a structure is referred to as "on" another structure, this may mean that the structure is integrally formed with the other structure, that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via the other structure.

[0074] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0075] Throughout the description, the terms “vertical,” “perpendicularly,” and “first direction” refer to a direction perpendicular to a plane parallel to a conventional plane or surface of the substrate base plate, ie, the Z direction or first direction.

[0076] Throughout the description, the "outermost layer" refers to the layer furthest away from the substrate along a first direction, wherein the Z direction refers to the first direction. The "outermost conductive layer" in the figure refers to the conductive layer furthest away from the substrate among the multiple conductive layers.

[0077] Integrated Passive Devices (IPDs) are a technology that integrates passive components in circuits (such as resistors, capacitors, and inductors) onto a single, compact chip. Compared to traditional discrete components, IPDs offer numerous advantages, including small size, highly consistent performance, excellent stability, low cost, and high efficiency. Because they offer excellent high-frequency characteristics and broadband bandwidth, IPDs are widely used in mobile communications, wireless networks, satellite communications, radar systems, and other fields. Within these applications, they are typically used for filtering, matching networks, power distribution, and signal coupling.

[0078] Integrated passive devices generally include a variety of passive components, such as resistors, capacitors, and inductors, and semiconductor processes are generally used to achieve high-density, high-performance passive component integration on a substrate 10 . Figure 1 The passive integrated circuit includes a capacitor structure 20 and an inductor 30 on one side of a substrate 10 , which are connected via conductive materials filled in a via structure of a multi-layer insulating layer 40 .

[0079] During the operation of a passive integrated device, the conductive layer in the inductor 30 generates parasitic resistance, which affects the quality factor (Q value) and efficiency of the inductor 30 and results in operating losses. A higher Q value indicates lower losses; conversely, a lower Q value indicates greater losses, which has a greater impact on the operating performance of the inductor 30 and the entire integrated passive device. Currently, as the integration density of integrated passive devices increases, the area of ​​the inductor 30 is shrinking. Reducing the losses caused by parasitic resistance and improving the inductor Q value while maintaining high integration density is a major challenge facing the development of integrated passive devices.

[0080] The embodiments of the present disclosure provide a passive device and an integrated passive circuit, which can improve the quality factor of an inductor.

[0081] like Figure 2As shown, the passive device includes a substrate 1 and an inductor 3 located on one side of the substrate 1. The inductor 3 includes a first conductive layer 31, a second conductive layer 32, a first insulating layer P1, and at least one first connecting portion 51. The first conductive layer 31 is disposed on one side of the substrate 1, and the second conductive layer 32 is disposed on a side of the first conductive layer 31 away from the substrate 1. The first conductive layer 31 and the second conductive layer 32 have different thicknesses. The first insulating layer P1 is disposed between the first conductive layer 31 and the second conductive layer 32. The at least one first connecting portion 51 penetrates the first insulating layer P1 and electrically connects to the first conductive layer 31 and the second conductive layer 32.

[0082] In some embodiments, the first insulating layer P1 is provided with at least one first via hole 511 corresponding to at least one first connection portion 51. At least a portion of the first connection portion 51 is disposed within the first via hole 511. The aperture of the first via hole 511 increases gradually as it moves away from the base substrate 1.

[0083] The above description uses two conductive layers as an example. The inductor 3 includes a first conductive layer 31 and a second conductive layer 32 spaced apart on one side of the substrate 1. A first insulating layer P1 is disposed between the first conductive layer 31 and the second conductive layer 32. The first insulating layer P1 is provided with at least a first via 511. The first connecting portion 51 is located within the first via 510, connecting the first conductive layer 31 and the second conductive layer 32, thereby achieving an electrical connection between the first conductive layer 31 and the second conductive layer 32. However, the embodiments of the present disclosure are not limited thereto. In some embodiments, the inductor 3 may also include three or more conductive layers.

[0084] like Figure 2 As shown, the inductor may further include a third conductive layer 33, a second insulating layer P2, and at least one second connecting portion 52. The third conductive layer 33 is disposed on a side of the second conductive layer 32 away from the substrate 1. The second insulating layer P2 is disposed between the second conductive layer 32 and the third conductive layer 33. The at least one second connecting portion 52 penetrates the second insulating layer P2 and electrically connects to the second conductive layer 32 and the third conductive layer 33.

[0085] The thickness of one of the first conductive layer 31, the second conductive layer 32, and the third conductive layer 33 may be different from the thickness of the other two. In some embodiments, the thickness of the third conductive layer 33 is less than the thickness of the first conductive layer 31 and the second conductive layer 32. In the process of preparing multiple film layers stacked in sequence, the thicker the conductive layer is, the more likely it is to induce film peeling or separation problems in subsequent processes. The embodiments of the present disclosure design the thickness of the third conductive layer 33 to be less than the thickness of the first conductive layer 31 and the second conductive layer 32, so that the conductive layer farthest from the substrate is the thinnest, thereby preventing the phenomenon of film peeling during the preparation of multiple film layers and improving the reliability of inductors and integrated passive devices.

[0086] The thickness of the second conductive layer 32 and the first conductive layer 31 may be the same or different.

[0087] For example, the thickness of the second conductive layer 32 may be greater than the thickness of the first conductive layer 31 and the third conductive layer 33. Figure 2 As shown. In this way, a multi-layer conductive structure with a thick middle and thin sides is achieved, which can reduce the parasitic resistance of the inductor 3 during operation, increase the inductor Q value without changing the area of ​​the inductor 3, and improve the operating performance of the inductor and the integrated passive device. In addition, the thickness of the outermost conductive layer is made thin to prevent the outermost conductive layer from peeling off during the preparation of the integrated passive device, thereby improving the manufacturing yield of the integrated passive device. In some embodiments, the thickness of the second conductive layer 32 is 1.5 to 2 times the thickness of the third conductive layer 33, as shown in FIG. Figure 2 When the thickness of the second conductive layer 32 is less than 1.5 times the thickness of the third conductive layer 33, the parasitic resistance generated in the inductor's middle layer is not significantly improved. When the thickness of the second conductive layer 32 is greater than twice the thickness of the third conductive layer 33, the large differences in the film layers can easily cause film peeling during the fabrication process of the multi-layer inductor, reducing the reliability of the inductor's film layers.

[0088] For another example, the thickness of the first conductive layer 31 may be greater than the thickness of the second conductive layer 32, and the thickness of the second conductive layer 32 may be greater than the thickness of the third conductive layer 33. Figure 3 As shown in the figure, a multi-layer conductive structure with gradually decreasing thickness from bottom to top is achieved, with the first conductive layer 31 at the bottom having the greatest thickness. This reduces the parasitic resistance of the inductor 3 and the risk of film delamination, thereby improving the performance of the inductor 3. In some embodiments, the thickness of the first conductive layer 31 is 1.5 to 2 times that of the second conductive layer 32. This further improves the quality factor of the inductor while ensuring that the film delamination does not occur.

[0089] For example, Figure 4 As shown, a four-layer inductor 3 is used as an example. The inductor 3 comprises four alternating conductive and insulating layers. A first conductive layer 31, a second conductive layer 32, a third conductive layer 33, and a fourth conductive layer 34 are sequentially arranged on one side of the substrate 1. Each conductive layer is covered by insulating layers P1, P2, P3, and P4, respectively. During the fabrication of the inductor 3, the conductive layers are fabricated in the following order: first conductive layer 31, second conductive layer 32, third conductive layer 33, and fourth conductive layer 34.

[0090] In some embodiments, the thickness of the fourth conductive layer 34 is thinner than the thicknesses of the first conductive layer 31, the second conductive layer 32, and the third conductive layer 33. By increasing the thickness of the conductive layers in the inductor 3 while ensuring a higher inductance, the Q value of the inductor 3 is improved. Furthermore, by making the outermost conductive layer of the inductor thinner, the phenomenon of outer film peeling, which is easily caused by a multi-layer structure, is avoided.

[0091] In other embodiments, the thickness of the fourth conductive layer 34 is smaller than the thicknesses of the first conductive layer 31 , the second conductive layer 32 and the third conductive layer 33 , and the thickness of the third conductive layer 33 is smaller than the thicknesses of the first conductive layer 31 and the second conductive layer 32 .

[0092] In some other embodiments, the thicknesses of the first conductive layer 31, the second conductive layer 32, the third conductive layer 33, and the fourth conductive layer 34 decrease in sequence. Specifically, the thickness of the fourth conductive layer 34 is thinner than the thicknesses of the first conductive layer 31, the second conductive layer 32, and the third conductive layer 33; the thickness of the third conductive layer 33 is thinner than the thicknesses of the first conductive layer 31 and the second conductive layer 32; and the thickness of the second conductive layer 32 is thinner than the thickness of the first conductive layer 31. To achieve a high inductance value for the multilayer inductor 3, the inductor Q value can be improved by adjusting the thickness of the conductive layers.

[0093] In practical applications, the inductance requirements for inductor 3 vary. To achieve a higher inductance, the number of inductor coil layers can be increased. Maintaining a high Q value while maintaining multiple conductive layers and a high inductance is a major challenge in the fabrication of passive components. This application achieves an inductor 3 with a higher Q value by increasing the thickness of the conductive layer in inductor 3.

[0094] In the embodiment of the present disclosure, the conductive layer in the inductor 3 is in a strip structure, and the strip widths of the conductive layer can be different.

[0095] For example, a two-layer inductor includes a first conductive layer 31 disposed on one side of a substrate 1; a second conductive layer 32 disposed on a side of the first conductive layer 31 away from the substrate 1, with the first and second conductive layers 31 and 32 having different thicknesses; a first insulating layer P1 disposed between the first and second conductive layers 31 and 32; and at least one first connecting portion 51 extending through the first insulating layer P1 to electrically connect the first and second conductive layers 31 and 32. The width of the second conductive layer 32 is greater than that of the first conductive layer 31. By increasing the cross-section of the second conductive layer 32, the parasitic resistance is reduced, further improving the quality factor of the inductor.

[0096] Figure 5 A three-dimensional diagram of a passive device according to an embodiment of the present disclosure is shown. For clarity, only the conductive structure of the passive device, namely the conductive layer and the connecting portion, is shown in the figure.

[0097] like Figure 5 As shown, the inductor includes a first conductive layer 31, a second conductive layer 32, and a third conductive layer 33, as well as a first connecting portion 51 and a second connecting portion 52 located between the conductive layers. The first conductive layer 31, the second conductive layer 32, and the third conductive layer 33 are all arranged in a strip structure, and the width of the strip is the width perpendicular to the extending direction of the strip in the plane where the conductive layer is located. Figure 5 As shown, the width of the third conductive layer 33 is greater than that of the first conductive layer 31 and the second conductive layer 32. This arrangement increases the cross-sectional area of ​​the conductive layer, reduces parasitic resistance, and improves inductance quality without increasing the thickness of the film layer. Furthermore, it increases the contact area between the outermost conductive layer (the third conductive layer 33 in this embodiment) and the underlying insulating layer, preventing film peeling in the multilayer inductor structure.

[0098] In some embodiments, the width of the third conductive layer 33 is 1.5 to 2 times the width of the second conductive layer 32. When the width of the third conductive layer 33 is less than 1.5 times the width of the second conductive layer 32, the performance of the inductor is not significantly improved. When the width of the third conductive layer 33 is greater than 2 times the width of the second conductive layer 32, the projected area of ​​the conductive layer on the insulating layer 4 increases, affecting the horizontal uniformity of the conductive layer and thus affecting the performance of the inductor. The embodiments of the present disclosure achieve a good balance between the above two aspects by setting the width of the third conductive layer 33 to 1.5 to 2 times the width of the second conductive layer 32, thereby improving the performance of the inductor.

[0099] In other embodiments, Figure 6 As shown, the width of the third conductive layer 33 can be greater than the width of the first conductive layer 31 and the second conductive layer 32, and the width of the second conductive layer 32 can be greater than the width of the first conductive layer 31. By increasing the cross-sectional area of ​​the second conductive layer 32, the Q value of the inductor structure can be improved. For example, the width of the third conductive layer 33 and the width of the second conductive layer 32 are 1.5 to 2 times the width of the first conductive layer 31. When the width of the third conductive layer 33 and the width of the second conductive layer 32 are less than 1.5 times the width of the first conductive layer 31, the performance of the inductor is not significantly improved; when the width of the third conductive layer 33 and the width of the second conductive layer 32 are greater than 2 times the width of the first conductive layer 31, the projected area of ​​the conductive layer on the insulating layer 4 increases, affecting the horizontal uniformity of the conductive layer, thereby affecting the performance of the inductor. The embodiment of the present disclosure achieves a good balance between the above two aspects by setting the width of the third conductive layer 33 and the width of the second conductive layer 32 to 1.5 to 2 times the width of the first conductive layer 31, thereby improving the performance of the inductor.

[0100] According to the embodiments of the present disclosure, the thickness of the insulating layer can be set as needed. In some embodiments, the thickness of the first insulating layer P1 is 1 to 2.5 times the thickness of the first conductive layer 31 to prevent the distance between the first conductive layer 31 and the second conductive layer 32 from being too small, thereby generating parasitic resistance and reducing the inductance quality. In other embodiments, the thickness of the second insulating layer P2 is 1 to 2.5 times the thickness of the second conductive layer 32 to prevent the distance between the second conductive layer 32 and the third conductive layer 33 from being too small, thereby generating parasitic resistance and reducing the inductance quality.

[0101] Figure 7 A cross-sectional view of a passive component according to an embodiment of the present disclosure is shown.

[0102] like Figure 7 As shown, the inductor is configured as a three-layer conductive structure, including a first conductive layer 31 , a second conductive layer 32 and a third conductive layer 33 , and first to third insulating layers P1 , P2 , P3 and first to third connecting portions 51 , 52 , 53 located therebetween.

[0103] On a side of the first conductive layer 31 away from the base substrate 11, at least one first blind hole 512 is provided, corresponding one-to-one with at least one first connecting portion 5151. The orthographic projection of the first blind hole 512 on the base substrate 1 is within the orthographic projection of the first via hole 511 on the base substrate 1. A portion of the first connecting portion 51 is disposed within the first via hole 511, while another portion of the first connecting portion 51 is disposed within the first blind hole 512. In this manner, the portion of the first connecting portion 51 located within the first blind hole 512 is surrounded by the material of the first conductive layer 31, enabling better contact between the first connecting portion 51 and the first conductive layer 31, improving the electrical connection reliability of the inductor structure, and thereby improving the quality factor of the inductor.

[0104] After preparing the first blind hole 512, the first connecting portion 51 can be further prepared by photolithography technology, so as to remove the material of the residual insulating layer 4 or the formed metal oxide on the surface of the lower conductive layer connected to the first connecting portion 51, thereby improving the electrical connection performance between the first connecting portion 51 and the lower connected conductive layer, reducing the contact resistance of the via structure 5 between the conductive layers, and improving the performance of the inductor.

[0105] In some embodiments, the depth of the first blind hole 512 is less than 15% of the thickness of the first conductive layer 31. This can prevent the thickness of the first conductive layer 31 at the blind hole from being reduced due to the first blind hole being too deep, thereby reducing the inductance quality factor.

[0106] For example, the depth of the first blind hole 512 can be greater than 50 nm, and the thickness of the oxide generated on the surface of the first conductive layer 31 is relatively thin, which can effectively improve the electrical connection between the first conductive layer 31 and the second conductive layer 32 and improve the inductance quality.

[0107] For example, the depth of the first blind hole 512 may be less than 400 nm, which can effectively improve the electrical connection between the first conductive layer 31 and the second conductive layer 32, improve the inductance quality, and save process time.

[0108] For example, the depth of the first blind hole 512 can be less than 100 nm. During the manufacturing process of the inductor structure, the thickness of the oxide generated on the surface of the first conductive layer 31 is relatively thin. The depth of the first blind hole 512 is less than 100 nm, which can improve the electrical connection performance between the conductive layer and the first connecting portion 51.

[0109] For example, the depth of the first blind hole 512 is in the range of 100 to 200 nm. During the manufacturing process of the inductor structure, it is ensured that the oxide generated on the surface of the first conductive layer 31 is removed as much as possible, thereby improving the inductor quality by improving the electrical connection.

[0110] For example, the depth of the first blind hole 512 is in the range of 200-400 nm. During the manufacturing process of the inductor structure, it is ensured that the oxide thickness generated on the surface of the first conductive layer 31 is completely removed, thereby improving the inductor quality by improving the electrical connection.

[0111] In the embodiments of the present disclosure, Figure 7 As shown, the inductor 3 further includes a first transition layer 540, which is disposed on a side of the first conductive layer 31 close to the substrate 1, and the first conductive layer 31 covers the first transition layer 540. The first transition layer 540 includes a first adhesion layer 541 and a first seed layer 542, and the first seed layer 542 is disposed on a side of the first adhesion layer 541 away from the substrate 1.

[0112] In the embodiments of the present disclosure, Figure 7 As shown, the inductor 3 further includes a second transition layer 550, which is disposed on the sidewalls of the first via 511, the bottom and sidewalls of the first blind hole 512, and the side of the first insulating layer P1 away from the base substrate. The second conductive layer 32 covers the second transition layer 550. The second transition layer 550 connects the second conductive layer 32 away from the base substrate 1 and the first connecting portion 51, improving the stability of the second conductive layer 32, preventing delamination of the second conductive layer 32, and ensuring the density of the prepared second conductive layer 32.

[0113] The second transition layer 550 may include a second adhesion layer 551 and a second seed layer 552. The second seed layer 552 is disposed on the side of the second adhesion layer 551 away from the base substrate 1. The second adhesion layer 551 prevents the first connecting portion 51 and the second conductive layer 32 from peeling off during the fabrication process. The second seed layer 552 is disposed on the side of the second adhesion layer 551 away from the base substrate 1. This makes the fabricated second conductive layer 32 more compact, and the first connecting portion 51 fills the first via 511 and the first blind hole 512.

[0114] In the embodiment of the present disclosure, Figure 7 As shown, the aperture variation rate of the first via hole 511 is smaller than that of the first blind hole 512 as it moves away from the substrate 1. For example, the apertures of the first via hole 511 and the first blind hole 512 can gradually increase as they move away from the substrate 1. This is due to uneven energy distribution along the laser beam's extension direction during photolithography processes, such as laser etching. By making the aperture variation rate of the first via hole 511 smaller than that of the first blind hole 512, the electrical connection between the first connecting portion 51 and the first conductive layer 31 is further improved, thereby enhancing the quality factor of the inductor.

[0115] like Figure 7 At least one second via 521 is provided in the second insulating layer P2, corresponding one-to-one with the second connecting portion 52. At least a portion of the second connecting portion 52 is disposed within the second via 521. The orthographic projections of the first connecting portion 51 and the second connecting portion 52 on the substrate do not overlap. A portion of the second connecting portion 52 is disposed within the second via 521, while another portion of the second connecting portion 52 is disposed within a second blind via 522. The provision of the second blind via 522 ensures better contact between the second connecting portion 52 and the second conductive layer 32, further improving the electrical connection reliability of the inductor structure and, consequently, the quality factor of the inductor.

[0116] In the embodiments of the present disclosure, Figure 7 As shown, the inductor also includes a third transition layer 560, which is disposed on the sidewalls of the second via 521, the bottom and sidewalls of the second blind hole 522, and the side of the second insulating layer P2 away from the base substrate. The third conductive layer 33 covers the third transition layer 560. The third transition layer 560 includes a third adhesion layer 561 and a third seed layer 562. The third seed layer 562 is disposed on the side of the third adhesion layer 561 away from the base substrate 1. The third transition layer 560 connects the third conductive layer 33 away from the base substrate 1 and the second connecting portion 52, improving the stability of the third conductive layer 33, preventing delamination of the third conductive layer 33, and ensuring the density of the prepared third conductive layer 33.

[0117] In some embodiments, the orthographic projection of the first connecting portion 51 between the first conductive layer 31 and the second conductive layer 32 on the substrate 1 does not overlap with the orthographic projection of the second connecting portion 52 between the second conductive layer 32 and the third conductive layer 33 on the substrate 1. Maintaining a certain distance between the orthographic projections of the first connecting portion 51 and the second connecting portion 52 on the substrate 1 can prevent the problem of poor horizontal uniformity of the conductive layer caused by the via structure, thereby improving the quality and performance of the inductor structure.

[0118] For example, the distance between the first connecting portion 51 and the second connecting portion 52 is greater than 15 to 50 μm. Here, the distance between the connecting portions can be the distance between the geometric centers of the two. For example, the first connecting portion 51 and the second connecting portion 52 can be set as a columnar structure, and the distance between the first connecting portion 51 and the second connecting portion 52 can be defined as the distance between the central axes of the columnar structure. In some embodiments, as Figures 2 to 7 As shown, the central axes of the first connecting portion 51 located between the first conductive layer 31 and the second conductive layer 32 and the second connecting portion 52 located between the second conductive layer 32 and the third conductive layer 33 are parallel but do not intersect, and the distance between the first connecting portion 51 and the second connecting portion 52 is greater than 15 to 50 μm.

[0119] like Figure 8 As shown, the first via hole 511 has a slope angle α, and the first blind hole 512 has a slope angle β. The so-called slope angle here refers to the angle between the side wall of the hole and the direction parallel to the substrate (horizontal direction in the figure). The slope angle α of the first via hole 511 can be greater than the slope angle β of the first blind hole 512. For example, the slope angle (α) of the first via hole 511 ranges from 20° to 90°. The slope angle β of the first blind hole 512 can range from 30° to 60°. This can remove the surface insulating layer 4 material or metal oxide of the first conductive layer 31 connected to the first connecting portion 51 as cleanly as possible.

[0120] In some embodiments, the slope angle α of the first via 511 is in the range of 70±5°. The first via 511 can be formed by a photolithography process, such as laser drilling. When the slope angle of the first via 511 is less than 20°, it is easy to cause film peeling. In the embodiments of the present disclosure, by setting the slope angle α of the first via 511 to be in the range of 70±5°, the sidewall of the via is as vertical as possible within process constraints, thereby minimizing the risk of film peeling.

[0121] exist Figure 8 In the embodiment, the surface of the second transition layer 550 in the first blind hole 512, which is away from the base substrate 1 (the upper surface in the figure), is recessed relative to the surface of the first conductive layer 31, which is away from the base substrate 1 (the upper surface in the figure). However, the embodiments of the present disclosure are not limited thereto, and the former may be flush with the latter or raised relative to the latter.

[0122] like Figure 9 As shown, the distance between the upper surface of the second transition layer 550 and the first surface S1 of the substrate 1 is equal to the thickness of the first conductive layer 31. This removes as much oxide as possible from the surface of the first conductive layer 31, thereby improving the electrical connection between the first conductive layer 31 and the first connecting portion 51.

[0123] like Figure 10As shown, the distance between the upper surface of the second transition layer 550 and the first surface S1 of the substrate 1 is higher than the thickness of the first conductive layer 31. While removing the oxide on the surface of the first conductive layer 31, the uniformity of the overall thickness of the first conductive layer 21 is improved to ensure the inductance quality.

[0124] In the embodiment of the present disclosure, the aperture of the first via 511 is positively correlated with the thickness of the second conductive layer 32. Compared with the case where the second conductive layer 32 and the first conductive layer 31 have the same thickness, when the thickness of the second conductive layer 32 is greater than that of the first conductive layer 31, the size of the first via 511 increases accordingly, and the size of the corresponding first connecting portion 51 increases, thereby preventing the second conductive layer 32 from easily peeling off. In some embodiments, the aperture of the first via 511 may be related to other dimensions of the second conductive layer 32, such as length, width, etc. In some embodiments, the first conductive layer 31 and the second conductive layer 32 are configured as a strip structure, for example Figure 5 and Figure 6 In this case, the diameter of the first via hole 511 may be positively correlated with the strip width of the second conductive layer 32. The strip width here refers to the width perpendicular to the strip extension direction.

[0125] In some embodiments, the first aperture 501 of the first via 511 is 3 to 6 times the thickness of the second conductive layer 32. When the first aperture 501 of the first via 511 is greater than or equal to 3 times the thickness of the second conductive layer 32, the mechanical reliability of the second conductive layer 32 is significantly improved. When the first aperture 501 of the first via 511 is less than or equal to 6 times the thickness of the second conductive layer 32, the thickness uniformity of the second conductive layer 32 is ensured, thereby reducing the inductance quality factor.

[0126] For example, Figure 11 As shown, taking a three-layer inductor as an example, when the thickness of the second conductive layer 32 is greater than that of the first conductive layer 31 and the third conductive layer 33, the size of the first via 511 is larger than that of the second via 521, and the difference between the first aperture 501 of the first via 511 and the second aperture 532 of the second via 521 is 15 to 30 μm. When the difference between the first aperture 501 and the second aperture 532 of the second via 521 is greater than 15 μm, the second conductive layer 32 is significantly prevented from delamination. When the difference between the first aperture 501 and the second aperture 532 of the second via 521 is less than 30 μm, there is sufficient space for the conductive layer, ensuring the uniformity of the thickness of the second conductive layer 32 and improving the quality factor of the inductor 3.

[0127] For example, compared with the second conductive layer 32 and the first conductive layer 31 having the same width, when the width of the second conductive layer 32 is greater than the width of the first conductive layer 31, the size of the first via 511 increases accordingly, and the size of the corresponding first connecting portion 51 increases, thereby preventing the second conductive layer 32 from easily peeling off.

[0128] For example, the size of the first aperture 501 of the first via 511 is 3 to 6 times the width of the second conductive layer 32. When the size of the first aperture 501 of the first via 511 is greater than or equal to 3 times the width of the second conductive layer 32, the mechanical reliability of the second conductive layer 32 is significantly improved. When the size of the first aperture 501 of the first via 511 is less than or equal to 6 times the width of the second conductive layer 32, the width uniformity of the second conductive layer 32 is ensured and the inductance quality factor is improved.

[0129] For example, in a three-layer inductor, when the width of the second conductive layer 32 is greater than the widths of the first and third conductive layers 31 and 33, and the size of the first via 511 is greater than the size of the second via 521, the difference between the first aperture 501 of the first via 511 and the second aperture 532 of the second via 521 is 15 to 30 μm. When the difference between the first aperture 501 and the second aperture 532 of the second via 521 is greater than or equal to 15 μm, the second conductive layer 32 is significantly prevented from delamination. When the difference between the first aperture 501 and the second aperture 532 of the second via 521 is less than or equal to 30 μm, the uniformity of the width of the second conductive layer 32 is ensured, improving the quality factor of the inductor 3.

[0130] For example, Figure 12 As shown, when the width of the third conductive layer 33 is greater than the widths of the second conductive layer 32 and the first conductive layer 31 , the size of the second via 521 is greater than the size of the first via 511 , thereby preventing the film of the third conductive layer 33 from peeling off.

[0131] In other embodiments, the first conductive layer 31 and the second conductive layer 32 are arranged in a strip structure, and the thickness of the first transition layer 540 is positively correlated with the width of the second conductive layer 32. When the width of the second conductive layer 32 is greater than the width of the first conductive layer 31, the thickness of the second transition layer 550 is greater than the thickness of the first transition layer 540. This can prevent film peeling caused by the increased width of the second conductive layer 32. When the third conductive layer 33 is thicker than the second conductive layer 32 and / or the first conductive layer 31, the thickness of the third transition layer 560 is greater than the thickness of the first transition layer 540 and / or the second transition layer 550, preventing film peeling of the third conductive layer 33 during preparation and use.

[0132] For example, Figure 12As shown, the first conductive layer 31, the second conductive layer 32, and the third conductive layer 33 are arranged in a strip structure, and the thickness of the first transition layer 540 is positively correlated with the thickness of the second conductive layer 32. When the thickness of the second conductive layer 32 is greater than the thickness of the first conductive layer 31 and / or the third conductive layer 33, the thickness of the second transition layer 550 is greater than the thickness of the first transition layer 540 and / or the third transition layer 560, thereby preventing the second conductive layer 32 from easily peeling off as the thickness of the second conductive layer 32 increases.

[0133] For example, the thickness of the second transition layer 550 is 1.25 to 2×10 -2 times, or the thickness of the third transition layer 560 is 1.25 to 2×10 times the thickness of the third conductive layer 33 -2 When the conductivity of the transition layer is lower than that of the conductive layer, the conductive layer is controlled within a suitable range to ensure stable electrical connection performance between the conductive layers and improve the inductance performance.

[0134] Reference below Figures 13 to 19 Several examples of inductance in passive devices according to embodiments of the present disclosure are described.

[0135] like Figures 13 to 19 As shown, in the embodiment of the present disclosure, the orthographic projection of the first conductive layer 31 on the base substrate 1 is a first annular pattern having a first opening, and the orthographic projection of the second conductive layer 32 on the base substrate 1 is a second annular pattern having a second opening. The proportion of the first opening in the first annular pattern and the proportion of the second opening in the second annular pattern are both greater than one-half.

[0136] In the embodiment of the present disclosure, the above-mentioned annular pattern is a symmetrical pattern, the conductive layer of the inductor is a strip structure, and the projection of the graphic on the substrate is a part of the symmetrical pattern, which is beneficial for the inductor to have a more uniform inductance distribution during operation and further improve the inductor quality.

[0137] As an example, the centrally symmetrical pattern can be circular or polygonal. When the symmetrical pattern is a polygon, the internal angle of the polygon is greater than or equal to 90°. When the angle is less than 90°, the outer edge of the conductive layer at the angle is far from the central axis of the conductive layer, which can easily lead to poor consistency of the conductive layer, thereby affecting the performance of the inductor. The embodiments of the present disclosure can avoid this problem by setting the internal angle of the polygon to be greater than 90°.

[0138] exist Figure 13In the figure, the orthographic projection of the first conductive layer 31, the second conductive layer 32, and the third conductive layer 33 on the base substrate 1 is a symmetrical quadrilateral with an opening, such as a rectangle or a square, and the opening occupies two adjacent sides of the quadrilateral. The routing angle of the first conductive layer 31, the second conductive layer 32, and the third conductive layer 33 is 90°; in some embodiments, the quadrilateral can be set as a rounded quadrilateral. The first conductive layer 31 and the second conductive layer 32 are connected by a first connecting portion 51, and the second conductive layer 32 and the third conductive layer 33 are connected by a second connecting portion 52; the orthographic projection of the first conductive layer 31 and the second conductive layer 32 on the base substrate 1 overlap, and the orthographic projection of the second conductive layer 32 and the third conductive layer 33 on a plane perpendicular to the thickness direction of the conductive layers overlap; the orthographic projections of the first connecting portion 51 and the second connecting portion 52 on the base substrate 1 do not overlap.

[0139] For example, Figure 14 As shown, taking a three-layer inductor structure as an example, the orthographic projections of the first conductive layer 31, the second conductive layer 32, and the third conductive layer 33 on the substrate 1 are symmetrical quadrilaterals with an opening, such as a rectangle or square, with the opening occupying one side of the quadrilateral. The routing angle between the first conductive layer 31, the second conductive layer 32, and the third conductive layer 33 is 90°; in some embodiments, the quadrilateral can be configured as a rounded quadrilateral. The first conductive layer 31 and the second conductive layer 32 are connected by a first connecting portion 51, and the second conductive layer 32 and the third conductive layer 33 are connected by a second connecting portion 52. The orthographic projections of the first conductive layer 31 and the second conductive layer 32 on the substrate 1 overlap, while the orthographic projections of the second conductive layer 32 and the third conductive layer 33 on the substrate 1 overlap. The orthographic projections of the first connecting portion 51 and the second connecting portion 52 on the substrate 1 do not overlap.

[0140] For example, Figure 15 As shown, taking a three-layer inductor structure as three examples, the orthographic projection patterns of the first conductive layer 31, the second conductive layer 32, and the third conductive layer 33 on the base substrate 1 are seven-eighths of a symmetrical octagonal structure, and the routing angle between the first conductive layer 31, the second conductive layer 32, and the third conductive layer 33 is 135°; the first conductive layer 31 and the second conductive layer 32 are connected by the first connecting portion 51, and the second conductive layer 32 and the third conductive layer 33 are connected by the second connecting portion 52; the first conductive layer 31 and the second conductive layer 32 overlap in their orthographic projections on the base substrate 1, and the second conductive layer 32 and the third conductive layer overlap in their orthographic projections on the base substrate 1; the orthographic projections of the first connecting portion 51 and the second connecting portion 52 on the base substrate 1 do not overlap.

[0141] In the disclosed embodiment, the orthographic projection of the first conductive layer 31 on the substrate 1 forms a ring-shaped pattern with a first opening, and the orthographic projection of the second conductive layer 32 on the substrate 1 forms a ring-shaped pattern with a second opening. The first opening and the second opening face different directions. This reduces the overlapping area of ​​the orthographic projections of the first and second conductive layers 31, 32 on the substrate 1, lowering the parasitic resistance of the first and second conductive layers 31, 32 during operation and improving the inductor quality.

[0142] For example, in a three-layer inductor 3, the orthographic projection of the first conductive layer 31 on the substrate 1 forms a first ring-shaped pattern with a first opening, the orthographic projection of the second conductive layer 32 on the substrate 1 forms a second ring-shaped pattern with a second opening, and the orthographic projection of the third conductive layer 33 on the substrate 1 forms a third ring-shaped pattern with a third opening. The first, second, and third openings face different directions. This further reduces the overlapping area of ​​the orthographic projections of the first, second, and third conductive layers 31, 32, and 33 on the substrate 1, thereby lowering the parasitic resistance of the first, second, and third conductive layers 31, 32, and 33 during operation and improving the inductor quality.

[0143] In the disclosed embodiment, the first annular pattern and the second annular pattern have the same shape but different sizes. Parasitic resistance is easily generated between adjacent conductive layers during operation, resulting in a decrease in the inductance and Q value of the inductor, thereby affecting the operational reliability of the entire integrated passive device. For example, during the operation of a filter, the parasitic resistance generated by the adjacent conductive layers can cause changes in the filter frequency band, making it impossible to achieve a good filtering effect. By adjusting the orthographic projection relationship of the conductive layer of the inductor 3 on the substrate 1, the parasitic resistance between the conductive layers can be reduced, thereby improving the quality of the inductor.

[0144] Exemplarily, the width of the second ring pattern is greater than the width of the first ring pattern, and the width is the distance between the inner ring and the outer ring of the ring pattern. As described above, by increasing the width of the second conductive layer 32 of the strip structure, the parasitic resistance during operation of the inductor can be reduced and the inductor quality can be improved.

[0145] Exemplarily, the width of the first ring-shaped pattern is greater than the width of the second ring-shaped pattern, which can also reduce the parasitic resistance of the inductor.

[0146] Furthermore, taking a three-layer inductor as an example, the width of the third ring pattern is greater than the width of the second ring pattern, which can improve the quality factor of the multi-layer inductor.

[0147] For example, the first annular pattern, the second annular pattern and the third annular pattern have the same shape but different sizes, for example, Figure 6This can minimize the overlapping area of ​​the orthographic projections of the first conductive layer 31 , the second conductive layer 32 , and the third conductive layer 33 on the substrate 1 , further improving the quality factor of the three-layer inductor 3 .

[0148] For example, Figure 17 As shown, taking a three-layer inductor 3 as an example, the orthographic projection pattern of at least one of the first conductive layer 31 and the second conductive layer 32 on the substrate 1 is a part of a circle, the orthographic projection of the first conductive layer 31 on the substrate 1 has a first annular pattern, the orthographic projections of the second conductive layer 32 and the third conductive layer 33 on the substrate 1 have a second annular pattern, and the orthographic projections of the third conductive layer 33 and the third conductive layer 33 on the substrate 1 have a third annular pattern. Among them, the size of the second annular pattern is smaller than the size of the first annular pattern and the third annular pattern, and the so-called size here is the diameter of the ring. However, the embodiments of the present disclosure are not limited to this, and the size can also be the width of the ring (the distance between the inner diameter and the outer diameter) or the area of ​​the ring, etc. In this way, the problem of deterioration of the inductor quality caused by the parasitic resistance between adjacent conductive layers can be avoided.

[0149] For example, Figure 18 As shown, taking a three-layer inductor 3 as an example, the orthographic projection of at least one of the first conductive layer 31 and the second conductive layer 32 on the substrate 1 is a portion of a circle. The orthographic projection of the first conductive layer 31 on the substrate 1 has a first annular pattern, the orthographic projections of the second conductive layer 32 and the third conductive layer 33 on the substrate 1 have a second annular pattern, and the orthographic projections of the third conductive layer 33 and the third conductive layer 33 on the substrate 1 have a third annular pattern. The second annular pattern is larger than the first and third annular patterns, thereby preventing the problem of inductor quality degradation caused by parasitic resistance between adjacent conductive layers.

[0150] For example, Figure 19 As shown, taking a three-layer inductor 3 as an example, the orthographic projection of at least one of the first conductive layer 31 and the second conductive layer 32 on the base substrate 1 is a portion of a circle. The orthographic projection of the first conductive layer 31 on the base substrate 1 has a first annular pattern, the orthographic projections of the second conductive layer 32 and the third conductive layer 33 on the base substrate 1 have a second annular pattern, and the orthographic projections of the third conductive layer 33 and the third conductive layer 33 on the base substrate 1 have a third annular pattern. The second annular pattern is larger than the first annular pattern, and the third annular pattern is larger than the second annular pattern. This prevents the problem of inductor quality degradation caused by parasitic resistance between adjacent conductive layers.

[0151] Furthermore, the geometric centers (eg, centers of circles) of the first annular pattern, the second annular pattern, and the third annular pattern may overlap or not overlap, and adjustments may be made based on actual conditions.

[0152] In the disclosed embodiment, at least one of the first conductive layer 31 and the second conductive layer 32 in the same layer has a protrusion 530 in a direction parallel to the base substrate 1 , and the protrusion 530 is connected to the first connection portion 51 . The protrusion 53 is fabricated in the same layer as the conductive layer, which reduces the process and enables the connection of conductive layers of different sizes.

[0153] like Figures 17 to 19 As shown, taking a three-layer inductor as an example, one or more of the first to third conductive layers may have a protrusion. Taking the second conductive layer 32 as an example, it has a protrusion in a direction parallel to the base substrate 1, and the protrusion includes a first protrusion 501 and a second protrusion 502. The first protrusion 501 is connected to the first connection part 51, and the second protrusion 502 is connected to the second connection part 52. According to actual conditions, the position of the protrusion relative to the same conductive layer is adjusted. For example, Figure 17 and Figure 19 In the figure, the protruding portion of the second conductive layer 32 is outside the circle of the orthographic projection of the second conductive layer 32 on the base substrate 1; Figure 18 In the figure, the protruding portion of the second conductive layer 32 is within the circular ring of the orthographic projection of the second conductive layer 32 on the base substrate 1 .

[0154] The present disclosure provides an integrated passive device. Figures 20 to 23 As shown, the integrated passive device includes the aforementioned passive devices and capacitor 2, which is electrically connected to the first conductive layer 31 of inductor 3. Capacitor 2 and inductor 3 are connected in series to form an integrated passive device circuit, which can be used in integrated passive devices such as filters and duplexers.

[0155] Capacitor 2 may include a first electrode 21 disposed on one side of substrate 1, a second electrode 23 disposed on a side of first electrode 21 away from substrate 1, and a first dielectric layer 22 disposed between first electrode 21 and second electrode 23. The orthographic projections of first electrode 21, first dielectric layer 22, and second electrode 23 on substrate 1 at least partially overlap. The overlapping projection area of ​​first electrode 21, first dielectric layer 22, and second electrode 23 on substrate 1 determines the capacitance of capacitor 2.

[0156] For example, Figure 20 As shown, a first trace 302 and a second trace 303 are provided on the side of the capacitor 2 away from the base substrate 1. The first trace 302 and the second conductive layer 32 are on the same layer, and the second trace 303 and the third conductive layer 33 are on the same layer. The third connecting portion 53 penetrates the insulating layer P2 to connect the second electrode 23 and the first trace 302. The fourth connecting portion 54 penetrates the insulating layer P3 to connect the first trace 302 and the second trace 303. The orthographic projections of the third connecting portion 53 and the fourth connecting portion 54 on the base substrate 1 do not overlap.

[0157] For example, Figure 20 As shown, the integrated passive device 100 further includes a fifth connecting portion 55 and a sixth connecting portion 56 , which penetrate the third insulating layer P3 to connect different bumps 6 , and the bumps 6 are connected to different solder balls 7 , which are used to connect to external circuits.

[0158] The connection between the first trace 302 and the second trace 303 can be used for signal connection and can also be used to form an inductor 3 , which is connected to the second electrode 23 of the capacitor 2 .

[0159] For example, Figure 20 As shown, the inductor 3 and capacitor 2 are arranged on the same side of the base substrate 1, and the first conductive layer 31 of the inductor 3 and the first electrode 21 of the capacitor 2 are arranged on the same layer and electrically connected. This structure simplifies the manufacturing process and saves process steps. The first conductive layer 31 and the first electrode 21 are formed on the surface of the base substrate 1 and connected in the same layer. The first conductive layer 31 and the first electrode 21 are more flat, and the electrical connection performance is more stable, which is conducive to improving the reliability of the integrated passive device circuit. At the same time, the overall thickness of the integrated passive device 100 is reduced, preventing the problem of film peeling that is easily caused by the integrated passive device 100 with multiple layers.

[0160] In some embodiments, the thickness of the first electrode 21 is the same as the thickness of the first conductive layer 31, and the thickness of the first electrode 21 is greater than the thickness of the second electrode 22. As the thickness of the first conductive layer 31 increases, the high-temperature structural stability of the first electrode 21 is improved, which can prevent the problem of reduced consistency of the capacitor 2 caused by deformation of the first electrode 21 during high-temperature processes.

[0161] For example, Figure 21 As shown, the inductor 3 and the capacitor 2 are arranged on the same side of the base substrate 1, and the first electrode 21 and the first conductive layer 31 are arranged in the same layer. The thickness of the first electrode 21 is the same as that of the first conductive layer 31, and the thickness of the first electrode 21 is greater than that of the second electrode 22. A first trace 302 and a second trace 303 are arranged on the side of the capacitor 2 away from the base substrate 1. The first trace 302 and the second conductive layer 32 are in the same layer, and the second trace 303 and the third conductive layer 33 are in the same layer and electrically connected. The connection between the capacitor 2 and the inductor 3 can be achieved through the third conductive layer 33. Among them, the bumps 6 and solder balls 7 for signal connection are set according to actual conditions.

[0162] For example, Figure 22 As shown, the thickness of the second conductive layer 32 is greater than the thickness of the first conductive layer 31 and the second conductive layer 32. By increasing the thickness of the second conductive layer 32, the quality factor of the inductor is improved.

[0163] For example, Figure 23As shown, the thickness of the first conductive layer 31 is greater than that of the second conductive layer 32 , and the thickness of the second conductive layer 32 is greater than that of the third conductive layer 33 , thereby further improving the quality factor of the inductor.

[0164] For example, a two-layer inductor 3 is used as an example. The inductor 3 includes a first conductive layer 31 and a second conductive layer 32. The first conductive layer 31 and the first electrode 21 are fabricated on the same layer, and the thickness of the first electrode 21 is greater than that of the second electrode 23. The first electrode 21 and the first conductive layer 31 can be electrically connected to achieve a series connection between the capacitor 2 and the inductor 3; alternatively, the second conductive layer 32 and the first trace 302 can be provided on the same layer and electrically connected to achieve a series connection between the capacitor 2 and the inductor 3.

[0165] Furthermore, the fifth and sixth connecting portions 55 and 56 penetrate the second insulating layer P2 and connect to different bumps 6 on the side of the second insulating layer P2 away from the substrate. The bumps 6 are connected to solder balls 7 for connecting to external circuits. The number and position of the bumps 6 and solder balls 7 are designed based on actual conditions.

[0166] The present disclosure provides a method for preparing an integrated passive device. The method is applicable to preparing the integrated passive device of any of the above embodiments. Figures 20 to 23 To describe the various steps of the preparation method.

[0167] Step 1601 : forming a first electrode 21 and a first conductive layer 31 on one side of a base substrate 1 .

[0168] Exemplarily, the patterns of the first electrode 21 and the first conductive layer 31 are formed by an additive method: a whole-surface photoresist is coated on one side of the first surface S1 of the substrate 1, and then the photoresist is exposed and developed using a mask to form a photoresist pattern corresponding to the area and thickness of the first electrode 21 and the first conductive layer 31, and then an electroplating process is performed to form a first conductive layer 31 pattern on the side of the insulating layer 4 away from the substrate 1.

[0169] Exemplarily, the pattern of the first electrode 21 and the first conductive layer 31 is formed by a subtractive method: the first conductive layer 31 is formed on the base substrate 1 by physical vapor deposition (PVD), and a layer of photoresist is coated on the surface of the first conductive layer 31 away from the base substrate 1, and the thickness of the photoresist is sufficient to ensure that the surface of the first conductive pattern material is completely covered. Then, the photoresist is exposed using a mask and developed, and the photoresist above the pattern of the first electrode 21 and the first conductive layer 31 is retained, and all other areas are removed. The structure outside the pattern of the first electrode 21 and the first conductive layer 31 is etched, and then the photoresist above the pattern of the first electrode 21 and the first conductive layer 31 is removed to form the pattern of the first electrode 21 and the first conductive layer 31. Compared with the previous semi-additive process, due to the isotropy of metal wet etching, the precision of the subtractive process is lower, the metal surface will be rougher, and the roughness will also be affected by the skin effect to a certain extent, increasing the resistance and thus increasing the loss. Therefore, the previous semi-additive process is often used.

[0170] Furthermore, a first adhesion layer 541 and a first seed layer 542 are sequentially formed on one side of the base substrate 1. The first adhesion layer 541 and the first seed layer 542 are formed on one side of the base substrate 1 by electroplating, chemical plating, or sputtering, and the patterns of the first adhesion layer 541 and the first seed layer 542 are formed by photolithography.

[0171] In step 1602 , a first dielectric 22 is formed on a side of the first electrode 21 away from the base substrate 1 , and a second electrode 23 is formed on a side of the first dielectric 22 away from the base substrate 1 .

[0172] For example, the first dielectric 22 is formed on the side of the first electrode 21 away from the substrate 1. The first dielectric 22 layer is deposited on the entire surface of the first electrode 21 away from the substrate 1 by physical vapor deposition (PVD), and a pattern of the first dielectric 22 is formed by processes such as photoresist coating, exposure, development, and etching.

[0173] Exemplarily, a second electrode 23 is formed on the first dielectric 22. The second electrode layer 23 is formed on the side of the first dielectric 22 away from the substrate 1 by physical vapor deposition (PVD), and a layer of photoresist is coated on the surface of the second electrode layer 23 away from the substrate 1. The thickness of the photoresist can ensure that the surface of the first conductive pattern material is completely covered. Afterwards, the photoresist is exposed using a mask and developed. The photoresist above the pattern of the second electrode 23 is retained, and all other areas are removed. The second electrode layer 23 outside the pattern of the second electrode 23 is etched to remove the photoresist above the pattern of the second electrode 23 to form the pattern of the second electrode 23.

[0174] In step 1603, a first insulating layer P1 pattern is formed on the side of the second electrode 23 and the first conductive layer 31 away from the base substrate 1; a second conductive layer 32 and a first trace 302 are formed on the side of the first insulating layer P1 away from the base substrate 1, a first connecting portion 51 connecting the second conductive layer 32 and the first conductive layer 31, and a third connecting portion 53 connecting the first trace 302 and the second electrode 23 is formed.

[0175] For example, an insulating layer P1 is formed on the side of the second electrode 23 and the first conductive layer 31 away from the substrate 1. After spin coating the entire insulating layer P0, a pattern of the insulating layer P0 is formed using processes such as photoresist coating, exposure, development, and etching. The second conductive layer 32, the first trace 302, the first connecting portion 51 connecting the second conductive layer 32 and the first conductive layer 31, and the third connecting portion 53 connecting the first trace 302 and the second electrode 23 can be produced using either an additive or subtractive process.

[0176] Furthermore, before preparing the second conductive layer 32, the first wiring 302, the first connecting portion 51 connecting the second conductive layer 32 and the first conductive layer 31, and the third connecting portion 53 connecting the first wiring 302 and the second electrode 23, a second adhesion layer 551 and a second seed layer 552 can be formed on the side of the first insulating layer P1 away from the base substrate 1 by electroplating, chemical plating or sputtering, and a photolithography process can be used to form a pattern of the second adhesion layer 551 and the second seed layer 552.

[0177] In step 1604, a second insulating layer P2 pattern is formed on one side of the second conductive layer 32 and the first trace 302; a third conductive layer 33 and a second trace 303 are formed on a side of the second insulating layer P2 away from the base substrate 1, a second electrolytic portion 52 connecting the third conductive layer 33 and the second conductive layer 32, and a fourth connecting portion 54 connecting the second trace 303 and the first trace 302 is formed.

[0178] Exemplarily, the second insulating layer P2 can be made by a semiconductor photolithography process, the same as the manufacturing method of the second insulating layer P1; the third conductive layer 33, the second trace 303, and the second electrolytic portion 52 connecting the third conductive layer 33 and the second conductive layer 32 and the fourth connecting portion 54 connecting the second trace 303 and the first trace 302 can be prepared by a semi-integrated method or an additive method.

[0179] Furthermore, before preparing the third conductive layer 33, the second wiring 303, the second electrolytic portion 52 connecting the third conductive layer 33 and the second conductive layer 32, and the fourth connecting portion 54 connecting the second wiring 303 and the first wiring 302, a third adhesion layer 561 and a third seed layer 562 are formed on the side of the first insulating layer P1 away from the base substrate 1, and patterns of the third adhesion layer 561 and the third seed layer 562 are formed by a photolithography process.

[0180] Step 1604: Form a third insulating layer P3 pattern on the side of the third conductive layer 33 and the second trace 303 away from the substrate 1; and form bumps 6 and solder balls 7 on the side of the third insulating layer P3 away from the substrate 1.

[0181] Exemplarily, the third insulating layer P3 can be made by a semiconductor photolithography process, similar to the manufacturing method of the second insulating layer P2; the fifth connecting portion 55 and the sixth connecting portion 56 and the bump 6 connecting the two can be prepared by a semi-finished method or an additive method.

[0182] The integrated passive device disclosed in this application can be used for filters, baluns, duplexers, etc., and is suitable for the fields of mobile communication RF front-end modules, Bluetooth and mobile hotspots.

[0183] The first electrode 21 and the second electrode 23 can be made of one or more metal materials (Au, Al, Ag, Cu, W, etc.) or other materials with good electrical conductivity, and the thickness is generally between 0.2 and 2 μm.

[0184] The first dielectric 22 may be made of insulating materials such as silicon nitride (SiNx), and its thickness may be designed and determined according to the requirements of the capacitance 2, and is usually set between 80 nm and 200 nm.

[0185] It should be noted that the base substrate 1 can be made of glass, ceramic, silicon or other polymer materials, and the thickness of the base substrate 1 can be about 200 μm, which is determined according to design requirements.

[0186] It should be noted that the thickness of the insulating layer 4 is in the range of 5 to 8 μm. The material of the insulating layer 4 can be a photosensitive insulating material, such as a polyimide (PI) material; a common photosensitive photoresist can be selected, and either a positive photoresist or a negative photoresist can be selected, and the thickness is determined according to the design requirements. If the thickness of the optical insulating layer 4 is too small, the conductive layers on the upper and lower sides of the insulating layer 4 will easily generate parasitic resistance during the operation of the device, affecting the operation performance of the device; if the thickness of the insulating layer 4 is too large, the film layer glass phenomenon is likely to occur during the preparation of multi-layer integrated passive devices, reducing the preparation yield of the device.

[0187] It should be noted that the thickness of the conductive layer ranges from 3 to 9 μm. If the conductive layer is too thin, parasitic resistance may be generated due to the small conductive cross-section area, affecting device performance. If the conductive layer is too thick, the conductive layer may easily peel off during the preparation process, affecting device reliability.

[0188] It should be noted that the conductive layer and the conductive material filled in the first connection portion 51 can be metals such as Au, Al, Ag, Cu, W or other conductive materials, which are not limited here, and are used to achieve electrical connection between different conductive layers.

[0189] It should be noted that in this application, the first adhesion layer 541, the second adhesion layer 551, and the third adhesion layer 561 can be made of Ti, Ti, Ta, TiN, or TaN, etc. The thickness of the adhesion layer 541 ranges from 100 to 200 nm, which is not limited here. If the adhesion layer thickness is too thin, the adhesion of the grown conductive layer to the underlying film layer will be weak, and the film layer may easily delaminate. The thickness of the adhesion layer should not be too thick, as the conductivity of the adhesion layer will be weak, which will affect the electrical connection between the conductive layers.

[0190] It should be noted that the first seed layer 542, the second seed layer 552, and the third seed layer 562 in the via structure, including the first one, can be made of materials such as Ti or Cu, and the seed layer thickness ranges from 5 to 300 nm, which is not limited here. They are used for the growth of the conductive material filled during the electroplating process.

[0191] It should be noted that the drawings of the present disclosure are schematic diagrams, and the positions of the passive components and passive integrated components can be set according to actual conditions.

[0192] In the structure of actual products, due to the thin thickness of the adhesion layer and the seed layer, it is difficult to accurately distinguish the boundary position between the two in microscopic characterizations, such as scanning electron microscopy images and transmission electron microscopy images.

[0193] The above descriptions are merely embodiments of the present disclosure and are not intended to limit the patent scope of the present disclosure. Any equivalent structures or equivalent process transformations made using the contents of the present disclosure and the drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present disclosure.

Claims

1. A passive device, characterized in that: The device comprises a substrate and an inductor located on one side of the substrate, wherein the inductor comprises: A first conductive layer is provided on one side of the base substrate; a second conductive layer, disposed on a side of the first conductive layer away from the base substrate, wherein the first conductive layer and the second conductive layer have different thicknesses; a first insulating layer, disposed between the first conductive layer and the second conductive layer; At least one first connecting portion passes through the first insulating layer and is electrically connected to the first conductive layer and the second conductive layer.

2. The passive device according to claim 1, characterized in that At least one first via hole is provided in the first insulating layer and corresponds to the at least one first connecting portion in a one-to-one manner, and at least a portion of the first connecting portion is provided in the first via hole; The aperture of the first via hole gradually increases in a direction away from the substrate.

3. The passive device according to claim 2, characterized in that The first conductive layer is provided with at least one first blind hole corresponding to the at least one first connecting portion on a side away from the base substrate, the orthographic projection of the first blind hole on the base substrate is within the orthographic projection of the first via hole on the base substrate, a portion of the first connecting portion is provided in the first via hole, and another portion of the first connecting portion is provided in the first blind hole.

4. The passive device according to claim 3, characterized in that Along a direction away from the substrate, a diameter variation rate of the first via hole is smaller than a diameter variation rate of the first blind hole.

5. The passive device according to claim 2, characterized in that: The first conductive layer and the second conductive layer are arranged in a strip structure, and the aperture of the first via hole is positively correlated with the thickness or strip width of the second conductive layer.

6. The passive device according to claim 3, characterized in that Also includes a second transition layer, The second transition layer is arranged on the sidewall of the first via hole, the bottom and sidewall of the first blind hole, and the side of the first insulating layer away from the substrate; The second conductive layer covers the second transition layer.

7. The passive device according to claim 6, characterized in that The first conductive layer and the second conductive layer are arranged in a strip structure, and the thickness of the second transition layer is positively correlated with the thickness of the second conductive layer or the strip width.

8. The passive device according to claim 6, characterized in that The second transition layer includes a second adhesion layer and a second seed layer, and the second seed layer is disposed on a side of the second adhesion layer away from the base substrate.

9. The passive device according to claim 1, characterized in that: The orthographic projection of the first conductive layer on the base substrate is a first annular pattern having a first opening, and the orthographic projection of the second conductive layer on the base substrate is a second annular pattern having a second opening.

10. The passive device according to claim 9, characterized in that: The proportion of the first opening in the first annular pattern and the proportion of the second opening in the second annular pattern are both greater than one half.

11. The passive device according to claim 9, characterized in that: The first opening and the second opening face different directions.

12. The passive device according to claim 9, characterized in that The first annular pattern and the second annular pattern are symmetrical patterns.

13. The passive device according to claim 12, characterized in that: The symmetrical pattern is a circle or a polygon.

14. The passive device according to claim 13, characterized in that: The interior angle of the polygon is greater than 90°.

15. The passive device according to claim 9, characterized in that The first annular pattern and the second annular pattern have the same shape but different sizes.

16. The passive device according to claim 15, characterized in that: The width of the second annular pattern is greater than that of the first annular pattern, and the width is the distance between an inner ring and an outer ring of the annular pattern.

17. The passive device according to claim 1, wherein: At least one of the first conductive layer and the second conductive layer in the same layer has a protruding portion in a direction parallel to the base substrate, and the protruding portion is connected to the first connecting portion.

18. The passive component according to any one of claims 1 to 17, characterized in that: Also includes: a third conductive layer, disposed on a side of the second conductive layer away from the base substrate; a second insulating layer, disposed between the second conductive layer and the third conductive layer; at least one second connecting portion, penetrating the second insulating layer and electrically connecting to the second conductive layer and the third conductive layer; A thickness of one of the first conductive layer, the second conductive layer, and the third conductive layer is different from thicknesses of the other two.

19. The passive device according to claim 18, characterized in that The orthographic projection of the second conductive layer on the base substrate is a second annular pattern with a second opening, and the orthographic projection of the third conductive layer on the base substrate is a third annular pattern with a third opening. The width of the third annular pattern is greater than that of the second annular pattern.

20. The passive component according to claim 18, wherein: The thickness of the second conductive layer is greater than that of the first conductive layer and the third conductive layer; or The thickness of the first conductive layer is greater than that of the second conductive layer, and the thickness of the second conductive layer is greater than that of the third conductive layer.

21. The passive device according to claim 18, characterized in that The second insulating layer is provided with at least one second via hole corresponding to the second connecting portion, and at least a portion of the second connecting portion is provided in the second via hole; The orthographic projections of the first connecting portion and the second connecting portion on the substrate do not overlap.

22. An integrated passive device, characterized in that: include: At least one passive component according to any one of claims 1 to 21; as well as A capacitor is electrically connected to the first conductive layer of the inductor.

23. The integrated passive device according to claim 22, characterized in that The capacitor includes a first electrode disposed on one side of the substrate, a second electrode disposed on a side of the first electrode away from the substrate, and a first dielectric layer disposed between the first electrode and the second electrode; The orthographic projections of the first electrode, the first dielectric layer, and the second electrode on the substrate at least partially overlap; The inductor and the capacitor are arranged on the same side of the base substrate, and the first conductive layer of the inductor and the first electrode of the capacitor are arranged on the same layer and are electrically connected.

24. The integrated passive device according to claim 23, characterized in that The thickness of the first electrode is the same as that of the first conductive layer, and the thickness of the first electrode is greater than that of the second electrode.

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