Self-adaptive low-cost MBUS host circuit

Abstract

The utility model discloses a self-adaptive low-cost MBUS host circuit which comprises a BOOST circuit, and the BOOST circuit comprises a POWER pin, a core boost chip, an L inductor, an L inductor, a VDDH high voltage and a VDDL low voltage which are arranged. The utility model discloses a circuit for writing data from an MBUS host to an MBUS slave. The circuit for writing data from the MBUS host to the MBUS slave comprises a D diode, a D diode, an NPN triode QI, an NPN triode QII, a TX pin, a resistor R and an NPN triode QIII. According to the utility model, the BOOST circuit and the circuit for writing the data from the MBUS host to the MBUS slave are arranged, the automatic switching function of the circuit is realized through the structure of a single hardware circuit, the circuit is simple and stable, the manufacturing cost is low, the response speed of the whole circuit is high, the structure is simple, and the maintenance after damage is convenient.

Description

Technical Field

[0001] The utility model relates to the technical field of MBUS host circuits, in particular to a self-adaptive low-cost MBUS host circuit. Background Art

[0002] MBUS is a data bus designed specifically for transmitting information for consumption measuring instruments and counters. It is mainly used in data collection in the field of energy consumption, where the host can read and write relevant data content in the slave, while the slave can only perform corresponding operations under the instructions of the host. Therefore, the anti-interference requirements on the MBUS host bus are very high. It must be able to resist various capacitive and inductive coupling interferences, and all slaves and hosts must be isolated from each other as much as possible. Since terminal slaves often require low networking costs and most transmission lines use unshielded cables, abnormal situations such as unstable and incorrect information acquisition often occur in actual applications. Therefore, under normal circumstances, high-specification MBUS master control chips are used for circuit design. As a result, the manufacturing cost of the circuit design is high, it is not suitable for compatibility expansion, and it cannot be repaired after damage. Utility Model Content

[0003] Therefore, the purpose of the present invention is to provide a self-adaptive low-cost MBUS host circuit, which realizes the automatic switching function of the circuit through the set BOOST boost circuit and the MBUS host writing data circuit to the MBUS slave with a single hardware circuit structure. The circuit is simple, stable and has low manufacturing cost. The response speed of the entire circuit is fast, and the structure is simple, which is convenient for repair after damage.

[0004] To solve the above technical problems, according to one aspect of the present invention, the present invention provides the following technical solution: a self-adaptive low-cost MBUS host circuit, comprising:

[0005] A BOOST boost circuit, comprising a POWER pin, a core boost chip, an L inductor, an L inductor, a VDD_H high voltage, and a VDD_L low voltage;

[0006] The MBUS host writes data to the MBUS slave circuit, wherein the MBUS host writes data to the MBUS slave circuit including a D diode, a D diode, an NPN transistor QI, an NPN transistor QⅡ, a TX pin, a resistor R, and an NPN transistor QⅢ;

[0007] The BOOST boost circuit provides power input to the BOOST boost circuit via the POWER pin;

[0008] The BOOST boost circuit L inductor and L inductor obtain two sets of output voltages, which are divided into VDD_H high voltage and VDD_L low voltage, to provide a level signal of the high voltage difference between the MBUS host and the MBUS slave;

[0009] The VDD_H high voltage and the VDD_L low voltage are isolated by the D diode and the D diode;

[0010] The TX pin controller data output pin;

[0011] The MBUS host outputs current through the MBUS slave pin, and the current passes through the resistor R1 and is grounded.

[0012] Compared with the prior art, the advantages of the present invention are:

[0013] By setting up a BOOST boost circuit and a circuit for the MBUS host to write data to the MBUS slave, the automatic switching function of the circuit is realized with a single hardware circuit structure. The circuit is simple, stable, and has a low manufacturing cost. The entire circuit has a fast response speed and a simple structure, which is convenient for repair after damage. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the present invention will be described in detail below in conjunction with the accompanying drawings and detailed embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without inventive labor. Among them:

[0015] Figure 1 This is the circuit diagram of the BOOST boost circuit of the utility model;

[0016] Figure 2 This is a circuit diagram of the MBUS host writing data to the MBUS slave in the utility model;

[0017] Figure 3 This is the circuit location diagram of the resistor R1 of the present invention;

[0018] Figure 4 This is the circuit location diagram of the NPN transistor Q3 of the utility model;

[0019] Figure 5 This is the overall circuit diagram of the utility model.

[0020] In the figure: 11, POWER pin; 12, core boost chip; 13, L1 inductor; 14, L2 inductor; 15, VDD_H high voltage; 16, VDD_L low voltage; 21, D1 diode; 22, D2 diode; 23, NPN transistor QI; 24, NPN transistor QⅡ; 25, TX pin; 26, resistor R1; 27, NPN transistor QⅢ. DETAILED DESCRIPTION

[0021] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0022] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. People skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific implementation methods disclosed below.

[0023] Next, the present invention is described in detail with reference to schematic diagrams. For ease of illustration, cross-sectional views of device structures may be partially enlarged and not to scale when describing the embodiments of the present invention. Furthermore, the schematic diagrams are merely illustrative and should not limit the scope of protection of the present invention. Furthermore, in actual production, three-dimensional dimensions, including length, width, and depth, should be included.

[0024] In order to make the purpose, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0025] The utility model provides a self-adaptive low-cost MBUS host circuit, which realizes the automatic switching function of the circuit through the provided BOOST boost circuit and the MBUS host writing data circuit to the MBUS slave with a single hardware circuit structure. The circuit is simple, stable and has a low manufacturing cost. The response speed of the entire circuit is fast, and the structure is simple, which is convenient for repair after damage.

[0026] Figure 1-Figure 5 The figure shows the overall structure of a low-cost self-adaptive MBUS host circuit according to the present invention. Figure 1-5 The main structure of this embodiment includes: a BOOST boost circuit and a circuit for the MBUS host to write data to the MBUS slave.

[0027] The BOOST boost circuit is used to cooperate with the MBUS host to write data to the MBUS slave circuit. Specifically, the BOOST boost circuit includes a POWER pin 11, a core boost chip 12, an L1 inductor 13, an L2 inductor 14, a VDD_H high voltage 15, and a VDD_L low voltage 16. The MBUS host writes data to the MBUS slave circuit, and the MBUS host writes data to the MBUS slave circuit includes a D1 diode 21, a D2 diode 22, an NPN transistor QI 23, an NPN transistor QII 24, a TX pin 25, a resistor R1 26, and an NPN transistor QIII 27.

[0028] In actual use, the power input is provided to the BOOST boost circuit through the POWER pin 11, and then two sets of output voltages are obtained through the L1 inductor 13 and the L2 inductor 14, which are divided into VDD_H high voltage and VDD_L low voltage, to provide a level signal of the high voltage difference between the MBUS host and the MBUS slave. Among them, U2 serves as the core boost chip 12, and two sets of independent BOOST boost circuits can also be used to obtain VDD_H and VDD_L;

[0029] The VDD_H and VDD_L voltages provided by the BOOST circuit are isolated by diodes D1 21 and D2 22. When the collector C of NPN transistor QI 23 and its emitter E conduct, the VDD_H voltage is higher than the VDD_L voltage, so the MBUS_P pin reaches the VDD_H pin. TX pin 25 is the controller's data output pin. When TX is high, NPN transistor QII 24 conducts, and the voltage level at pin 1 of QII reaches 0, connecting it to GND. R3 and R2 form a series connection between VDD_H and GND, and the base B of QI reaches 1 / 2 of VDD_H. Therefore, the collector C of QI and its emitter E conduct, and the MBUS_P output voltage, VDD_H, is high. When TX is low, NPN transistor QⅡ24 is cut off. At this time, the level of pin 1 of QⅡ is equal to VDD_H. At this time, R3, R2 and the collector C of QⅡ are in an equipotential state, so the collector C of QI and the emitter E of QI are cut off, and the MBUS_P output level VDD_L is low.

[0030] The MBUS slave transmits data back to the MBUS master using the MBUS slave's output current. Therefore, when the MBUS slave outputs current through the MBUS_N pin, the current passes through sampling resistor R126 and then to ground. At this point, the MBUS_N bus voltage is equal to Iout*R1. However, due to the relatively small voltage amplitude, this voltage is susceptible to noise on the line, making data processing difficult. Therefore, the present invention uses an amplifier circuit, built with U1, to amplify the MBUS_N line signal by a factor equal to 1+R6 / R5. This amplified output signal significantly enhances stability and noise immunity. NPN transistor QIII27 utilizes a common-emitter amplifier circuit. When the base B level at pin 2 of QIII exceeds 0.7 / 0.8V, QIII turns on, and the RX level is low. When the base B level at pin 2 of QIII falls below 0.7 / 0.8V, QIII turns off, and the RX level is high. Therefore, through these steps, the data information fed back from the MBUS slave to the MBUS master using the current is captured.

[0031] While the present invention has been described above with reference to specific embodiments, various modifications may be made and equivalent components may be substituted without departing from the scope of the present invention. In particular, as long as no structural conflicts exist, the various features of the embodiments disclosed herein may be combined with one another in any manner, and the omission of an exhaustive description of these combinations in this specification is solely for the sake of space and resource conservation. Therefore, the present invention is not limited to the specific embodiments disclosed herein, but encompasses all technical solutions within the scope of the claims.

Claims

1. A self-adaptive low-cost MBUS host circuit, characterized in that: include: A BOOST boost circuit, the BOOST boost circuit comprising a POWER pin (11), a core boost chip (12), an L1 inductor (13), an L2 inductor (14), a VDD_H high voltage (15) and a VDD_L low voltage (16); The MBUS host writes data to the MBUS slave circuit, wherein the MBUS host writes data to the MBUS slave circuit including a D1 diode (21), a D2 diode (22), an NPN transistor QI (23), an NPN transistor QII (24), a TX pin (25), a resistor R1 (26), and an NPN transistor QIII (27); The MBUS host outputs current through the MBUS slave pin, and the current is grounded through the resistor R1 (26); The TX pin (25) is a controller data output pin; The VDD_H high voltage is isolated from the VDD_L low voltage by the D1 diode (21) and the D2 diode (22); The BOOST boost circuit L1 inductor (13) and L2 inductor (14) obtain two sets of output voltages, which are divided into VDD_H high voltage and VDD_L low voltage, for providing a level signal of a high voltage difference between the MBUS host and the MBUS slave; The BOOST boost circuit provides power input to the BOOST boost circuit via a POWER pin (11).

Images