Precision-adjustable DC offset cancellation circuit
By introducing an adjustable reference current source array and a logic selection switch into the DCOC circuit, the problem of unadjustable circuit correction accuracy and range in the prior art is solved, and the circuit accuracy is adjustable and standardized.
Patent Information
- Application Number
- CN202422402855.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-30
- Publication Date
- 2025-09-09
- Estimated Expiration
- 2034-09-30
AI Technical Summary
The correction accuracy and range of the existing DCOC circuit structure are not adjustable, resulting in the need to customize different circuits for each level of the intermediate frequency link, making standardization difficult.
A precision-adjustable DC offset cancellation circuit comprising a first adjustable reference current source array unit, a second adjustable reference current source array unit, a first current mirror unit module and a second current mirror unit module is adopted, and the adjustment of precision and range is achieved through a control switch and a logic selection switch.
The accuracy and range of the DCOC circuit can be flexibly adjusted, the standardization and accuracy of the circuit are improved, and the circuit operating point is ensured to be within an appropriate range.
Smart Images
Figure CN223320793U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of circuit technology, and in particular to a precision-adjustable DC offset elimination circuit. Background Art
[0002] In a zero-IF transceiver architecture, the IF circuit has a large DC offset. This offset voltage, after high-gain amplification in the IF circuit, can cause subsequent circuits to deviate from their normal DC operating point, severely impacting circuit functionality and performance. Therefore, a DC offset cancellation (DCOC) circuit with adjustable accuracy is generally required to suppress this offset.
[0003] In related technologies, the correction accuracy and range of the DCOC circuit structure are not adjustable. The intermediate frequency link generally has multiple stages, and DCOC correction is required at almost every stage. Usually, the correction range and accuracy required for different stages are different. The current circuit structure has a fixed LSB and cannot be adjusted. Different DCOCs need to be customized for each stage, which is not conducive to standardization and needs improvement. Summary of the Invention
[0004] In order to facilitate the adjustment of the correction accuracy and range of the DCOC circuit structure, the present application provides a DC offset cancellation circuit with adjustable accuracy.
[0005] The present application provides a precision-adjustable DC offset cancellation circuit, which adopts the following technical solution:
[0006] A precision-adjustable DC offset cancellation circuit includes a first adjustable reference current source array unit, a second adjustable reference current source array unit, a first current mirror unit module, and a second current mirror unit module; an output end of the first adjustable reference current source array unit is connected to one end of the first current mirror unit module, and an output end of the second adjustable reference current source array unit is connected to one end of the second current mirror unit module;
[0007] The first adjustable reference current source array unit includes N corresponding first MOS transistors and N control switches SP, wherein the first electrodes of two adjacent first MOS transistors are connected to the first electrode and the second electrodes are connected to the second electrode, the third electrodes of the first MOS transistors are connected to the control switch SP, and the other end of the control switch SP is electrically connected to the power supply;
[0008] The second adjustable reference current source array unit includes N corresponding second MOS transistors and N control switches SN. The first electrodes of two adjacent second MOS transistors are connected to the first electrode, and the second electrodes are connected to the second electrode. The third electrodes of the MOS transistors are connected to the control switch SN, and the other end of the control switch SP is grounded.
[0009] Optionally, it further includes a first minimum current source module, a second minimum current source module, an output current on-off switch module and a logic gate switch unit;
[0010] The first minimum current source module is connected in parallel with the first current mirror unit module to lead to a first output end, and the second minimum current source module is connected in parallel with the second current mirror unit module to lead to a second output end; the first end of the logic gate switch unit is electrically connected to the first output end, and the second end of the logic gate switch unit is electrically connected to the second output end;
[0011] The output current on-off switch module is used to control the on-off between the first end of the logic gate switch unit and the first output end, and the on-off between the second end of the logic gate switch unit and the second output end.
[0012] Optionally, the first minimum current source module includes a first current source and a first switch S1, one end of the first current source is electrically connected to a power supply, and the other end of the first current source is electrically connected to one end of the first switch S1;
[0013] The other end of the first switch S1 is electrically connected to the first branch switch of the first current mirror unit module, and the first output end is located between the other end of the first switch S1 and the first branch switch of the first current mirror unit module.
[0014] Optionally, the second minimum current source module includes a second current source and a second switch S2, one end of the first current source is grounded, and the other end of the second current source is electrically connected to one end of the second switch S2;
[0015] The other end of the second switch S2 is electrically connected to the second branch switch of the second current mirror unit module, and the second output end is located between the other end of the second switch S2 and the second branch switch of the first current mirror unit module.
[0016] Optionally, a first low-pass filter circuit is connected between one end of the first adjustable reference current source array unit and the first current mirror unit module.
[0017] Optionally, a second low-pass filter circuit is connected between one end of the second adjustable reference current source array unit and the second current mirror unit module.
[0018] Optionally, the output current on-off switch module includes a current on-off switch S3 and a current on-off switch S4, one end of the current on-off switch S3 is connected to the first output end, and the other end of the current on-off switch S3 is connected to one end of the logic selection switch unit; one end of the current on-off switch S4 is connected to the second output end, and the other end of the current on-off switch S4 is connected to the other end of the logic selection switch unit.
[0019] Optionally, the logic gating switch unit includes a gating switch S5, a gating switch S6, a gating switch S7 and a gating switch S8 connected end to end, one end of the current on-off switch S3 is connected between the gating switch S5 and the gating switch S6, and one end of the current on-off switch S4 is connected between the gating switch S7 and the gating switch S8.
[0020] Optionally, a switch S9 is provided in parallel at both ends of the filter resistor of the first low-pass filter circuit, and a switch S10 is provided in parallel at both ends of the filter resistor of the second low-pass filter circuit.
[0021] In summary, the present application includes at least one of the following beneficial technical effects: by adjusting the number of the first adjustable reference current source array unit and the second adjustable reference current source array unit connected to the circuit, the precision adjustment of DCOC can be achieved, the value of n needs to ensure that the circuit operating point is within an appropriate range, and the LSB size of the reference current can be adjusted in the range of I / n, I / (n-1),…, I. On this basis, selecting a smaller LSB can make DCOC achieve higher precision. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] Figure 1 The embodiment of the present application mainly embodies a circuit diagram of a DC offset cancellation circuit with adjustable precision.
[0023] Figure 2 This is a logic block diagram of a logic selection switch unit mainly embodied in an embodiment of the present application. DETAILED DESCRIPTION
[0024] The following describes the embodiments of the present application in detail, and examples of the embodiments are shown in the attached Figure 1-2 Shown in.
[0025] Throughout this specification, reference to the terms "certain embodiments," "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
[0026] The present application discloses a precision adjustable DC offset elimination circuit, referring to Figure 1 , comprising a first adjustable reference current source array unit, a second adjustable reference current source array unit, a first current mirror unit module P_source, and a second current mirror unit module N_sink; an output end of the first adjustable reference current source array unit is connected to one end of the first current mirror unit module P_source, and an output end of the second adjustable reference current source array unit is connected to one end of the second current mirror unit module N_sink;
[0027] The first adjustable reference current source array unit includes N correspondingly arranged first MOS transistors and N control switches SP, wherein the first electrodes of two adjacent first MOS transistors are connected to the first electrode, and the second electrodes are connected to the second electrode, the third electrodes of the first MOS transistors are connected to the control switch SP, and the other end of the control switch SP is electrically connected to the power supply;
[0028] The second adjustable reference current source array unit includes N corresponding second MOS transistors and N control switches SN. The first electrodes of two adjacent second MOS transistors are connected to the first electrode, and the second electrodes are connected to the second electrode. The third electrodes of the MOS transistors are connected to the control switch SN, and the other end of the control switch SP is grounded.
[0029] Two N-channel adjustable reference current source array units, P_bias and N_bias, each function as an identical current mirror controlled by switches SP1-SPn and SN1-SNn, respectively. An external bias current is given by kI, where k is the ratio of the adjustable reference current source array unit to the minimum current source of the DCOC. The reference current is determined by the on / off state of switches SP1-SPn and SN1-SNn. If only one switch is closed (SN1 and SP1 are closed) and the others are open, the reference current is kI, and the minimum current source's LSB current is kI / k=I. If all switches SP1-SPn and SN1-SNn are closed, the reference current is kI / n, and the minimum current source's LSB current is I / n. The DCOC's precision can be adjusted by adjusting the number of reference current source arrays connected to the circuit. The value of n must ensure that the circuit operating point is within an appropriate range. The LSB of the reference current can be adjusted from I / n, I / (n-1), ..., to I. Selecting a smaller LSB can achieve higher DCOC precision.
[0030] A precision-adjustable DC offset cancellation circuit also includes a first minimum current source module P_fix, a second minimum current source module N_fix, an output current on-off switch module, and a logic selection switch unit. The first minimum current source module P_fix is connected in parallel with the first current mirror unit module P_source to lead to a first output terminal, and the second minimum current source module N_fix is connected in parallel with the second current mirror unit module N_sink to lead to a second output terminal. The current magnitudes of N_fix and P_fix are both the minimum current I, and the on-off of the switch is determined by the highest bit code. <7> The inverse signal code_b <7> Control, its function is to ensure the monotonicity of output current with code change. <7> =0, and the absolute value of the output current of Psource and Nsink is increased by I when code < 128, to prevent the output current from being 0 when code = 127 and code 128.
[0031] The first end of the logic gate switch unit is electrically connected to the first output end, and the second end of the logic gate switch unit is electrically connected to the second output end. The output current on-off switch module is used to control the on-off between the first end of the logic gate switch unit and the first output end, and the on-off between the second end of the logic gate switch unit and the second output end, thereby achieving current direction and magnitude control.
[0032] The first minimum current source module P_fix includes a first current source and a first switch S1. One end of the first current source is electrically connected to a power supply, and the other end of the first current source is electrically connected to one end of the first switch S1. The other end of the first switch S1 is electrically connected to a first branch switch of the first current mirror unit module P_source. The first output end is located between the other end of the first switch S1 and the first branch switch of the first current mirror unit module P_source.
[0033] The second minimum current source module N_fix includes a second current source and a second switch S2. One end of the first current source is grounded, and the other end of the second current source is electrically connected to one end of the second switch S2. The other end of the second switch S2 is electrically connected to the second branch switch of the second current mirror unit module. The second output end is located between the other end of the second switch S2 and the second branch switch of the first current mirror unit module.
[0034] A first low-pass filter circuit is connected between one end of the first adjustable reference current source array unit and the first current mirror unit module, and a second low-pass filter circuit is connected between one end of the second adjustable reference current source array unit and the second current mirror unit module.
[0035] Specifically, the first low-pass filter circuit includes a filter resistor Rp and a filter capacitor Cp, and the second low-pass filter circuit includes a filter resistor Rn and a filter capacitor Cn. Their function is to filter out high-frequency noise. A switch S9 is provided in parallel across the filter resistor of the first low-pass filter circuit, and a switch S10 is provided in parallel across the filter resistor of the second low-pass filter circuit. Switches S9 and S10 are fast-control switches. When closed in calibration mode, they short-circuit the resistors to quickly establish the voltage across resistors Rn and Rp, thereby improving the circuit's response speed. S9 and S10 are complementary switches that can offset channel charge injection.
[0036] The output current on-off switch module includes a current on-off switch S3 and a current on-off switch S4. One end of the current on-off switch S3 is connected to the first output terminal, and the other end of the current on-off switch S3 is connected to one end of the logic gate switch unit. One end of the current on-off switch S4 is connected to the second output terminal, and the other end of the current on-off switch S4 is connected to the other end of the logic gate switch unit. The logic gate switch unit includes gate switches S5, S6, S7, and S8 connected end to end. One end of the current on-off switch S3 is connected between gate switches S5 and S6, and one end of the current on-off switch S4 is connected between gate switches S7 and S8.
[0037] The direction of the current at the P and N terminals is changed to be controlled by the switch. <7> and its inverse signal code_b <7> By controlling the on and off of switches S5 to S8, the current direction of output ports P and N is controlled. <7> =0, S5 and S8 are turned on, S6 and S7 are turned off, the P terminal injects current, and the N terminal extracts current; code <7> =1, the direction of the output port current extraction and injection is opposite, as shown by the red arrow in the figure. For a certain output port, the extraction and injection of current are not performed at the same time.
[0038] The logic block diagram of the logic gate switch unit is shown in the attached Figure 2 As shown, when the highest code <7> = 0, p_code<6:0> = n_code<6:0> = code_b<6:0>; when code <7> =1,
[0039] p_code<6:0> = n_code<6:0> = code<6:0>. n_code<6:0> always equals p_code<6:0>, ensuring symmetry between the P and N output currents. For a node, the source current is negative, while the sink current is positive. Therefore, the Psource current is positive for the output node, and the Nsink current is negative for the output node.
[0040] When code=127=0111 1111, n_code<6:0>=p_code<6:0>=code_b<6:0>=0000000, the output current of Psource and Nsink are both 0; when code=128=1000 0000,
[0041] n_code<6:0>=p_code<6:0>=code_b<6:0>=000 0000, so the output current is not monotonic when code=127 and code=128. After adding the fix branch, the absolute value of the output current of Psource and Nsink Iout(code=127)=I, Iout(code=128)=0, ensuring monotonicity.
[0042] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.
Claims
1. A precision-adjustable DC offset cancellation circuit, characterized in that: The invention comprises a first adjustable reference current source array unit, a second adjustable reference current source array unit, a first current mirror unit module, and a second current mirror unit module; an output end of the first adjustable reference current source array unit is connected to one end of the first current mirror unit module, and an output end of the second adjustable reference current source array unit is connected to one end of the second current mirror unit module; The first adjustable reference current source array unit includes N corresponding first MOS transistors and N control switches SP, wherein the first electrodes of two adjacent first MOS transistors are connected to the first electrode and the second electrodes are connected to the second electrode, the third electrodes of the first MOS transistors are connected to the control switch SP, and the other end of the control switch SP is electrically connected to the power supply; The second adjustable reference current source array unit includes N corresponding second MOS transistors and N control switches SN. The first electrodes of two adjacent second MOS transistors are connected to the first electrode, and the second electrodes are connected to the second electrode. The third electrodes of the MOS transistors are connected to the control switch SN, and the other end of the control switch SP is grounded.
2. The precision-adjustable DC offset cancellation circuit according to claim 1, wherein: It also includes a first minimum current source module, a second minimum current source module, an output current on-off switch module and a logic gate switch unit; The first minimum current source module is connected in parallel with the first current mirror unit module to lead to a first output end, and the second minimum current source module is connected in parallel with the second current mirror unit module to lead to a second output end; the first end of the logic gate switch unit is electrically connected to the first output end, and the second end of the logic gate switch unit is electrically connected to the second output end; The output current on-off switch module is used to control the on-off between the first end of the logic gate switch unit and the first output end, and the on-off between the second end of the logic gate switch unit and the second output end.
3. The precision-adjustable DC offset cancellation circuit according to claim 2, characterized in that: The first minimum current source module includes a first current source and a first switch S1, one end of the first current source is electrically connected to the power supply, and the other end of the first current source is electrically connected to one end of the first switch S1; The other end of the first switch S1 is electrically connected to the first branch switch of the first current mirror unit module, and the first output end is located between the other end of the first switch S1 and the first branch switch of the first current mirror unit module.
4. The precision-adjustable DC offset cancellation circuit according to claim 3, characterized in that: The second minimum current source module includes a second current source and a second switch S2, one end of the first current source is grounded, and the other end of the second current source is electrically connected to one end of the second switch S2; The other end of the second switch S2 is electrically connected to the second branch switch of the second current mirror unit module, and the second output end is located between the other end of the second switch S2 and the second branch switch of the first current mirror unit module.
5. The precision-adjustable DC offset cancellation circuit according to claim 1, characterized in that: A first low-pass filter circuit is connected between one end of the first adjustable reference current source array unit and the first current mirror unit module.
6. The precision-adjustable DC offset cancellation circuit according to claim 5, characterized in that: A second low-pass filter circuit is connected between one end of the second adjustable reference current source array unit and the second current mirror unit module.
7. The precision-adjustable DC offset cancellation circuit according to claim 2, characterized in that: The output current on-off switch module includes a current on-off switch S3 and a current on-off switch S4, one end of the current on-off switch S3 is connected to the first output end, and the other end of the current on-off switch S3 is connected to one end of the logic selection switch unit; one end of the current on-off switch S4 is connected to the second output end, and the other end of the current on-off switch S4 is connected to the other end of the logic selection switch unit.
8. The precision-adjustable DC offset cancellation circuit according to claim 7, characterized in that: The logic selection switch unit includes a selection switch S5, a selection switch S6, a selection switch S7 and a selection switch S8 connected end to end, one end of the current on-off switch S3 is connected between the selection switch S5 and the selection switch S6, and one end of the current on-off switch S4 is connected between the selection switch S7 and the selection switch S8.
9. The precision-adjustable DC offset cancellation circuit according to claim 6, characterized in that: A switch S9 is provided in parallel at both ends of the filter resistor of the first low-pass filter circuit, and a switch S10 is provided in parallel at both ends of the filter resistor of the second low-pass filter circuit.