Lead frame and packaging structure

Abstract

The utility model provides a lead frame and a packaging structure, the lead frame comprises two base islands, the two base islands comprise a first base island and a second base island, a first distance exists between the first base island and the second base island, and a second distance exists between the first base island and the second base island; each base island comprises a first surface for bearing a chip and a second surface opposite to the first surface; a plurality of signal pins, wherein the plurality of signal pins are arranged at intervals; and the distance between the first pin and the plurality of signal pins and the distance between the second pin and the plurality of signal pins are greater than or equal to a second distance. According to the utility model, the two base islands can avoid mutual interference between two chips, and meanwhile, the first pins and the second pins can be arranged as high-voltage output pins, so that a packaging line diagram can be designed more flexibly on the basis of ensuring the product safety.

Description

Technical Field

[0001] The utility model relates to the field of chip packaging, in particular to a lead frame and a packaging structure. Background Art

[0002] Conventional packaging methods for IC control chips and high-power chips typically use packages such as DFN (Dual Flat No Leads) and QFN (Quad Flat No Leads). However, these packages often have the following problems:

[0003] 1. The safety distance between the high-voltage pin and the low-voltage pin is not met;

[0004] 2. Placing two chips on a single island causes mutual interference between the two chips.

[0005] Therefore, providing a lead frame that reduces mutual interference between two chips and meets the safety distance between high-voltage pins and low-voltage pins has become a technology that the industry urgently needs to solve. Utility Model Content

[0006] The technical problem solved by the utility model is to provide a lead frame, which solves the problems of mutual interference between sealed chips and the safe distance between high-voltage pins and low-voltage pins.

[0007] In order to solve the above technical problems, according to a first aspect of the present invention, a lead frame is provided, comprising:

[0008] Two base islands, the two base islands include a first base island and a second base island, a first distance exists between the first base island and the second base island, and each base island includes a first surface for carrying a chip and a second surface opposite to the first surface;

[0009] A plurality of signal pins, wherein the plurality of signal pins are arranged at intervals;

[0010] The first pin, the second pin, the distance between the first pin and the plurality of signal pins, and the distance between the second pin and the plurality of signal pins are both greater than or equal to the second distance.

[0011] Optionally, the lead frame further includes a plurality of third pins, wherein the third pins are directly connected to the second base island, and the width of the third pins is greater than the width of the signal pins.

[0012] Optionally, the distance between the third pin and the plurality of signal pins, the first pin, and the second pin is greater than or equal to the second distance.

[0013] Optionally, the second distance is 1.7 mm.

[0014] Optionally, the plurality of signal pins include a first-width signal pin and at least one second-width signal pin, and the width of the second-width signal pin is greater than the width of the first-width signal pin.

[0015] Optionally, the width of the second-width signal pin is between 0.22 mm and 0.87 mm.

[0016] Optionally, the width of the first pin is greater than the width of the second pin.

[0017] According to a second aspect of the present invention, a packaging structure is provided, comprising the lead frame, a first control chip, a first power chip, and a packaging body; the packaging body is used to package the lead frame, the first control chip, and the first power chip;

[0018] The first control chip is mounted on the first surface of the first base island, and the first power chip is mounted on the first surface of the second base island;

[0019] The signal pins specifically include:

[0020] a first signal pin, the first signal pin being directly connected to the first base island and being used to support the first base island;

[0021] a second signal pin, the second signal pin being electrically connected to the first control chip and used for voltage and current detection;

[0022] a third signal pin, the third signal pin being electrically connected to the first control chip and used for optocoupler current feedback detection;

[0023] a fourth signal pin, the fourth signal pin being electrically connected to the first control chip and used for source circuit detection;

[0024] a fifth signal pin, the fifth signal pin being electrically connected to the first power chip and used for power input;

[0025] a sixth signal pin, the sixth signal pin being electrically connected to the first power chip and used for current output;

[0026] The first pin is electrically connected to the first power chip, the second pin is electrically connected to the first control chip, and both the first pin and the second pin are used for high-voltage current input.

[0027] According to a third aspect of the present invention, a packaging structure is provided, comprising the lead frame, a second control chip, a second power chip, and a packaging body; the packaging body is used to package the lead frame, the second control chip, and the second power chip;

[0028] The second control chip is mounted on the first surface of the first base island, and the second power chip is mounted on the first surface of the second base island;

[0029] The signal pins specifically include:

[0030] a first signal pin, the first signal pin being directly connected to the first base island and being used to support the first base island, and the first signal pin being grounded;

[0031] a second signal pin, the second signal pin being electrically connected to the second control chip and used for source current detection;

[0032] a third signal pin, the third signal pin being electrically connected to the second control chip and used for voltage and current detection;

[0033] a fourth signal pin, the fourth signal pin being electrically connected to the second control chip and used for optocoupler current feedback detection;

[0034] a fifth signal pin and a sixth signal pin, wherein the fifth signal pin and the sixth signal pin are both electrically connected to the second power chip and used for current output;

[0035] The first pin is electrically connected to the second power chip and is used for high-voltage current input; the second pin is electrically connected to the second control chip and is used for power input.

[0036] According to a fourth aspect of the present invention, a packaging structure is provided, comprising the lead frame, a third control chip, a third power chip, and a packaging body; the packaging body is used to package the lead frame, the third control chip, and the third power chip;

[0037] The third control chip is mounted on the first surface of the first base island, and the third power chip is mounted on the first surface of the second base island;

[0038] The signal pins specifically include:

[0039] a first signal pin, the first signal pin being directly connected to the first base island and being used to support the first base island, and the first signal pin being grounded;

[0040] a second signal pin, the second signal pin being electrically connected to the third control chip and used for source current detection;

[0041] a third signal pin, the third signal pin being electrically connected to the third control chip and used for voltage and current detection;

[0042] a fourth signal pin, the fourth signal pin being electrically connected to the third control chip and used for optocoupler current feedback detection;

[0043] a fifth signal pin and a sixth signal pin, wherein the fifth signal pin and the sixth signal pin are both electrically connected to the third power chip and are used for current output;

[0044] Wherein, the first pin is grounded and electrically connected to the first base island; the second pin is electrically connected to the third control chip and is used for power supply voltage input;

[0045] The lead frame further includes three third pins, all of which are used for high-voltage current input.

[0046] Compared with the prior art, the present invention has the following beneficial effects:

[0047] The present invention provides a lead frame, which is provided with two base islands, a plurality of signal pins, a first pin and a second pin. The two base islands can be used to place two different chips to prevent mutual interference between the chips.

[0048] In addition, since the distance between the first pin and the several signal pins and the distance between the second pin and the several signal pins are both greater than or equal to the second distance, the first pin and the second pin can both be set as high-voltage pins, thereby ensuring product safety and enabling the package line diagram to be designed more flexibly.

[0049] Furthermore, the lead frame also includes several third pins directly connected to the second base island, which enables the chip placed on the second base island to dissipate heat better; and the width of the third pin is greater than the width of the signal pin, so that the third pin can pass large current.

[0050] Furthermore, if the distance between the third pin and the several signal pins, the first pin, and the second pin is greater than or equal to the second distance, the third pin can also be used for high-voltage output, and when the third pin is used for high-voltage output, the third pin can take into account the dual functions of heat dissipation and high-voltage output.

[0051] Furthermore, the several signal pins include a first width signal pin and at least one second width signal pin, and the width of the second width signal pin is greater than the width of the first pin, so that the second width signal pin can weld more pairs of wires compared to the first width signal pin, which not only increases the overcurrent capacity of the second width signal pin, but also reduces the impedance of the second width signal pin. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 This is a schematic diagram of the structure of an embodiment of the lead frame provided by the utility model Figure 1 ;

[0053] Figure 2 This is a schematic diagram of the structure of an embodiment of the lead frame provided by the utility model Figure 2 ;

[0054] Figure 3 This is a structural schematic diagram of another embodiment of the lead frame provided by the present invention;

[0055] Figure 4 This is a packaging design line diagram of an embodiment of the packaging structure provided by the present utility model;

[0056] Figure 5 This is a package design line diagram of another embodiment of the package structure provided by the present invention;

[0057] Figure 6 This is a packaging design line diagram of another embodiment of the packaging structure provided by the present invention.

[0058] Reference numerals:

[0059] 1-first pin;

[0060] 2- Second pin;

[0061] 3- third pin;

[0062] 4-Signal pin;

[0063] 5-First base island;

[0064] 6- Second base island;

[0065] 7-encapsulation body;

[0066] 8- first control chip;

[0067] 9-first power chip;

[0068] 10- second control chip;

[0069] 11- second power chip;

[0070] 12-third power chip;

[0071] 13- third control chip;

[0072] 401-first width signal pin;

[0073] 402-second width signal pin;

[0074] 4011-first signal pin;

[0075] 4012-second signal pin;

[0076] 4013-third signal pin;

[0077] 4014-fourth signal pin;

[0078] 4015-Fifth signal pin. DETAILED DESCRIPTION

[0079] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0080] In the description of the specification of the present invention, it should be understood that the terms "upper part", "lower part", "upper end", "lower end", "lower surface", "upper surface", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they cannot be understood as limitations on the present invention.

[0081] In the description of this utility model, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, features specified as "first" or "second" may explicitly or implicitly include one or more of such features.

[0082] In the description of the present invention, “a plurality of” means multiple, such as two, three, four, etc., unless otherwise clearly defined.

[0083] In the description of this utility model, unless otherwise specified or limited, the term "connection" and other terms should be understood in a broad sense. For example, it can mean fixed connection, detachable connection, or integration; it can mean mechanical connection, electrical connection, or mutual communication; it can mean direct connection or indirect connection through an intermediate medium; it can mean internal communication between two components or interaction between two components. For those skilled in the art, the specific meanings of the above terms in this utility model can be understood according to specific circumstances.

[0084] The following specific embodiments are used to describe the technical solution of the present invention in detail. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0085] As described in the background art, the conventional packaging of IC control chips and high-power chips usually causes interference between the chips and a safety issue in that the high-voltage pins and the low-voltage pins do not meet the safety distance requirement.

[0086] In view of this, the present invention creatively proposes a lead frame.

[0087] in, Figure 1 This is a schematic diagram of the structure of an embodiment of the lead frame provided by the utility model. Figure 1 .

[0088] Please refer to Figure 1 An embodiment of the present invention provides a lead frame, comprising:

[0089] Two base islands, the two base islands include a first base island 5 and a second base island 6, a first distance exists between the first base island 5 and the second base island 6, each base island includes a first surface for carrying a chip and a second surface opposite to the first surface;

[0090] A plurality of signal pins 4, wherein the plurality of signal pins 4 are arranged at intervals;

[0091] The first pin 1 and the second pin 2 , the distance between the first pin 1 and the plurality of signal pins 4 and the distance between the second pin 2 and the plurality of signal pins 4 are greater than or equal to the second distance.

[0092] The second distance is specifically used to represent the safe distance between high-voltage pins and low-voltage pins in the chip packaging field. Specifically, the second distance can be set to 1.7 mm. Of course, the specific value of the second distance can be set accordingly according to different application scenarios, and this utility model does not limit this.

[0093] The first base island 5 can be used to place an IC control chip, and the second base island 6 can be used to place a high-power chip such as a MOS.

[0094] Through the above technical means, the embodiments of the present invention can not only reduce the mutual interference between the two chips, but also flexibly design the packaging circuit based on the safety distance between the high-voltage pin and the low-voltage pin. The specific principle is as follows:

[0095] In a lead frame provided by the present invention, on the one hand, the interference between the two chips is reduced by setting two base islands; on the other hand, the distance between the first pin 1 and the multiple signal pins 4 and the distance between the second pin 2 and the multiple signal pins 4 are both greater than or equal to the second distance, that is, the first pin 1 and the second pin 2 are both safely isolated, so the first pin 1 and the second pin 2 can both be set as high-voltage pins, thereby making the design of the package line diagram more flexible.

[0096] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0097] in, Figure 2 This is a schematic diagram of the structure of an embodiment of the lead frame provided by the utility model. Figure 2 , Figure 3 It is a structural schematic diagram of another embodiment of the lead frame provided by the present invention.

[0098] Please refer to Figure 2 or Figure 3 As a specific embodiment, the lead frame further includes a plurality of third pins 3, which are directly connected to the second base island 6. The distances between the third pins 3 and the plurality of signal pins 4, the first pin 1, and the second pin 2 are all greater than or equal to the second distance, and the width of the third pin 3 is greater than the width of the signal pin 4.

[0099] Specifically, the width of a single third pin 3 can be set to about 0.87 mm, while the width of a conventional signal pin 4 is about 0.22 mm. Furthermore, because several third pins 3 are directly connected to the second base island 6, the heat dissipation capability of the chip on the second base island 6 is improved.

[0100] As an alternative, in addition to providing several separate third pins 3, the third pins 3 can also be integrated together to form a wider pin. For example, three separate third pins 3 are provided, and each third pin 3 has a width of 0.87 mm. These three third pins 3 can also be replaced with one 0.87 mm pin and one 1.74 mm pin, or with a whole 3.5 mm pin. The specific configuration can be selected according to needs and is not limited here.

[0101] Furthermore, because the distances between the third pin 3 and the plurality of signal pins 4, the first pin 1, and the second pin 2 are all greater than or equal to the second distance, that is, the distance between the third pin 3 and the other pins also meets the safety distance between high- and low-voltage pins, the third pin 3 can also be configured as a high-voltage pin. This means that the first pin 1, the second pin 2, and the third pin 3 can all be configured as high-voltage pins as needed, further increasing the flexibility of setting the package wiring diagram.

[0102] It should be noted that this embodiment does not limit the functions of the first pin 1 , the second pin 2 and the third pin 3 . Any lead frame that meets the above design specifications is within the protection scope of the present invention.

[0103] As a specific embodiment, the third pin 3 is used for high voltage output, and the first pin 1 and the second pin 2 are used for low voltage output. This enables the third pin 3 to take into account the dual functions of heat dissipation and high voltage output.

[0104] As a specific implementation, the first pin 1 and the second pin 2 are used for high voltage output, and the other pins are used for low voltage output.

[0105] Please refer to Figure 2 As a specific implementation, the width of the first pin 1 is set to be greater than the width of the second pin 2. Specifically, the width of the first pin 1 is set to be about 0.87 mm, and the width of the second pin 2 is set to be about 0.22 mm.

[0106] The beneficial effects of setting the width of the first pin 1 to be greater than the width of the second pin 2 are:

[0107] The wider first pin 1 can output a higher voltage and current than the second pin 2 , which allows for greater flexibility in designing a package diagram and broadens the application scenarios of the lead frame of the present invention.

[0108] Of course, in addition to the above embodiment, the width of the first pin 1 and the width of the second pin 2 can also be the same. For details, please refer to Figure 3 .

[0109] It should be noted that there is no limitation on the width of the first pin 1 and the second pin 2. As long as the distance between the first pin 1 and the plurality of signal pins 4 is greater than the second distance and the distance between the second pin 2 and the plurality of signal pins 4 is also greater than the second distance, the structure is within the scope of protection of the present invention.

[0110] Please refer to Figure 2 or Figure 3 As a specific embodiment, the plurality of signal pins 4 include a first width signal pin 401 and at least one second width signal pin 402 , and the width of the second width signal pin 402 is greater than the width of the first width signal pin 401 .

[0111] The beneficial effects of setting the second width signal pin 402 are:

[0112] The width of the second-width signal pin 402 is greater than that of the first-width signal pin 401 , so that the second pin 2 can be used to weld more pairs of wires, thereby increasing the overcurrent capacity and reducing the impedance.

[0113] Specifically, the width of the second width signal pin 402 is between 0.22 mm and 0.87 mm. Of course, the specific width of the second width signal pin 402 can be set according to needs, and the present invention does not limit it here.

[0114] As a specific embodiment, at least one first-width signal pin 401 is directly connected to the first base island 5. The first-width signal pin 401 directly connected to the first base island 5 can serve as both a signal output pin and a base island support pin.

[0115] In summary, the present invention provides a lead frame in which a double base island is provided to separate two chips so as to reduce the mutual interference between the two chips; the distance between the first pin and a plurality of signal pins is set to be greater than or equal to the second distance, and the distance between the second pin and a plurality of signal pins is set to be greater than or equal to the second distance, so that both the first pin and the second pin can be set as high-voltage pins, thereby increasing the flexibility of designing the package line diagram while ensuring product safety.

[0116] Furthermore, the lead frame also includes a plurality of third pins, which are directly connected to the second base island and have a width greater than that of the signal pins, so that the chip on the second base island can not only dissipate heat better but also pass large current.

[0117] Furthermore, if the distances between the third pin and the plurality of signal pins, the first pin, and the second pin are all greater than or equal to the second distance, the third pin can also be used for high-voltage output. Furthermore, when the third pin is used for high-voltage output, the third pin can simultaneously provide both heat dissipation and high-voltage output.

[0118] Furthermore, the width of the first pin is greater than or equal to the width of the second pin. When the width of the first pin is greater than the width of the second pin, the first pin can be used to output a higher voltage than the second pin, thereby making the lead frame suitable for more complex application scenarios. The two high-voltage output pins of different widths also make the package design more flexible.

[0119] Furthermore, the several signal pins 4 include a first width signal pin and at least one second width signal pin, wherein the width of the second width signal pin is greater than the width of the first pin 1, so that the second width signal pin can weld more pairs of wires than the first width signal pin, which not only increases the overcurrent capacity of the second width signal pin, but also reduces the impedance of the second width signal pin.

[0120] Please refer to Figure 4 The present invention also provides a packaging structure, which includes the lead frame, the first control chip 8, the first power chip 9 and the packaging body 7; the packaging body 7 is used to encapsulate the lead frame, the first control chip 8 and the first power chip 9.

[0121] The first control chip 8 is mounted on the first surface of the first base island 5 , and the first power chip 9 is mounted on the first surface of the second base island 6 .

[0122] As a specific embodiment, the first control chip 8 is an IC control chip containing high voltage, and the first power chip 9 can be, for example, a planar MOS chip of gallium nitride or silicon carbide type; wherein, the first control chip 8 is electrically connected to the gate of the first power chip 9, so that the first control chip 8 can control the first power chip 9.

[0123] The signal pins specifically include:

[0124] a first signal pin 4011, the first signal pin 4011 being directly connected to the first base island 5 and used to support the first base island 5, and the first signal pin 4011 being used as a free pin; wherein the free pin is used to represent a pin that is neither grounded nor used to transmit any signal;

[0125] A second signal pin 4012, the second signal pin 4012 is electrically connected to the first control chip 8 and is used for voltage and current detection;

[0126] A third signal pin 4013 , the third signal pin 4013 is electrically connected to the first control chip 8 and is used for optocoupler current feedback detection;

[0127] a fourth signal pin 4014 , the fourth signal pin 4014 being electrically connected to the first control chip 8 and used for source circuit detection;

[0128] a fifth signal pin 4015 , the fifth signal pin 4015 being electrically connected to the first power chip 9 and used for power input;

[0129] A sixth signal pin is electrically connected to the first power chip 9 and is used for current output.

[0130] Among them, the first signal pin 4011, the second signal pin 4012, the third signal pin 4013, the fourth signal pin 4014 and the fifth signal pin 4015 are all first width signal pins 401, and the sixth signal pin is a second width signal pin 402; therefore, multiple pairs of lines can be welded between the sixth signal pin and the first power chip 9, thereby increasing the overcurrent capacity of the sixth signal pin, so that the source maximum current of the first power chip 9 can be output.

[0131] The first pin 1 is electrically connected to the first power chip 9, and the second pin 2 is electrically connected to the first control chip 8. Both the first pin 1 and the second pin 2 are used for high-voltage current input. Specifically, the first pin 1 is used as the drain current input pin of the first power chip 9; the second pin 2 is used as the current input pin when the first control chip 8 is started.

[0132] Among them, several third pins 3 are all grounded and serve as heat dissipation pins to enhance the heat dissipation of the first power chip 9.

[0133] Please refer to Figure 5 The present invention also provides a packaging structure, which includes the lead frame, the second control chip 10, the second power chip 11 and the packaging body 7; the packaging body 7 is used to encapsulate the lead frame, the second control chip 10 and the second power chip 11.

[0134] The second control chip 10 is mounted on the first surface of the first base island 5 , and the second power chip 11 is mounted on the first surface of the second base island 6 .

[0135] As a specific embodiment, the second control chip 10 is an IC control chip without high voltage, and the second power chip 11 can be, for example, a planar MOS chip of gallium nitride or silicon carbide type; wherein, the second control chip 10 is electrically connected to the gate of the second power chip 11, so that the second control chip 10 can control the second power chip 11.

[0136] The signal pins specifically include:

[0137] A first signal pin 4011, which is directly connected to the first base island 5 and is used to support the first base island 5, and is grounded;

[0138] A second signal pin 4012 , the second signal pin 4012 is electrically connected to the second control chip 10 and is used for source current detection;

[0139] A third signal pin 4013, the third signal pin 4013 is electrically connected to the second control chip 10 and is used for voltage and current detection;

[0140] A fourth signal pin 4014 , the fourth signal pin 4014 being electrically connected to the second control chip 10 and used for optocoupler current feedback detection;

[0141] The fifth signal pin 4015 and the sixth signal pin are both electrically connected to the second power chip 11 and used for current output.

[0142] Among them, the first signal pin 4011, the second signal pin 4012, the third signal pin 4013, the fourth signal pin 4014 and the fifth signal pin 4015 are all first width signal pins 401, and the sixth signal pin is a second width signal pin 402; therefore, multiple pairs of lines can be welded between the sixth signal pin and the second power chip 11, thereby increasing the overcurrent capacity of the sixth signal pin, so that the source maximum current of the second power chip 11 can be output.

[0143] Among them, the first pin 1 is electrically connected to the second power chip 11 and is used for high-voltage current input; the second pin 2 is electrically connected to the second control chip 10 and is used for power input; specifically, the first pin 1 is used as the drain current input of the first power chip 9, the second pin 2 is used as the power input of the second control chip 10, and the second pin 2 is a low-voltage pin.

[0144] The second pin 2 is adjacent to the first signal pin 4011 , that is, the power input of the second control chip 10 is adjacent to the ground, and its location is convenient for the design and nearby use of the peripheral circuit of the package structure.

[0145] Among them, a plurality of third pins 3 are all grounded and serve as heat dissipation pins to enhance the heat dissipation of the second power chip 11 .

[0146] Please refer to Figure 6 The present invention also provides a packaging structure, which includes the lead frame, the third control chip 13, the third power chip 12 and the packaging body 7; the packaging body 7 is used to encapsulate the lead frame, the third control chip 13 and the third power chip 12.

[0147] The third control chip 13 is mounted on the first surface of the first base island 5 , and the third power chip 12 is mounted on the first surface of the second base island 6 .

[0148] As a specific embodiment, the third control chip 13 is an IC control chip without high voltage, and the third power chip 12 is a high-voltage MOS chip; wherein, the third control chip 13 is electrically connected to the gate of the third power chip 12, so that the third control chip 13 can control the third power chip 12.

[0149] The plurality of signal pins 4 specifically include:

[0150] A first signal pin 4011, which is directly connected to the first base island 5 and is used to support the first base island 5, and is grounded;

[0151] A second signal pin 4012 , the second signal pin 4012 is electrically connected to the third control chip 13 and is used for source current detection;

[0152] A third signal pin 4013, the third signal pin 4013 is electrically connected to the third control chip 13 and is used for voltage and current detection;

[0153] A fourth signal pin 4014 , the fourth signal pin 4014 is electrically connected to the third control chip 13 and is used for optocoupler current feedback detection;

[0154] The fifth signal pin 4015 and the sixth signal pin are both electrically connected to the third power chip 12 and are used for outputting the source current of the third power chip 12 .

[0155] Among them, the first signal pin 4011, the second signal pin 4012, the third signal pin 4013, the fourth signal pin 4014 and the fifth signal pin 4015 are all first width signal pins 401, and the sixth signal pin is a second width signal pin 402; therefore, multiple pairs of lines can be welded between the sixth signal pin and the third power chip 12, thereby increasing the overcurrent capacity of the sixth signal pin, so that the source maximum current of the third power chip 12 can be output.

[0156] The first pin 1 is grounded and electrically connected to the first base island 5 ; the second pin 2 is electrically connected to the third control chip 13 and is used for inputting a power supply voltage to the third control chip 13 .

[0157] The second pin 2 is adjacent to the first signal pin 4011 , that is, the power input of the third control chip 13 is adjacent to the ground, and its location is convenient for the design and nearby use of the peripheral circuit of the package structure.

[0158] Among them, the lead frame also includes three third pins 3, all of which are used for high-voltage end current input; since the drain of the third power chip 12 is attached to the first surface of the second base island 6, the third pin 3 can be used to input the large drain current of the third power chip 12, and the third pin 3 can also enhance the heat dissipation of the third power chip 12.

[0159] Although the present invention is disclosed as above, it is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope defined by the claims.

Claims

1. A lead frame, characterized in that: include: Two base islands, the two base islands include a first base island and a second base island, a first distance exists between the first base island and the second base island, and each base island includes a first surface for carrying a chip and a second surface opposite to the first surface; A plurality of signal pins, wherein the plurality of signal pins are arranged at intervals; The first pin, the second pin, the distance between the first pin and the plurality of signal pins, and the distance between the second pin and the plurality of signal pins are both greater than or equal to the second distance.

2. The lead frame according to claim 1, wherein: The device further includes a plurality of third pins, which are directly connected to the second base island, and the width of the third pins is greater than the width of the signal pins.

3. The lead frame according to claim 2, wherein: The distance between the third pin and the plurality of signal pins, the first pin, and the second pin is greater than or equal to the second distance.

4. The lead frame according to claim 3, wherein: The second distance is 1.7 mm.

5. The lead frame according to claim 1, wherein The plurality of signal pins include a first-width signal pin and at least one second-width signal pin, wherein the width of the second-width signal pin is greater than the width of the first-width signal pin.

6. The lead frame according to claim 5, wherein: The width of the second-width signal pin is between 0.22 mm and 0.87 mm.

7. The lead frame according to claim 1, wherein: The width of the first pin is greater than the width of the second pin.

8. A packaging structure, characterized in that: The packaging structure comprises the lead frame according to any one of claims 1 to 7, a first control chip, a first power chip, and a packaging body; the packaging body is used to encapsulate the lead frame, the first control chip, and the first power chip; The first control chip is mounted on the first surface of the first base island, and the first power chip is mounted on the first surface of the second base island; The signal pins specifically include: a first signal pin, the first signal pin being directly connected to the first base island and being used to support the first base island; a second signal pin, the second signal pin being electrically connected to the first control chip and used for voltage and current detection; a third signal pin, the third signal pin being electrically connected to the first control chip and used for optocoupler current feedback detection; a fourth signal pin, the fourth signal pin being electrically connected to the first control chip and used for source circuit detection; a fifth signal pin, the fifth signal pin being electrically connected to the first power chip and used for power input; a sixth signal pin, the sixth signal pin being electrically connected to the first power chip and used for current output; The first pin is electrically connected to the first power chip, the second pin is electrically connected to the first control chip, and both the first pin and the second pin are used for high-voltage current input.

9. A packaging structure, characterized in that: The packaging structure comprises the lead frame according to any one of claims 1 to 7, a second control chip, a second power chip, and a packaging body; the packaging body is used to encapsulate the lead frame, the second control chip, and the second power chip; The second control chip is mounted on the first surface of the first base island, and the second power chip is mounted on the first surface of the second base island; The signal pins specifically include: a first signal pin, the first signal pin being directly connected to the first base island and being used to support the first base island, and the first signal pin being grounded; a second signal pin, the second signal pin being electrically connected to the second control chip and used for source current detection; a third signal pin, the third signal pin being electrically connected to the second control chip and used for voltage and current detection; a fourth signal pin, the fourth signal pin being electrically connected to the second control chip and used for optocoupler current feedback detection; a fifth signal pin and a sixth signal pin, wherein the fifth signal pin and the sixth signal pin are both electrically connected to the second power chip and used for current output; The first pin is electrically connected to the second power chip and is used for high-voltage current input; the second pin is electrically connected to the second control chip and is used for power input.

10. A packaging structure, characterized in that: The packaging structure comprises the lead frame according to any one of claims 1 to 7, a third control chip, a third power chip, and a packaging body; the packaging body is used to package the lead frame, the third control chip, and the third power chip; The third control chip is mounted on the first surface of the first base island, and the third power chip is mounted on the first surface of the second base island; The signal pins specifically include: a first signal pin, the first signal pin being directly connected to the first base island and being used to support the first base island, and the first signal pin being grounded; a second signal pin, the second signal pin being electrically connected to the third control chip and used for source current detection; a third signal pin, the third signal pin being electrically connected to the third control chip and used for voltage and current detection; a fourth signal pin, the fourth signal pin being electrically connected to the third control chip and used for optocoupler current feedback detection; a fifth signal pin and a sixth signal pin, wherein the fifth signal pin and the sixth signal pin are both electrically connected to the third power chip and are used for current output; Wherein, the first pin is grounded and electrically connected to the first base island; the second pin is electrically connected to the third control chip and is used for power supply voltage input; The lead frame further includes three third pins, all of which are used for high-voltage current input.

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