Semiconductor structure

Abstract

The semiconductor structure includes first standard cells having first active regions formed over alternating first n-type wells and first p-type wells, the first active regions and the alternating first n-type wells and first p-type wells each extending longitudinally in a first direction, each first standard cell including a first n-type well and a first p-type well; and a second standard cell adjacent to the first standard cell, the second standard cell having a second active region formed over alternating second n-type wells and second p-type wells, the second active region and alternating second n-type wells and second p-type wells each extending longitudinally in the first direction, each second standard cell including a second n-type well and a second p-type well. The first standard cell has a first cell height, the second standard cell has a second cell height, and the second cell height is greater than the first cell height.

Description

Technical Field

[0001] The utility model relates to a semiconductor structure, in particular to a standard unit device layout with different unit heights. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Advances in semiconductor manufacturing technology have produced generations of integrated circuits, each with smaller and more complex circuits than the previous one. IC evolution has typically increased functional density (the number of interconnected IC components per chip area) while simultaneously decreasing geometry (the size and / or dimensions of IC features and / or the spacing between these IC features).

[0003] To facilitate aggressive scaling and increase functional density, standard cells have been developed as fundamental building blocks in the design and manufacture of integrated circuit semiconductor structures. Due to their compactness and reusability, standard cells serve design applications with minimal area cost. Generally, standard cells have a fixed height and consist of n-type and p-type wells of equal size periodically placed on a substrate. The periodic fixed height is defined by the width of the n-type well plus the width of the p-type well, upon which the integrated circuit structure is formed. The integrated circuit structure includes the corresponding device (or active region) placed in each standard cell, along with a gate, metal contacts, and upper metal / vias, some of which may span multiple cells. Integrated circuit structures placed on standard cells may have limited geometry and size to simplify process complexity and achieve aggressive scaling goals.

[0004] However, the fixed cell height in a standard cell limits the choice of device size, which can be critical in certain applications. For example, in a device array, some devices require a wider active area than is available in a single standard cell height (e.g., to drive higher currents), while other devices require a narrower active area than is available in a single standard cell height (e.g., for better leakage control).

[0005] Thus, while existing layouts and structures associated with standard cells are generally adequate for their intended purposes, they are not entirely satisfactory in every respect. Utility Model Content

[0006] Some embodiments of the present disclosure provide a semiconductor structure. The semiconductor structure includes a plurality of first standard cells and a plurality of second standard cells. The first standard cells have a plurality of first active regions formed above a plurality of alternating first n-type wells and first p-type wells. The first active regions and the alternating first n-type wells and first p-type wells each extend longitudinally along a first direction, and each first standard cell includes a first n-type well and a first p-type well. A second standard cell is adjacent to the first standard cell along the first direction and has a plurality of second active regions formed above a plurality of alternating second n-type wells and second p-type wells. The second active regions and the alternating second n-type wells and second p-type wells each extend longitudinally along the first direction, and each second standard cell includes a second n-type well and a second p-type well. The first standard cell has a first cell height along a second direction perpendicular to the first direction, and the second standard cell has a second cell height along the second direction, the second cell height being greater than the first cell height. The second active region has a greater width along the second direction than the first active region. In some embodiments, the semiconductor structure further includes: a plurality of metal gates located above the plurality of first active regions and the plurality of second active regions, the plurality of metal gates extending longitudinally along the second direction; and a plurality of first source / drain contacts and a plurality of second source / drain contacts located above the plurality of first active regions and the plurality of second active regions, respectively, with each of the metal gates inserted between the plurality of first source / drain contacts and the plurality of second source / drain contacts along the first direction, wherein the plurality of first source / drain contacts have a first length along the second direction, and the plurality of second source / drain contacts have a second length along the second direction, and the second length is greater than the first length.

[0007] In some embodiments, the semiconductor structure further includes: a plurality of metal vias located above the plurality of metal gates and above the plurality of first source / drain contacts and the plurality of second source / drain contacts; and a plurality of metal lines extending longitudinally along the first direction above the plurality of metal vias, wherein the plurality of metal lines have the same width along the second direction when extending above the plurality of first standard cells and the plurality of second standard cells.

[0008] In some embodiments, the semiconductor structure further includes: a plurality of metal vias located above the plurality of metal gates and above the plurality of first source / drain contacts and the plurality of second source / drain contacts; and a plurality of metal lines extending longitudinally along the first direction above the plurality of metal vias, wherein when the plurality of metal lines extend above the plurality of first standard cells, the plurality of metal lines have a first metal width along the second direction, and when the plurality of metal lines extend above the plurality of metal line second standard cells, the plurality of metal lines have a second metal width along the second direction, and the second metal width is greater than the first metal width.

[0009] Other embodiments of the present disclosure provide a semiconductor structure. The semiconductor structure includes a plurality of first standard cells, a plurality of second standard cells, a plurality of metal gates, and a dielectric gate. The first standard cells have a plurality of first active regions formed above a plurality of alternating first n-type wells and first p-type wells, with the first active regions and the alternating first n-type wells and first p-type wells each extending longitudinally along a first direction. A second standard cell is adjacent to the first standard cell along the first direction and has a plurality of second active regions formed above a plurality of alternating second n-type wells and second p-type wells, with the second active regions and the alternating second n-type wells and second p-type wells each extending longitudinally along the first direction. A metal gate is located above the first and second active regions in the first and second standard cells, with the metal gate extending longitudinally along a second direction perpendicular to the first direction. A dielectric gate is located between the first and second standard cells and at a transition boundary between the alternating first n-type wells and first p-type wells and the alternating second n-type wells and second p-type wells, with the dielectric gate extending longitudinally along the second direction. The first n-type well and the first p-type well have a first width along the second direction, the second n-type well and the second p-type well have a second width along the second direction, and the second width is greater than the first width.

[0010] In some embodiments, wherein the dielectric gate is a first dielectric gate, the semiconductor structure further comprises: a transition well located between the plurality of first standard cells and the plurality of second standard cells along the first direction; and a second dielectric gate, wherein the transition well transitions the plurality of first widths of the plurality of first n-type wells and the plurality of first p-type wells to the plurality of second widths of the plurality of second n-type wells and the plurality of second p-type wells, wherein the first dielectric gate extends along a first edge of the transition well in the second direction, and the second dielectric gate extends along a second edge of the transition well in the second direction.

[0011] In some embodiments, the semiconductor structure further includes: a plurality of metal lines extending longitudinally along the first direction above the plurality of first standard cells and the plurality of second standard cells, wherein the plurality of metal lines above the plurality of first standard cells and the plurality of metal lines above the plurality of second standard cells are separated by a gap in the transition well.

[0012] In some embodiments, the semiconductor structure further includes: a plurality of third standard cells having a plurality of third active regions formed above a plurality of alternating third n-type wells and third p-type wells, the plurality of third active regions and the plurality of alternating third n-type wells and third p-type wells each extending longitudinally along the first direction, wherein the plurality of third n-type wells and the plurality of third p-type wells have the first width along the second direction, wherein the plurality of first standard cells and the plurality of third standard cells are directly adjacent to each other along the second direction, and the plurality of second standard cells and the plurality of third standard cells are directly adjacent to each other along the second direction.

[0013] Some further embodiments of the present disclosure provide a semiconductor structure. The semiconductor structure includes a first standard cell, a second standard cell, and a dielectric gate. The first standard cell has a first n-type well and a first p-type well extending longitudinally along a first direction. The second standard cell is adjacent to the first standard cell along the first direction, and the second standard cell has a second n-type well and a second p-type well extending longitudinally along the first direction. The dielectric gate is located at a boundary between the first standard cell and the second standard cell, and the dielectric gate extends longitudinally along a second direction perpendicular to the first direction. The first standard cell has a first cell height along the second direction, the second standard cell has a second cell height along the second direction, and the second cell height is greater than the first cell height.

[0014] In some embodiments, the semiconductor structure further includes: a first active region extending longitudinally along the first direction above the first n-type well; a second active region extending longitudinally along the first direction above the first p-type well; a third active region extending longitudinally along the first direction above the second n-type well; and a fourth active region extending longitudinally along the second direction above the second p-type well, wherein the third active region and the fourth active region have a greater width along the second direction than the first active region and the second active region.

[0015] At least one embodiment of the present invention has the following advantages or technical effects: One exemplary advantage is the formation of multiple standard cells having wells of different sizes adjacent to each other. Wells of different sizes can accommodate device active regions of different sizes on the standard cell block. Another exemplary advantage is the periodic alignment of different standard cells to facilitate integration with a larger standard cell device layout. Another exemplary advantage is the incorporation of one or more dielectric gates between standard cells of different cell heights for proper isolation between device active regions. These dielectric gates can be set above the transition boundaries of different standard cells or above the transition boundary of a transition well. Another exemplary advantage is allowing the same upper metal line setting across different standard cells to simplify the process, or allowing customized upper metal line setting across different standard cells to improve the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The present disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, in accordance with standard practice in the industry, various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion. It is also emphasized that the drawings illustrate only some embodiments of the present disclosure and, therefore, should not be considered limiting of the scope, as the present disclosure is equally applicable to other embodiments. Furthermore, the drawings may implicitly depict features that are not explicitly described in the detailed description.

[0017] Figure 1AA top view of a device layout defined by standard cells according to an embodiment of the present disclosure is shown, and an n-type well and a p-type well above a substrate are shown.

[0018] Figure 1B A top view of a device layout defined by standard cells according to an embodiment of the present disclosure is shown, and Figure 1A The device-level structure above the n-type well and p-type well.

[0019] Figure 1C A top view of a device layout defined by standard cells according to an embodiment of the present disclosure is shown, and Figure 1B The metal lines above the device-level structures.

[0020] Figure 1D Showing the embodiment of the present disclosure Figures 1A-1C A cross-sectional view of a semiconductor structure in a device area of ​​a device layout in FIG.

[0021] Figure 2A A top view of a device layout defined by standard cells according to an embodiment of the present disclosure is shown, and an n-type well and a p-type well above a substrate are shown.

[0022] Figure 2B A top view of a device layout defined by standard cells according to an embodiment of the present disclosure is shown, and Figure 2A The device-level structure above the n-type well and p-type well.

[0023] Figure 2C A top view of a device layout defined by standard cells according to an embodiment of the present disclosure is shown, and Figure 2B The metal lines above the device-level structures.

[0024] Figure 2D Cross-sectional views of semiconductor structures in the device region of the device layout in Figures 2A-2C are shown according to embodiments of the present disclosure.

[0025] Figure 3A 、 3B 3C shows a top view of different layers of a device layout defined by standard cells according to an embodiment of the present disclosure, and shows dielectric gates between standard cells.

[0026] Figure 4A 、 4B 4C shows a top view of different layers of a device layout defined by standard cells according to an embodiment of the present disclosure, and shows transition wells between standard cells.

[0027] Figure 5A A top view of a device layout block defined by standard cells according to an embodiment of the present disclosure is shown, and an n-type well and a p-type well above a substrate are shown.

[0028] Figure 5B A top view of a device layout block defined by standard cells according to an embodiment of the present disclosure is shown, and Figure 5A The device-level structure above the n-type well and p-type well.

[0029] Figure 5C-1 A top view of a device layout block defined by standard cells according to an embodiment of the present disclosure is shown, and Figure 5B The metal lines above the device-level structures.

[0030] Figure 5C-2 A top view of a device layout block defined by standard cells according to another embodiment of the present disclosure is shown, and Figure 5B The metal lines above the device-level structures.

[0031] The accompanying drawings are described as follows:

[0032] 100: Standard cell device layout

[0033] 150: Mixed area

[0034] 200:First standard unit

[0035] 202: First active area

[0036] 204: first metal gate

[0037] 206: first metal contact

[0038] 208: first metal through hole

[0039] 202n: first n-type well

[0040] 202p: first p-type well

[0041] 250: Standard unit

[0042] 300: Second standard unit

[0043] 302n: second n-type well

[0044] 302p: second p-type well

[0045] 302: Second active area

[0046] 304: second metal gate

[0047] 306: Second metal contact

[0048] 308: Second metal through hole

[0049] 350: Installation area

[0050] 402a, 402b: Metal wire

[0051] 404: dielectric gate

[0052] 500: Transition well

[0053] 1000: Device layout block

[0054] y1: height of the first unit

[0055] y2: Height of the second unit

[0056] w1: first width

[0057] w2: second width

[0058] w3: third width

[0059] w4: fourth width. DETAILED DESCRIPTION

[0060] The following disclosure provides many different embodiments or examples for implementing different components of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these examples are merely examples and do not limit the present disclosure. For example, if the specification describes that a first component is formed above or on a second component, it means that it may include an embodiment in which the first component and the second component are in direct contact, and may also include an embodiment in which an additional component is formed between the first component and the second component, so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference element symbols and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself specify the relationship between the various embodiments and / or configurations discussed.

[0061] Additionally, spatially relative terms such as "below," "beneath," "below," "above," "upper," and similar terms are used to facilitate describing the relationship of one element or component to another element or component in the drawings. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device may be referenced in different orientations (rotated 90 degrees or at other orientations), and the spatially relative terms used herein should be interpreted accordingly.

[0062] Furthermore, when "about," "approximately," or the like is used to describe a number or range of numbers, such terms are intended to encompass numbers within a reasonable range that includes the described number, such as within + / - 10% of the described number, or other values ​​understood by one of ordinary skill in the art. For example, the term "approximately 5 nm" includes a size range from 4.5 nm to 5.5 nm. Also, when comparing a size or dimension of one component to another, terms such as "substantially the same," "substantially the same," "similar in size," or the like should be understood to mean within + / - 10% between the two compared components, or other values ​​understood by one of ordinary skill in the art. Furthermore, the disclosed dimensions of different features may implicitly disclose the ratio of dimensions between the different features.

[0063] The present disclosure generally relates to standard cell device layouts with different cell heights. Standard cells can be used in integrated circuit design to achieve compact device layouts and manufacture corresponding semiconductor structures. However, when standard cells are limited to a single fixed cell height, device options are limited. In order to allow flexibility in device size, the present disclosure provides standard cells with multiple sizes of n-type wells and p-type wells while accommodating a standard cell frame. That is, in a standard cell block, standard cells with n-type wells and p-type wells of different sizes can be integrated together. Having n-type wells and p-type wells of different sizes allows device and contact sizes / locations to vary based on performance requirements. At the same time, the metal lines on the device-level structure have the flexibility to maintain the same settings as the single fixed cell height solution, or to adopt wider sizes when needed. The present disclosure also considers incorporating dielectric gates between standard cells of different cell heights for isolation between devices.

[0064] The embodiments shown in this disclosure are implemented using gate-all-around (GAA) field-effect transistors (FETs), but the disclosure is not limited thereto. A gate-all-around field-effect transistor is a transistor having a gate stack (gate electrode and gate dielectric layer) surrounding the transistor channel, such as a vertically stacked gate-all-around horizontal nanowire or nanosheet metal oxide semiconductor field-effect transistor (MOSFET) device. The transistor channel and adjacent source / drain components are formed by an active region above a substrate, such as a fin-type active region protruding from the substrate.

[0065] Those skilled in the art will readily appreciate that they can readily use this disclosure as a basis for designing or modifying other structures to achieve the same objectives and / or advantages as the embodiments described herein. For example, other types of field effect transistors, such as planar metal oxide semiconductor field effect transistors or fin field effect transistors (FinFETs), can also implement the embodiments of this disclosure.

[0066] Figure 1AA top view of a standard cell device layout 100 (device layout 100) according to an embodiment of the present disclosure is shown. Device layout 100 includes a first standard cell 200 and a second standard cell 300, each of which has an n-type well and a p-type well alternating along the y-direction. The alternating n-type wells and p-type wells can be formed in a substrate by a suitable doping process, such as ion implantation, diffusion, other suitable techniques, or a combination thereof. The substrate can be a silicon (Si) substrate, or a substrate having other semiconductor materials such as germanium (Ge), silicon carbide (SiC), silicon germanium (SiGe), or diamond. Each first standard cell 200 includes a first n-type well 202n and a first p-type well 202p, wherein each first standard cell 200 has a first cell height y1 defined by the combined width of the first n-type well 202n and the first p-type well 202p along the y-direction. In this embodiment, the first n-type well 202n and the first p-type well 202p have substantially the same width. Each second standard cell 300 includes a second n-type well 302n and a second p-type well 302p, wherein each second standard cell 300 has a second cell height y2 defined by the combined width of the second n-type well 302n and the second p-type well 302p along the y-direction. In this embodiment, the second n-type well 302n and the second p-type well 302p have substantially the same width. As shown, the second cell height y2 is greater than the first cell height y1. Therefore, the second n-type well 302n has a greater width along the y-direction than the first n-type well 202n, and the second p-type well 302p has a greater width along the y-direction than the first p-type well 202p. The ratio of the second cell height y2 to the first cell height y1 can range from approximately 1.25 to approximately 2. In this embodiment, the ratio of the second cell height y2 to the first cell height y1 is approximately 1.5.

[0067] Still refer to Figure 1A Along the x-direction, the edge boundaries of the first standard cell 200 are periodically aligned with the edge boundaries of the second standard cell 300. In this embodiment, the edge boundaries of the first standard cell 200 and the second standard cell 300 are periodically aligned after every three first standard cell heights y1 and after every two second standard cell heights y2. At these edge boundaries, the alternating n-type wells and p-type wells in the first standard cell 200 are aligned with the alternating n-type wells and p-type wells in the second standard cell 300 along the x-direction. Furthermore, at each edge boundary of the second standard cell 300, the first n-type well 202n is aligned with the second n-type well 302n, and the first p-type well 202p is aligned with the second p-type well 302p.

[0068] Still refer to Figure 1AAlthough the device layout 100 is described using two different first standard cells 200 and second standard cells 300 adjacent to each other along the x-direction and having different fixed first standard cell heights y1 and second standard cell heights y2, the device layout 100 may be described in other ways without departing from the spirit and scope of the present disclosure. For example, Figure 1A Although the standard cells 250 may be described as having a single, fixed first standard cell height y1 or second standard cell height y2, each standard cell 250 includes both the first n-type well 202n and the first p-type well 202p, as well as both the second n-type well 302n and the second p-type well 302p. In other words, the standard cells 250 having the fixed first standard cell height y1 or second standard cell height y2 may have different well width settings within the same standard cell 250, such that the edge boundaries of the n-type well and the p-type well are not always aligned between the standard cells 250.

[0069] Figure 1B A top view of the device layout 100 defined by the first standard cell 200 and the second standard cell 300 is shown, and Figure 1A In other words, the device-level structure above the first n-type well 202n, the first p-type well 202p, the second n-type well 302n and the second p-type well 302p. Figure 1B The device-level structure shown is overlaid on Figure 1A The device-level structure in the first standard cell 200 includes a first n-type well 202n and a first p-type well 202p (see FIG. Figure 1A ), a first active region 202 formed above a channel region of the first active region 202, a first metal contact 206 (or source / drain contact) formed above a source / drain feature of the first active region 202, and a first metal via 208 formed above the first metal contact 206 and above the first metal gate 204. The device-level structure in the second standard cell 300 includes a second active region 302 formed above a second n-type well 302n and a second p-type well 302p (see Figure 1A ), a second metal gate 304 formed above the channel region of the second active region 302, a second metal contact 306 (or source / drain contact) formed above the source / drain component of the second active region 302, and a second metal through-hole 308 formed above the second metal contact 306 and above the second metal gate 304.

[0070] Still refer to Figure 1BThe first active region 202 and the second active region 302 extend longitudinally along the x-direction. Each first active region 202 and the second active region 302 are separated from the other first active regions 202 and the second active region 302 by an isolation structure (not shown). The isolation structure may be a shallow trench isolation (STI) structure comprising a dielectric material such as silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, combinations thereof, and / or other suitable materials. The isolation structure covers the top surface of the substrate and surrounds sidewall portions of the first active region 202 and the second active region 302. Described another way, the first active region 202 and the second active region 302 refer to semiconductor components exposed within the openings in the isolation structure. In this embodiment, the isolation structure active regions 202 and 302 protrude from the substrate above the top surface of the isolation structure. The substrate may include an n-type well or a p-type well as described above. The first active region 202 has a first width w1 along the y-direction, and the second active region 302 has a second width w2 along the y-direction, with the second width w2 being greater than the first width w1. Due to the enlarged second n-type well 302n and second p-type well 302p below the second active region 302, the second active region 302 can have a greater width than the first active region 202. In each first standard cell 200, there are two first active regions 202, one extending over the first n-type well 202n and the other extending over the first p-type well 202p. In the illustrated embodiment, the two first active regions 202 in each first standard cell 200 each have the same first width w1. In each second standard cell 300, there are two second active regions 302, one extending over the second n-type well 302n and the other extending over the second p-type well 302p. In the illustrated embodiment, the two second active regions 302 in each second standard cell 300 each have the same second width w2. The first active region 202 and the second active region 302 each include a channel region and source / drain regions adjacent to the channel region. The channel region is the portion of the first active region and the portion of the second active region located below the respective first metal gate 204 and second metal gate 304. The source / drain regions include epitaxial source / drain features connected to the transistor channel of the channel region. The source / drain features may be doped with n-type dopants and / or p-type dopants. In some embodiments, for n-type transistors, the epitaxial source / drain features comprise silicon and may be doped with carbon, phosphorus, arsenic, other n-type dopants, or combinations thereof (e.g., to form Si:C epitaxial source / drain features, Si:P epitaxial source / drain features, or Si:C:P epitaxial source / drain features). In some embodiments, for p-type transistors, the epitaxial source / drain features comprise silicon germanium or germanium and may be doped with boron, other p-type dopants, or combinations thereof (e.g., to form Si:Ge:B epitaxial source / drain features).

[0071] Still refer to Figure 1BThe first and second metal gates 204 and 304 extend longitudinally along the y-direction and overlie the channel regions of the first and second active regions 202 and 302 . The first and second metal gates 204 and 304 may extend over a plurality of channel regions of the first and second active regions 202 and 302 across a plurality of first and second standard cells 200 and 300 . Each metal gate may include an interfacial layer (e.g., a silicon oxide layer), a gate dielectric layer overlying the interfacial layer, and a gate electrode overlying the gate dielectric layer. The gate dielectric layer may include a high-k dielectric material, such as a material having a dielectric constant greater than that of silicon oxide (k≈3.9). The gate dielectric layer may include hafnium oxide (HfO), lanthanum oxide (LaO), zirconium oxide (ZrO), aluminum oxide (AlO), titanium oxide (TiO), or tantalum oxide (TaO). The gate electrode may include a suitable conductive material, such as aluminum (Al), tungsten (W), cobalt (Co), titanium aluminide (TiAl), titanium nitride (TiN), or other metal gate materials.

[0072] Still refer to Figure 1B The first metal contact 206 and the second metal contact 306 extend longitudinally along the y-direction and overlie the source / drain features of the first active region 202 and the second active region 302. The first metal contact 206 is disposed between the first metal gates 204 and has a width spanning along the x-direction between the first metal gates 204. The length spanning along the y-direction of the first metal contact 206 may be greater than the first width w1. The second metal contact 306 is disposed between the second metal gates 304 and has a width spanning along the x-direction between the second metal gates 304. The length spanning along the y-direction of the second metal contact 306 may be greater than the second width w2. Due to the larger second active region 302 and the larger spacing within the second standard cell 300, the second metal contact 306 may span a longer length than the first metal contact 206. In this embodiment, the second metal contact 306 may have a similar width in the x-direction as the first metal contact 206. The first metal contact 206 and the second metal contact 306 may include titanium (Ti), ruthenium (Ru), copper (Cu), nickel (Ni), cobalt (Co), tungsten (W), tantalum (Ta), or molybdenum (Mo). In one embodiment, silicide features are first formed over the source / drain features of the first active region 202 and the second active region 302, and then the first metal contact 206 and the second metal contact 306 are formed over the silicide features. The silicide features may include titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel platinum silicide (NiPtSi), nickel platinum germanium silicide (NiPtGeSi), nickel germanium silicide (NiGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi), or other suitable compounds.

[0073] Still refer to Figure 1B A plurality of first metal vias 208 and second metal vias 308 are disposed above the first metal gate 204 / second metal gate 304 or the first metal contact 206 / second metal contact 306 and are coupled to the first metal gate 204 / second metal gate 304 or the first metal contact 206 / second metal contact 306. These first metal vias 208 / second metal vias 308 allow the first metal gate 204 / second metal gate 304 or the first metal contact 206 / second metal contact 306 to be electrically coupled to a higher material layer (e.g., a metal line) in the z-direction. Some first metal vias 208 may electrically couple the first metal contact 206 to an upper power line, while other first metal vias 208 may electrically couple the first metal gate 204 to an upper signal line. Some second metal vias 308 may electrically couple the second metal contact 306 to an upper power line, while other second metal vias 308 may electrically couple the second metal gate 304 to an upper signal line. The first metal via 208 and the second metal via 308 may comprise any suitable conductive material, such as tungsten. The locations of the first metal via 208 and the second metal via 308 may be periodic between cells. These locations may be designed so that the same metal line (i.e. Figure 1C The metal lines 402a and 402b in FIG. 4 may directly land on both the first metal via 208 and the second metal via 308 for the same node connection (ie, power line or signal line).

[0074] Figure 1C A top view of the device layout 100 defined by the first standard cell 200 and the second standard cell 300 is shown, and Figure 1B In other words, Figure 1C The metal lines 402a and 402b are shown covering Figure 1B. Specifically, metal line 402a and metal line 402b extend longitudinally along the x-direction and land on the first metal via 208 and the second metal via 308 of the first standard cell 200 and the second standard cell 300. Metal line 402a may correspond to a power line electrically connected to the source / drain components of the first standard cell 200 and the second standard cell 300, and metal line 402b may correspond to a signal line electrically connected to the first metal gate 204 and the second metal gate 304 of the first standard cell 200 and the second standard cell 300. For example, a single metal line (e.g., metal line 402a) may be electrically connected to multiple source / drain components of the first active region 202 and the second active region 302. This single metal line has the same width, extending continuously along the x-direction above the first standard cell 200 and the second standard cell 300. In the same manner, another identical metal line (e.g., metal line 402b) can be electrically connected to the first metal gates 204 and the second metal gates 304 of the first active region 202 and the second active region 302. This another identical metal line has the same width extending continuously along the x-direction above the first standard cell 200 and the second standard cell 300. Figure 1C As shown, the same upper metal arrangement (i.e., metal line 402a and metal line 402b) can be used for both the first standard cell 200 and the second standard cell 300 to simplify process complexity and promote uniformity. That is, although the well type and device-level structure between the first standard cell 200 and the second standard cell 300 are different (to provide more device options), Figure 1C Starting from the first metal line level shown, the first standard cell 200 and the second standard cell 300 may have the same upper metal arrangement.

[0075] Figure 1D show Figures 1A-1C A cross-sectional view of a semiconductor structure in a device region 350 of the device layout 100 is shown. Figure 1B The device area 350 is shown as a dotted box around the second standard cell 300. Note that although the dotted box is only Figure 1B , but the device area 350 will also include Figure 1A and 1C The corresponding features shown in . Figure 1DTwo second standard cells 300 are shown, each adjacent to each other along the y-direction and having a second cell height y2. Within each second standard cell 300, one active region of the second active region 302 is formed above a p-type well for an n-type transistor, and the other active region of the second active region 302 is formed above an n-type well for a p-type transistor. Each active region in the second active region 302 has a second width w2. Device region 350 shows a second metal gate 304 formed above each second active region 302 in the two second standard cells 300. Through the second metal gate 304, each of the two second standard cells 300 forms a complementary metal oxide semiconductor (CMOS) device having an n-type transistor and a p-type transistor. As previously described and shown herein, within each second standard cell 300, there is a second metal contact 306 above the source / drain region of the second active region 302, a second metal via 308 above the second metal gate 304 or above the second metal contact 306, and a metal line 402a or 402b above the second metal via 308. In the embodiment shown, the top surface of the second metal contact 306 is located above the top surface of the second metal gate 304. Therefore, the second metal via 308 coupled between the metal line 402b and the second metal gate 304 can extend deeper than the second metal via 308 coupled between the metal line 402a and the second metal contact 306. Although not shown, the device area adjacent to the device area 350 and surrounding the first standard cell 200 will be shown to be the same as the device area 350. Figure 1D A similar cross-sectional view will show three first standard cells 200 adjacent to each other along the y-direction, each first standard cell 200 having a first cell height y1, and each active region in the first standard cell 200 having a first width w1 with corresponding gates, vias, and metal lines thereon.

[0076] Figures 2A-2D Display and Figures 1A-1D Unless otherwise specified, reference is made to another embodiment of the present disclosure. Figures 1A-1D The features described are applicable to Figures 2A-2D For the sake of brevity, these features will not be repeated. Figures 2A-2D The difference lies in that the first active region 202 may have different widths within the same first standard cell 200 , and the second active region 302 may have different widths within the same second standard cell 300 .

[0077] like Figure 2BAs shown, one first active region 202 in the first standard cell 200 may have a first width w1, and another first active region 202 in the first standard cell 200 may have a third width w3. For different design applications, the first width w1 and the third width w3 are different. In the embodiment shown, the first width w1 corresponds to the width w1 of the first active region 202 in the first standard cell 200. Figures 1A-1D The first width w1 described. Figures 1A-1D As shown, the first width w3 is smaller than the first width w1. In one embodiment, within the same first standard cell 200, one first active region 202 formed above the first p-type well 202p has the first width w1, and another first active region 202 formed above the first n-type well 202n has a third width w3. Alternatively, within the same first standard cell 200, one first active region 202 formed above the first p-type well 202p has the third width w3, and another first active region 202 formed above the first n-type well 202n has the first width w1.

[0078] Still refer to Figure 2B One second active region 302 in the second standard cell 300 may have a second width w2, and another second active region 302 in the second standard cell 300 may have a fourth width w4. The second width w2 and the fourth width w4 may vary for different design applications. In the illustrated embodiment, the second width w2 corresponds to the second width w2 described above with reference to FIGS. 1A-1D , and the fourth width w4 is less than the second width w2. In one embodiment, within the same second standard cell 300, one second active region 302 formed above the second p-type well 302p has the second width w2, and another second active region 302 formed above the second n-type well 302n has the fourth width w4. Alternatively, within the same second standard cell 300, one second active region 302 formed above the second p-type well 302p has the fourth width w4, and another second active region 302 formed above the second n-type well 302n has the second width w2. In other embodiments, each of the second width w2 and the fourth width w4 is greater than each of the first width w1 and the third width w3. For example, the second width w2 is greater than the fourth width w4, the fourth width w4 is greater than the first width w1, and the first width w1 is greater than the third width w3. In these embodiments, even the smaller fourth width w4 in the second standard cell 300 is greater than the larger first width w1 in the first standard cell 200. This can be achieved by increasing the cell height of the second standard cell 300 to a sufficient degree. In embodiments, this requires that the ratio of the second cell height y2 to the first cell height y1 be at least 1.5.

[0079] Figure 3A 、 3B, a top view of different layers in the 3C display device layout 100. Figure 3A 、 3B , 3C display and Figures 2A-2C Similar features will not be repeated for the sake of brevity. Figure 3A 、 3B , 3C, the device layout 100 is defined by a first standard cell 200 and a second standard cell 300, and has a dielectric gate 404 between the first standard cell 200 and the second standard cell 300. The dielectric gate 404 is oriented in the same manner as the first metal gate 204 / the second metal gate 304 (i.e., extends longitudinally in the y-direction), except that the dielectric gate 404 is not a gate and does not act as a gate. Instead, the dielectric gate 404 is a dielectric component that includes one or more dielectric materials and acts as an isolation component. The one or more dielectric materials may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric, combinations of the above, and / or other suitable materials. In some embodiments, the first metal gate 204 / the second metal gate 304 and the dielectric gate 404 are formed together by a process such as a gate-last process. For example, a dummy gate is first formed by deposition and patterning, wherein the patterning also includes a photolithography process and etching. Then, a gate dielectric layer and a gate electrode are deposited to replace a subset of the dummy gates to form the first metal gate 204 / the second metal gate 304. Meanwhile, only a dielectric material is deposited to replace the dummy gate between the first standard cell 200 and the second standard cell 300 to form the dielectric gate 404. Furthermore, the dielectric gate 404 has a different configuration and arrangement, and therefore has a different function.

[0080] In this embodiment, the dielectric gate 404 is placed on the transition boundary (or boundary) between the first standard cell 200 and the second standard cell 300 to play an isolation role and separate one standard cell from the adjacent standard cell. The transition boundary can be defined as the edge of the first n-type well 202n and the first p-type well 202p in the first standard cell 200 before they transition to different well sizes (i.e., the well size of the second standard cell 300). Alternatively, the transition boundary can be defined as the edge of the second n-type well 302n and the second p-type well 302p in the second standard cell 300 before they transition to different well sizes (i.e., the well size of the first standard cell 200). Figure 3A 、 3B In the embodiment shown in FIG. 3C , a single dielectric gate 404 is placed at a shared transition boundary at both edges of the first standard cell 200 and the second standard cell 300 .

[0081] Figure 4A 、 4B 4C shows a top view of different layers in the device layout 100 according to another embodiment of the present disclosure. Figure 4A、 4B , 4C display and Figure 3A 、 3B , 3C similar features, for the sake of brevity, similar features will not be repeated. The difference is Figure 4A 、 4B The device layout 100 of FIG4C includes a transition well 500 located between the first standard cell 200 and the second standard cell 300 along the x-direction. The transition well 500 is a region where the well size gradually transitions from one setting to another setting (e.g., from the well setting in the first standard cell 200 to the well setting in the second standard cell 300). Thus, the first standard cell 200 and the second standard cell 300 are not directly adjacent to each other and do not share a common well. Figure 3A 、 3B , 3C . Instead, there are two transition boundaries, one at the edge of the first n-type well 202n and the first p-type well 202p in the first standard cell 200 and at a first edge of the transition well 500, and another at the edge of the second n-type well 302n and the second p-type well 302p in the second standard cell 300 and at a second edge of the transition well 500. At these transition boundaries, the well configuration begins to change from one well configuration to another.

[0082] Still refer to Figure 4A 、 4B , 4C, the dielectric gate 404 is placed on each transition boundary (i.e., each edge of the transition well 500). Figure 4A 、 4B The device layout 100 in FIG4C has at least two dielectric gates 404 between the first standard cell 200 and the second standard cell 300. In further embodiments, depending on the gate spacing design, additional dielectric gates 404 may be present within the transition well and between the two transition boundaries. Having a transition well 500 and at least two dielectric gates 404 allows for further isolation between the integrated circuit devices between the first standard cell 200 and the second standard cell 300, which is desirable because they operate at different well settings and active area sizes. Providing additional dielectric gates 404 in the transition well also provides pattern density adjustment for improved processes such as etching, deposition, and chemical mechanical polishing (CMP).

[0083] Figure 5A A top view of the display device layout block 1000 is shown, showing the n-type well and p-type well above the substrate. Figure 5B A top view of the display device layout block 1000 is shown. Figure 5AThe device level structure above the n-type well and the p-type well. The device layout block 1000 is defined by a plurality of first standard cells 200, a plurality of second standard cells 300, and a plurality of transition wells 500 laterally located between the first standard cells 200 and the second standard cells 300. Figure 5A As shown, a first standard cell 200 having a first n-type well 202n and a p-type well 202p encloses and surrounds a second standard cell 300 having an n-type well 302n and a p-type well 302p. In the x-direction, due to the change in well configuration, one or more transition wells 500 may exist between the first standard cell 200 and the second standard cell 300. However, in the y-direction, the first standard cell 200 and the second standard cell 300 can directly abut each other, achieving seamless integration without any transition region. This is due to the periodic alignment of the first standard cell 200 and the second standard cell 300 in the y-direction.

[0084] Still refer to Figure 5A and Figure 5B , the rows of first standard cells 200 sandwich the hybrid region 150 along the y-direction. The hybrid region 150 includes both the first standard cell 200 and the second standard cell 300 and the transition well 500 therebetween. In other embodiments, the rows of second standard cells 300 or other types of standard cells may alternatively sandwich the hybrid region 150. In any case, the hybrid region 150 can be placed and incorporated into a larger device layout block 1000 without affecting the standard cell scheme of the larger device layout block 1000. Now referring to Figure 5B Because some metal gates extend across different first and second standard cells 200 and 300 in the y-direction, the first metal gate 204 and the second metal gate 304 can share the same gate structure. However, note that at the transition boundary of the transition well 500, the dielectric gate 404 separates the gate structures in the y-direction. Also note that due to the transition well 500, the first active region 202 can have different lengths in the x-direction, and the second active region 302 can have different lengths in the x-direction.

[0085] Figure 5C-1 A top view of the display device layout block 1000 is shown. Figure 5B Metal line 402a and metal line 402b are disposed above the device-level structure. Figure 5C-1 and Figure 1C Similar to and about Figure 1C The same applies to Figure 5C-1As shown, metal lines 402a and 402b have the same width and length extending along the x-direction above the first standard cell 200 and the second standard cell 300. This can be achieved by adjusting the positions of the first metal via 208 and the second metal via 308 on which the metal lines 402a and 402b will land. Using the same upper metal placement settings (i.e., metal lines 402a and 402b) simplifies process complexity and promotes uniformity. That is, although the well type and device-level structure between the first standard cell 200 and the second standard cell 300 are different (to provide more device options), the upper metal arrangement between the first standard cell 200 and the second standard cell 300 can be the same.

[0086] Figure 5C-2 A top view of a device layout block 1000 showing metal lines 402a and 402b according to another embodiment of the present disclosure is shown. These metal lines 402a and 402b are arranged in Figure 5B above the device-level structure. Figure 5C-2 and Figure 5C-1 The difference lies in varying the metal line settings of metal lines 402a and 402b to accommodate different standard cell types. As shown, for better contact resistance and device performance, metal lines 402a and / or 402b may be widened in the y-direction in the region above the second standard cell 300 to contact the larger device structure below. In other words, metal lines 402a and 402b may have a first metal width in the y-direction when extending above the first standard cell 200, and a second metal width in the y-direction when extending above the second standard cell 300, with the second metal width being greater than the first metal width. This difference in width may result in misalignment in the x-direction between metal lines 402a and 402b in the first and second standard cells 200 and 300. As a result, some metal lines 402a and 402b above the first standard cell 200 may be separated from some metal lines 402a and 402b above the second standard cell 300 by gaps in one or more transition wells 500. Figure 5C-1 and 5C-2 This allows the standard cell solution to have the flexibility to keep the same metal line settings across different standard cells or to use different metal line settings across different standard cells.

[0087] Although not limiting, the present disclosure provides advantages in standard cell layouts. One example advantage is the formation of multiple standard cells with wells of different sizes adjacent to each other. The wells of different sizes can accommodate device active areas of different sizes on the standard cell block. Another example advantage is the periodic alignment of different standard cells to facilitate integration with a larger standard cell device layout. Another example advantage is the incorporation of one or more dielectric gates between standard cells of different cell heights for proper isolation between device active areas. These dielectric gates can be set above the transition boundaries of different standard cells or above the transition boundary of a transition well. Another example advantage is allowing the same upper metal line setting across different standard cells to simplify the process, or allowing customized upper metal line setting across different standard cells to improve the device.

[0088] One aspect of the present disclosure relates to a semiconductor structure. The semiconductor structure includes a plurality of first standard cells having a plurality of first active regions formed above a plurality of alternating first n-type wells and first p-type wells, the first active regions and the alternating first n-type wells and first p-type wells each extending longitudinally along a first direction, and each first standard cell including a first n-type well and a first p-type well. The semiconductor structure also includes a plurality of second standard cells adjacent to the first standard cells along the first direction, the second standard cells having a plurality of second active regions formed above a plurality of alternating second n-type wells and second p-type wells, the second active regions and the alternating second n-type wells and second p-type wells each extending longitudinally along the first direction, and each second standard cell including a second n-type well and a second p-type well. The first standard cells have a first cell height along a second direction perpendicular to the first direction, and the second standard cells have a second cell height along the second direction, the second cell height being greater than the first cell height. The second active region has a greater width along the second direction than the first active region.

[0089] In an embodiment, the ratio of the second cell height to the first cell height is about 1.5.

[0090] In one embodiment, the edge boundaries of the first standard cell are periodically aligned with the edge boundaries of the second standard cell along the first direction. In another embodiment, the edge boundaries of the first standard cell are periodically aligned with the edge boundaries of the second standard cell after every three first standard cell heights and every two second standard cell heights.

[0091] In one embodiment, the semiconductor structure further includes a plurality of metal gates located above the first active region and the second active region, the metal gates extending longitudinally along the second direction, and a plurality of first source / drain (S / D) contacts and a plurality of second source / drain (S / D) contacts located above the first active region and the second active region, respectively, with each metal gate interposed between the first source / drain contact and the second source / drain contact along the first direction. The first source / drain contact has a first length along the second direction, and the second source / drain contact has a second length along the second direction, wherein the second length is greater than the first length.

[0092] In a further embodiment, the semiconductor structure further includes a plurality of metal vias located above the metal gate and above the first source / drain contact and above the second source / drain contact; and a plurality of metal lines extending longitudinally along the first direction above the metal vias, wherein the metal lines have the same width along the second direction when extending above the first standard cell and the second standard cell.

[0093] In a further embodiment, the semiconductor structure further includes a plurality of metal vias located above the metal gate, above the first source / drain contact, and above the second source / drain contact; and a plurality of metal lines extending longitudinally in a first direction above the metal vias. The metal lines have a first metal width along a second direction when extending above the first standard cell and a second metal width along the second direction when extending above the second standard cell, and the second metal width is greater than the first metal width.

[0094] In one embodiment, each first active region has a first width along the second direction, each second active region has a second width along the second direction, and the second width is greater than the first width.

[0095] In one embodiment, the first active region in each first standard cell includes an active region above the n-type well and having a first width along the second direction, and another active region above the p-type well and having a third width along the second direction, wherein the first width is different from the third width. The second active region in each second standard cell includes an active region above the n-type well and having a second width along the second direction, and another active region above the p-type well and having a fourth width along the second direction, wherein the second width is different from the fourth width. In another embodiment, each of the second width and the fourth width is greater than each of the first width and the third width.

[0096] Another aspect of the present disclosure relates to a semiconductor structure. The semiconductor structure includes a plurality of first standard cells having a plurality of first active regions formed over a plurality of alternating first n-type wells and first p-type wells, the first active regions and the alternating first n-type wells and first p-type wells each extending longitudinally along a first direction. The semiconductor structure includes a plurality of second standard cells adjacent to the first standard cells along the first direction, the second standard cells having a plurality of second active regions formed over a plurality of alternating second n-type wells and second p-type wells, the second active regions and the alternating second n-type wells and second p-type wells each extending longitudinally along the first direction. The semiconductor structure includes a plurality of metal gates over the first and second active regions in the first and second standard cells, the metal gates extending longitudinally along a second direction perpendicular to the first direction. The semiconductor structure includes a dielectric gate located between the first and second standard cells and at a transition boundary between the alternating first n-type wells and first p-type wells and the alternating second n-type wells and second p-type wells, the dielectric gate extending longitudinally along the second direction. The first n-type well and the first p-type well have a first width along the second direction, and the second n-type well and the second p-type well have a second width along the second direction, the second width being greater than the first width.

[0097] In one embodiment, the second active region has a greater width along the second direction than the first active region.

[0098] In one embodiment, the dielectric gate is a first dielectric gate, and the semiconductor structure further includes a transition well located between the first standard cell and the second standard cell along a first direction; and a second dielectric gate. The transition well transitions a first width of the first n-type well and the first p-type well to a second width of the second n-type well and the second p-type well. The first dielectric gate extends along a first edge of the transition well in a second direction, and the second dielectric gate extends along a second edge of the transition well in the second direction.

[0099] In a further embodiment, the semiconductor structure further includes one or more dielectric gates in the transition well and between the first dielectric gate and the second dielectric gate. In another embodiment, the semiconductor structure further includes a plurality of metal lines extending longitudinally in a first direction above the first standard cell and the second standard cell. The metal lines above the first standard cell are separated from the metal lines above the second standard cell by a gap in the transition well.

[0100] In one embodiment, the semiconductor structure further includes a plurality of third standard cells having a plurality of third active regions formed above a plurality of alternating third n-type wells and third p-type wells, the third active regions and the alternating third n-type wells and third p-type wells each extending longitudinally along a first direction. The third n-type wells and the third p-type wells each have a first width along a second direction. The first standard cell and the third standard cell are directly adjacent to each other along the second direction, and the second standard cell and the third standard cell are directly adjacent to each other along the second direction.

[0101] Another aspect of the present disclosure relates to a semiconductor structure. The semiconductor structure includes a first standard cell having a first n-type well and a first p-type well extending longitudinally along a first direction. The semiconductor structure includes a second standard cell adjacent to the first standard cell along the first direction, the second standard cell having a second n-type well and a second p-type well extending longitudinally along the first direction. The semiconductor structure includes a dielectric gate at a boundary between the first standard cell and the second standard cell, the dielectric gate extending longitudinally along a second direction perpendicular to the first direction. The first standard cell has a first cell height along a second direction, and the second standard cell has a second cell height along the second direction, wherein the second cell height is greater than the first cell height.

[0102] In one embodiment, the first n-type well and the first p-type well have the same first width along the second direction, and the second n-type well and the second p-type well have the same second width along the second direction, the second width being greater than the first width. In a further embodiment, the semiconductor structure further includes a first active region extending longitudinally in the first direction above the first n-type well; a second active region extending longitudinally in the first direction above the first p-type well; a third active region extending longitudinally in the first direction above the second n-type well; and a fourth active region extending longitudinally in the second direction above the second p-type well. The third active region and the fourth active region have a greater width along the second direction than the first and second active regions. In a further embodiment, the first active region has a different width along the second direction than the second active region. The third active region has a different width along the second direction than the fourth active region.

[0103] The features of several embodiments are summarized above so that those with ordinary knowledge in the art can better understand the viewpoints of the embodiments of the present disclosure. Those with ordinary knowledge in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the present disclosure to achieve the same purposes and / or advantages as the embodiments introduced herein. Those with ordinary knowledge in the art should also understand that such equivalent structures do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and replacements can be made without violating the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure, characterized in that The semiconductor structure includes: a plurality of first standard cells having a plurality of first active regions formed above a plurality of alternating first n-type wells and first p-type wells, the plurality of first active regions and the plurality of alternating first n-type wells and first p-type wells each extending longitudinally along a first direction, each of the first standard cells including the first n-type well and the first p-type well; and a plurality of second standard cells adjacent to the plurality of first standard cells along the first direction, the plurality of second standard cells having a plurality of second active regions formed above a plurality of alternating second n-type wells and second p-type wells, the plurality of second active regions and the plurality of alternating second n-type wells and second p-type wells each extending longitudinally along the first direction, each of the second standard cells including the second n-type well and the second p-type well; wherein the plurality of first standard cells have a first cell height along a second direction perpendicular to the first direction, the plurality of second standard cells have a second cell height along the second direction, and the second cell height is greater than the first cell height, The second active regions have a width greater than that of the first active regions along the second direction.

2. The semiconductor structure according to claim 1, wherein Also includes: a plurality of metal gates located above the plurality of first active regions and the plurality of second active regions, the plurality of metal gates extending longitudinally along the second direction; as well as A plurality of first source / drain contacts and a plurality of second source / drain contacts are respectively located above the plurality of first active regions and the plurality of second active regions, and each of the metal gates is inserted between the plurality of first source / drain contacts and the plurality of second source / drain contacts along the first direction. The first source / drain contacts have a first length along the second direction, the second source / drain contacts have a second length along the second direction, and the second length is greater than the first length.

3. The semiconductor structure according to claim 2, wherein: Also includes: a plurality of metal vias located above the plurality of metal gates and above the plurality of first source / drain contacts and the plurality of second source / drain contacts; as well as A plurality of metal lines extend longitudinally along the first direction over the plurality of metal vias, wherein the plurality of metal lines have the same width along the second direction when extending over the plurality of first standard cells and the plurality of second standard cells.

4. The semiconductor structure according to claim 2, wherein: Also includes: a plurality of metal vias located above the plurality of metal gates and above the plurality of first source / drain contacts and the plurality of second source / drain contacts; as well as A plurality of metal lines extend longitudinally along the first direction above the plurality of metal vias, wherein when the plurality of metal lines extend above the plurality of first standard cells, the plurality of metal lines have a first metal width along the second direction, and when the plurality of metal lines extend above the plurality of metal line second standard cells, the plurality of metal lines have a second metal width along the second direction, and the second metal width is greater than the first metal width.

5. A semiconductor structure, characterized in that The semiconductor structure includes: a plurality of first standard cells having a plurality of first active regions formed above a plurality of alternating first n-type wells and first p-type wells, the plurality of first active regions and the plurality of alternating first n-type wells and first p-type wells each extending longitudinally along a first direction; a plurality of second standard cells adjacent to the plurality of first standard cells along the first direction, the plurality of second standard cells having a plurality of second active regions formed above a plurality of alternating second n-type wells and second p-type wells, the plurality of second active regions and the plurality of alternating second n-type wells and second p-type wells each extending longitudinally along the first direction; a plurality of metal gates located above the plurality of first active regions and the plurality of second active regions in the plurality of first standard cells and the plurality of second standard cells, the plurality of metal gates longitudinally extending along a second direction perpendicular to the first direction; and a dielectric gate located between the plurality of first standard cells and the plurality of second standard cells and at a transition boundary between the plurality of alternating first n-type wells and first p-type wells and the plurality of alternating second n-type wells and second p-type wells, the dielectric gate extending longitudinally along the second direction; The first n-type wells and the first p-type wells have a first width along the second direction, the second n-type wells and the second p-type wells have a second width along the second direction, and the second width is greater than the first width.

6. The semiconductor structure according to claim 5, wherein: Wherein the dielectric gate is a first dielectric gate, the semiconductor structure further comprises: a transition well located between the plurality of first standard cells and the plurality of second standard cells along the first direction; and a second dielectric gate, wherein the transition well transitions the first widths of the plurality of first n-type wells and the plurality of first p-type wells to the second widths of the plurality of second n-type wells and the plurality of second p-type wells, The first dielectric gate extends along the second direction along a first edge of the transition well, and the second dielectric gate extends along the second direction along a second edge of the transition well.

7. The semiconductor structure according to claim 6, wherein: Also includes: A plurality of metal lines extend longitudinally along the first direction above the plurality of first standard cells and the plurality of second standard cells, wherein the plurality of metal lines above the plurality of first standard cells and the plurality of metal lines above the plurality of second standard cells are separated by a gap in the transition well.

8. The semiconductor structure according to claim 5 or 6, wherein: Also includes: a plurality of third standard cells having a plurality of third active regions formed above a plurality of alternating third n-type wells and third p-type wells, the plurality of third active regions and the plurality of alternating third n-type wells and third p-type wells each extending longitudinally along the first direction; wherein the plurality of third n-type wells and the plurality of third p-type wells have the first width along the second direction, The plurality of first standard cells and the plurality of third standard cells are directly adjacent to each other along the second direction, and the plurality of second standard cells and the plurality of third standard cells are directly adjacent to each other along the second direction.

9. A semiconductor structure, characterized in that The semiconductor structure includes: A first standard cell having a first n-type well and a first p-type well extending longitudinally along a first direction; a second standard cell adjacent to the first standard cell along the first direction, the second standard cell having a second n-type well and a second p-type well longitudinally extending along the first direction; and a dielectric gate located at a boundary between the first standard cell and the second standard cell, the dielectric gate extending longitudinally along a second direction perpendicular to the first direction; The first standard cell has a first cell height along the second direction, the second standard cell has a second cell height along the second direction, and the second cell height is greater than the first cell height.

10. The semiconductor structure according to claim 9, wherein Also includes: a first active region extending longitudinally along the first direction above the first n-type well; a second active region extending longitudinally along the first direction above the first p-type well; a third active region extending longitudinally along the first direction above the second n-type well; as well as a fourth active region extending longitudinally along the second direction above the second p-type well; The third active region and the fourth active region have a greater width along the second direction than the first active region and the second active region.

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