Semiconductor package

Abstract

The embodiment of the utility model provides a semiconductor package. A semiconductor package may include a substrate, an IC package assembly bonded to the substrate, where the IC package assembly may include a semiconductor die, and a ring structure on the substrate, where the ring structure may surround the IC package assembly in a top view. The ring structure may include: a first attachment segment attached to the substrate by an adhesive, wherein the first attachment segment may be spaced apart from the package assembly by a first distance; a second attachment segment attached to the substrate by the adhesive, wherein the second attachment segment may be spaced apart from the package assembly by a second distance; and a first suspension section positioned between the first attachment section and the second attachment section. The first suspension segment may be suspended over the substrate. The first suspension segment may be spaced apart from the encapsulation assembly by a third distance that is different than the first distance and the second distance.

Description

Technical Field

[0001] An embodiment of the utility model relates to a semiconductor package. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the continuous improvement in the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.). In most cases, this increase in integration density is due to the iterative reduction of minimum feature size, which allows more components to be integrated into a given area. As the demand for smaller electronic devices continues to grow, the need for smaller and more innovative semiconductor die packaging technologies has also emerged. Utility Model Content

[0003] In one embodiment, a semiconductor package includes: a substrate; an integrated circuit package component bonded to the substrate, wherein the integrated circuit package component includes a semiconductor die; and an annular structure located on the substrate, wherein in a top view, the annular structure surrounds the integrated circuit package component, and wherein the annular structure includes: a first attachment segment attached to the substrate by an adhesive, wherein the first attachment segment is spaced apart from the package component by a first distance; a second attachment segment attached to the substrate by an adhesive, wherein the second attachment segment is spaced apart from the package component by a second distance; a first hanging segment located between the first attachment segment and the second attachment segment, wherein the first hanging segment is suspended above the substrate, wherein the first hanging segment is spaced apart from the package component by a third distance, wherein the third distance is different from the first distance and the second distance.

[0004] In one embodiment, a semiconductor package includes: a substrate including a first edge and a second edge, wherein the first edge intersects the second edge; an integrated circuit package component bonded to the substrate, wherein the package component includes a semiconductor die; an underfill between the integrated circuit package component and the substrate; and a stiffener ring on the substrate, wherein the stiffener ring surrounds the integrated circuit package component in a top view, and wherein a first portion of the stiffener ring extends along the first edge of the substrate, the first portion including: a first attachment segment having a first width, wherein a bottom surface of the first attachment segment is covered by an adhesive; a second attachment segment having a second width, wherein a bottom surface of the second attachment segment is covered by the adhesive; and a first hanging segment extending from the first attachment segment to the second attachment segment, the first hanging segment having a third width, wherein the third width is less than the first width and the second width, and wherein a bottom surface of the first hanging segment is free of adhesive. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Various aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0006] Figure 1 A cross-sectional view of an integrated circuit die.

[0007] Figures 2A to 2B A cross-sectional view of the grain stack.

[0008] Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 、 Figure 8 、 Figure 9 、 Figure 10A 、 Figure 10B 、 Figure 11 、 Figure 12 、 Figure 13 、 Figure 14A 、 Figure 14B 、 Figure 15A 、 Figure 15B 、 Figure 15C 、 Figure 15D 、 Figure 16A 、 Figure 16B 、 Figure 17A 、 Figure 17B 、 Figure 18A 、 Figure 18B 、 Figure 19A 、 Figure 19B 、 Figure 20A 、 Figure 20B and Figure 20C is a diagram of an intermediate stage in the fabrication of an integrated circuit package including a stiffener ring according to some embodiments. DETAILED DESCRIPTION

[0009] The following disclosure provides many different embodiments or examples for implementing the different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature on or above a second feature in the description below may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present invention may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself dictate the relationship between the various embodiments and / or configurations discussed.

[0010] Additionally, for ease of description, spatially relative terms such as "below," "lower," "above," and "upper" may be used herein to describe the relationship of one component or feature to another component or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0011] According to various embodiments, an integrated circuit package includes an integrated circuit package component and a stiffener ring on a package substrate. In a top view, the stiffener ring may surround the integrated circuit package component. The stiffener ring may include an attachment segment and a suspension segment. The attachment segment may be attached to the package substrate by an adhesive. The suspension segment may be suspended above the package substrate, wherein the bottom surface of the suspension segment is free of adhesive. By using such a stiffener ring, the integrated circuit package component and the package substrate may have greater freedom of movement when heated during operation, which may prevent or reduce delamination and / or cracking of the underfill in the integrated circuit package component and / or delamination and / or cracking of the underfill between the integrated circuit package component and the package substrate. As a result, the long-term reliability of the integrated circuit package including the stiffener ring may be improved.

[0012] Figure 11 is a cross-sectional view of an integrated circuit die 50. Multiple integrated circuit dies 50 may be packaged in subsequent processing to form an integrated circuit package. Each integrated circuit die 50 may be a logic die (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a system-on-a-chip (SoC) die, a microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, an interface die, a sensor die, a micro-electro-mechanical-system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front-end (AFE) die), etc., or a combination thereof. The integrated circuit die 50 may be formed in a wafer, which may include different die regions that are subsequently separated to form multiple integrated circuit dies 50. The integrated circuit die 50 includes a semiconductor substrate 52, an interconnect structure 54, die connectors 56, and a dielectric layer 58.

[0013] The semiconductor substrate 52 may be a substrate of doped or undoped silicon, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 52 may include other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used. The semiconductor substrate 52 has an active surface (e.g., Figure 1 upward facing surface) and non-active surfaces (e.g. Figure 1 The devices are located on the active surface of the semiconductor substrate 52. The devices may be active devices (e.g., transistors, diodes, etc.), capacitors, resistors, etc. The inactive surface may be free of devices.

[0014] Interconnect structure 54 is located above the active surface of semiconductor substrate 52. Interconnect structure 54 electrically interconnects multiple devices on semiconductor substrate 52 to form an integrated circuit and provides connections to die connectors 56. Interconnect structure 54 may include one or more dielectric layers and corresponding metallization layers within the dielectric layers. Acceptable dielectric materials for the dielectric layers include oxides, such as silicon oxide or aluminum oxide; nitrides, such as silicon nitride; carbides, such as silicon carbide; similar materials; or combinations thereof, such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon carbon oxynitride, and the like. Other dielectric materials may also be used, such as polymers, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB)-based polymers, and the like. The metallization layers may include vias and / or conductive lines for interconnecting multiple devices on semiconductor substrate 52. The metallization layers may be formed from conductive materials, such as metals, such as copper, cobalt, aluminum, gold, combinations thereof, and the like. The metallization layer or the interconnect structure 54 may be formed by a damascene process, such as a single damascene process, a dual damascene process, or the like.

[0015] Die connector 56 is located on front side 50F of integrated circuit die 50. Die connector 56 may be a conductive stud, pad, or the like for external connection. Die connector 56 is located within and / or above interconnect structure 54. For example, die connector 56 may be part of an upper metallization layer of interconnect structure 54. Die connector 56 may be formed of a metal such as copper or aluminum and may be formed, for example, by electroplating.

[0016] Optionally, during the formation of the integrated circuit die 50, a solder region (not separately shown) may be provided on the die connector 56. The solder region may be used to perform a chip probe (CP) test on the integrated circuit die 50. For example, the solder region may be a solder ball, solder bump, etc., which is used to attach a chip probe to the die connector 56. A chip probe test may be performed on the integrated circuit die 50 to determine whether the integrated circuit die 50 is a known good die (KGD). Therefore, only integrated circuit die 50 that has undergone subsequent processing (i.e., KGD) are packaged, and dies that fail the chip probe test are not packaged. After testing, the solder region may be removed.

[0017] A dielectric layer 58 is located at the front side 50F of the integrated circuit die 50. The dielectric layer 58 is located within and / or above the interconnect structure 54. For example, the dielectric layer 58 may be an upper dielectric layer of the interconnect structure 54. The dielectric layer 58 laterally encapsulates the die connector 56. The dielectric layer 58 may be an oxide, a nitride, a carbide, or the like, or a combination thereof. The dielectric layer 58 may be formed, for example, by chemical vapor deposition (CVD). Initially, the dielectric layer 58 may bury the die connector 56, such that the top surface of the dielectric layer 58 is located above the top surface of the die connector 56. The die connector 56 may be exposed by the dielectric layer 58. Any solder areas that may be present on the die connector 56 may be removed to expose the die connector 56. A removal process may be applied to each layer to remove excess material from the die connector 56. The removal process may be a planarization process, such as chemical mechanical polishing (CMP), etch back, or a combination thereof. After the planarization process, the top surfaces of the die connector 56 and the dielectric layer 58 are coplanar (within process variations) and exposed at the front side 50F of the integrated circuit die 50 .

[0018] Figures 2A to 2B Figures 60A and 60B are cross-sectional views of die stacks 60A and 60B, respectively. Die stacks 60A and 60B can each have a single function (e.g., a logic device, a memory die, etc.), or can have multiple functions. In some embodiments, die stack 60A is a logic device such as a system-on-integrated-chip (SoIC) device, and die stack 60B is a memory device such as a high-bandwidth memory (HBM) device.

[0019] like Figure 2AAs shown, die stack 60A includes two bonded integrated circuit dies 50 (e.g., a first integrated circuit die 50A and a second integrated circuit die 50B). In some embodiments, first integrated circuit die 50A is a logic die, and second integrated circuit die 50B is an interface die. The interface die bridges the logic die to an external memory die and converts instructions between the logic die and the external memory die. In some embodiments, first integrated circuit die 50A and second integrated circuit die 50B are bonded so that their active surfaces face each other (e.g., a "face-to-face" bond). Vias 62 can be formed through one of the integrated circuit dies 50 to enable external connections to die stack 60A. Vias 62 can be through-substrate vias (TSVs), such as through-silicon vias. In the illustrated embodiment, vias 62 are formed in second integrated circuit die 50B (e.g., the interface die). The vias 62 extend through the semiconductor substrate 52 of the corresponding integrated circuit die 50 to physically and electrically connect to the metallization layer of the interconnect structure 54 .

[0020] like Figure 2B As shown, die stack 60B is a stacked device comprising multiple semiconductor substrates 52. For example, die stack 60B may be a memory device comprising multiple memory dies, such as a hybrid memory cube (HMC) device or a high bandwidth memory (HBM) device. Each semiconductor substrate 52 may or may not have a separate interconnect structure 54. The semiconductor substrates 52 are connected vias 62 (e.g., TSVs).

[0021] Figures 3 to 15C FIG2 is a diagram illustrating an intermediate stage in the fabrication of an integrated circuit package 300A according to some embodiments. Multiple packaging regions 100P are shown, and an integrated circuit package assembly 200 may be formed in each packaging region 100P, which may be used to form the integrated circuit package body 300A. Figures 3 to 15C The integrated circuit package 300A is shown as a chip-on-wafer-on-substrate (CoWoS) package, such as a CoWoS-L package as an example, and it is understood that other types of packages may be used.

[0022] exist Figure 3 In the embodiment, a carrier substrate 102 is provided, and a release layer 104 is formed on the carrier substrate 102. The carrier substrate 102 may be a glass carrier substrate, a ceramic carrier substrate, etc. The carrier substrate 102 may be a wafer, so that multiple packages can be formed on the carrier substrate 102 at the same time.

[0023] The release layer 104 can be formed of a polymer-based material that can be removed from the upper structure to be formed in subsequent steps along with the carrier substrate 102. In some embodiments, the release layer 104 is an epoxy-based thermal release material that loses its adhesive properties when heated, such as a light-to-heat-conversion (LTHC) release coating. In other embodiments, the release layer 104 can be an ultraviolet (UV) glue that loses its adhesive properties when exposed to UV light. The release layer 104 can be dispensed and cured as a liquid, can be a laminated film laminated to the carrier substrate 102, or can be the like. The top surface of the release layer 104 can be horizontal and can have a high degree of flatness.

[0024] exist Figure 4 In the embodiment, through hole 106 is formed above carrier substrate 102 (for example, on release layer 104). As an example of forming through hole 106, a seed layer (not shown) is formed above release layer 104. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including multiple sublayers formed of different materials. In one embodiment, the seed layer includes a titanium layer and a copper layer above the titanium layer. The seed layer can be formed using, for example, physical vapor deposition (PVD). A photoresist is formed on the seed layer and patterned. The photoresist can be formed by spin coating, etc., and can be exposed to patterning. The pattern of the photoresist corresponds to the through hole 106. The above patterning forms an opening through the photoresist to expose the seed layer. A conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating, such as electroplating or chemical plating. The conductive material can include metals such as copper, titanium, tungsten, aluminum, etc. The photoresist and the portion of the seed layer on which the conductive material is not formed are removed. The photoresist can be removed by an acceptable ashing or stripping process (e.g., using oxygen plasma, etc.). Once the photoresist is removed, the exposed portion of the seed layer is removed, for example, by an acceptable etching process, such as by wet or dry etching. The remaining portion of the seed layer and the conductive material form the through hole 106.

[0025] The interconnect die 120 is attached to the carrier substrate 102. Each interconnect die 120 can be a local silicon interconnect (LSI), a large-scale integrated package, an interposer die, etc. In the illustrated embodiment, one interconnect die 120 is attached to each package area 100P. It should be understood that any number of interconnect die 120 can be placed in the package area 100P. The interconnect die 120 can be placed using, for example, a pick-and-place process. Each interconnect die 120 includes a substrate 122, wherein conductive features are formed in and / or above the substrate 122. The substrate 122 can include a semiconductor substrate, one or more dielectric layers, etc. In addition, each interconnect die 120 can include a through-substrate via (TSV) 124 extending into or through the substrate 122 and can be coupled to the conductive features of the interconnect die 120. In the illustrated embodiment, the TSV 124 is exposed on the back side of the interconnect die 120. In another embodiment, the substrate 122 may cover the TSVs 124 at the backside of the interconnect die 120 .

[0026] In an embodiment where the interconnect die 120 is an LSI, the interconnect die 120 may be a bridging structure including die bridges 126. The die bridges 126 may be a metallization layer formed in and / or on, for example, the substrate 122, and are used to interconnect multiple integrated circuit devices (described later) to each other. Thus, the LSI can be used to directly connect multiple integrated circuit devices and allow communication between them. In such an embodiment, the interconnect die 120 may be placed in an area set between multiple integrated circuit devices that are subsequently joined, so that each of the interconnect die 120 overlaps the integrated circuit device above. In some embodiments, the interconnect die 120 may also include a logic device and / or a memory device. The interconnect die 120 is connected to the carrier substrate 102 so that the die bridges 126 face the carrier substrate 102.

[0027] exist Figure 5 In the embodiment of the present invention, an encapsulant 130 is formed on and around each component. After formation, the encapsulant 130 encapsulates the plurality of through-vias 106 and the plurality of interconnect die 120. The encapsulant 130 may be a molding compound, an epoxy resin, or the like. The encapsulant 130 may be applied by compression molding, transfer molding, or the like, and may be formed over the carrier substrate 102 such that the through-vias 106 and / or the interconnect die 120 are buried or covered. The encapsulant 130 is also formed in the interstitial region between the interconnect die 120 and the through-vias 106. The encapsulant 130 may be applied in a liquid or semi-liquid form and then cured.

[0028] Optionally, a planarization process is performed on encapsulation 130 to expose vias 106 and TSVs 124. The planarization process may also remove material from vias 106, substrate 122, and / or TSVs 124 until TSVs 124 and vias 106 are exposed. After the planarization process, the top surfaces of vias 106, substrate 122, TSVs 124, and encapsulation 130 are substantially coplanar (within process variations). The planarization process may be, for example, a CMP process, a grinding process, or the like. In some embodiments, for example, if vias 106 and / or TSVs 124 are already exposed, planarization may be omitted.

[0029] exist Figure 6 In the embodiment of the present invention, a front-side redistribution structure 140 is formed on the top surface of the encapsulation 130, the vias 106, and the interconnect die 120 (e.g., substrate 122). The front-side redistribution structure 140 includes a dielectric layer 142 and a metallization layer 144 (sometimes referred to as a redistribution layer or redistribution) in the dielectric layer 142. Therefore, the front-side redistribution structure 140 includes a plurality of metallization layers 144 separated from each other by corresponding dielectric layers 142. The metallization layers 144 of the front-side redistribution structure 140 are connected to the vias 106 and the interconnect die 120 (e.g., TSVs 124).

[0030] In some embodiments, dielectric layer 142 is formed from a polymer, which may be a photosensitive material such as PBO, polyimide, a BCB-based polymer, or the like, which can be patterned using a photolithographic mask. In other embodiments, dielectric layer 142 is formed from a nitride, such as silicon nitride; an oxide, such as silicon oxide, PSG, BSG, BPSG; or the like. Dielectric layer 142 can be formed by spin coating, lamination, CVD, or the like, or a combination thereof. After each dielectric layer 142 is formed, it is patterned to expose underlying conductive features, such as underlying vias 106, TSVs 124, and / or portions of metallization layer 144. Patterning can be performed using an acceptable process, such as by exposing the dielectric layer to light when the dielectric layer 142 is a photosensitive material, or by etching using, for example, an anisotropic etch. If the dielectric layer 142 is a photosensitive material, the dielectric layer 142 can be developed after exposure.

[0031] The metallization layers 144 each include vias and / or conductive lines. The vias extend through the corresponding dielectric layers 142, and the conductive lines extend along the corresponding dielectric layers 142. As an example of forming the metallization layers 144, a seed layer (not shown) is formed above the corresponding underlying features. For example, the seed layer may be formed on the corresponding dielectric layers 142 and in an opening through the corresponding dielectric layers 142. In some embodiments, the seed layer is a metal layer that may be a single layer or a composite layer comprising multiple sublayers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer above the titanium layer. The seed layer may be formed using a deposition process such as PVD. A photoresist is then formed on the seed layer and patterned. The photoresist may be formed by spin coating, etc., and may be exposed to patterning. The pattern of the photoresist corresponds to the metallization layers 144. The patterning forms an opening through the photoresist to expose the seed layer. Conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. Conductive material can be formed by electroplating, such as chemical plating or electroplating from seed layer etc. Conductive material can comprise metal or metal alloy, such as copper, titanium, tungsten, aluminum etc. or its combination. Then, remove photoresist and and the part seed layer on which conductive material is not formed. Photoresist can be removed by acceptable ashing or stripping process (such as using oxygen plasma etc.). Once photoresist is removed, the exposed portion of seed layer is just removed, such as by acceptable etching process, such as by wet or dry etching. The remainder of seed layer and conductive material forms a layer of metallization layer 144 of front side heavy wiring structure 140.

[0032] The front side redistribution structure 140 is used as an example for description. More or fewer dielectric layers 142 and metallization layers 144 than shown can be formed by repeating or omitting the aforementioned steps.

[0033] An under-bump metallization (UBM) 146 is formed for external connection to the front-side redistribution structure 140. The UBM 146 has a bump portion extending along the major surface of the upper dielectric layer 142 of the front-side redistribution structure 140 and a via portion extending through the upper dielectric layer 142 of the front-side redistribution structure 140 to physically and electrically couple the upper metallization layer 144 of the front-side redistribution structure 140. As a result, the UBM 146 is electrically connected to the vias 106 and the interconnect die 120 (e.g., TSVs 124). The UBM 146 can be formed of the same material as the metallization layer 144 and can be formed using a similar process as the metallization layer 144. In some embodiments, the UBM 146 has different dimensions than the metallization layer 144.

[0034] exist Figure 7In the embodiment, a buffer layer 154 is formed on the front side redistribution structure 140. The buffer layer 154 may be formed of an insulating material such as silicon oxide, silicon nitride, a molding compound, an epoxy resin, etc. The buffer layer 154 may cover and protect the UBM 146. Optionally, a planarization process is performed on the buffer layer 154 to form a carrier substrate (not shown, see FIG. Figure 8 ) can be bonded to a flat surface. The planarization process can be, for example, CMP, a grinding process, etc.

[0035] exist Figure 8 In the embodiment, the carrier substrate 152 is bonded to the buffer layer 154 , and the carrier substrate 102 and the interposer wafer 100 are detached (or de-bonded). Figure 8 The interposer wafer 100 is illustrated as being flipped. In some embodiments, the carrier substrate 152 is a substrate, such as a bulk semiconductor or a glass substrate. The carrier substrate 152 can be connected to the front side of the interposer wafer 100. The carrier substrate 152 can be attached by an adhesive layer (not shown separately), which can be removed from the structure together with the carrier substrate 152 after processing. In some embodiments, the bonding layer includes an oxide layer, such as a silicon oxide layer. In some embodiments, the bonding layer includes an adhesive, such as a suitable epoxy resin, etc. The separation of the carrier substrate 102 can include projecting light, such as a laser or UV light, onto the release layer 104, so that the release layer 104 decomposes under the heat of the light and the carrier substrate 102 can be removed.

[0036] exist Figure 9 In the embodiment of the present invention, a backside redistribution structure 160 is formed on the bottom surface of the encapsulation 130, the via 106, and the interconnect die 120 (e.g., the substrate 122). Similar to the frontside redistribution structure 140, the backside redistribution structure 160 includes a dielectric layer 162 and a metallization layer 164. The backside redistribution structure 160 can be formed using a process similar to that of the frontside redistribution structure 140.

[0037] The metallization layer 164 is connected to the vias 106 and the interconnect die 120 (e.g., die bridges 126). Additionally, the metallization layer 164 may include die connectors that are bonded to the integrated circuit device. The backside redistribution structure 160 described above is used as an example. More or fewer dielectric layers 162 and metallization layers 164 than shown may be formed in the backside redistribution structure 160.

[0038] exist Figure 10A and Figure 10B In the embodiment, integrated circuit devices 202 and 203 are bonded to the back side of the interposer wafer 100 (eg, to the backside redistribution structure 160 ), and an underfill 210 is formed between the integrated circuit devices 202 and 203 and the interposer wafer 100 . Figure 10A The cross-section shown can be taken along Figure 10B The reference cross-section AA' in top view shown, where like reference numerals denote like features, is taken. A plurality of integrated circuit devices 202 and 203 are placed adjacent to each other in each package region 100P. Figure 10B The layout of the integrated circuit devices 202 and 203 shown in FIG. 1 is provided as an example, and other layouts are contemplated.

[0039] In some embodiments, the integrated circuit devices 202 and 203 in each package area 100P include logic devices 202A and 202B and memory devices 203A and 203B. Each of the logic devices 202A and 202B can be a central processing unit (CPU), a graphics processing unit (GPU), a system-on-a-chip (SoC) die, a microcontroller, a system-on-integrated-chip (SoIC) die, etc. The logic devices 202A and 202B can be integrated circuit dies (similar to Figure 1 The integrated circuit die 50 is depicted) or may be a die stack (similar to Figure 2A Each of the memory devices 203A and 203B may be a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, a hybrid memory cube (HMC) module, a high bandwidth memory (HBM) module, etc. The memory devices 203A and 203B may be integrated circuit dies (similar to Figure 1 The integrated circuit die 50 is depicted) or may be a die stack (similar to Figure 2B The die stack 60B described in FIG.

[0040] Integrated circuit devices 202 and 203 can be placed on backside redistribution structure 160 using, for example, a pick-and-place tool. Conductive connectors 204 can be formed from a reflowable conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or a combination thereof. In some embodiments, conductive connectors 204 are formed by initially forming a solder layer by methods such as evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once the solder layer is formed on the structure, a reflow process can be performed to shape conductive connectors 204 into the desired bump shape. Bonding integrated circuit devices 202 and 203 to interposer wafer 100 can include placing integrated circuit devices 202 and 203 on interposer wafer 100 and reflowing conductive connectors 204. Die connectors 206 are located on the front sides of integrated circuit devices 202 and 203. The conductive connectors 204 form joints between the die connectors 206 of the integrated circuit devices 202 and 203 and the die connectors of the backside redistribution structure 160 , thereby electrically connecting the interposer of the interposer die 100 to the integrated circuit devices 202 and 203 .

[0041] Underfill 210 may be formed around conductive connectors 204 and, in a top view, may surround integrated circuit devices 202 and 203. Underfill 210 may be a continuous material extending from integrated circuit devices 202 and 203 to interposer wafer 100. Underfill 210 may also extend along the sidewalls of integrated circuit devices 202 and 203. Underfill 210 may reduce stress and protect the joints created by solder reflow of conductive connectors 204. Underfill 210 may be formed from an underfill material such as a molding compound, epoxy, or the like. Underfill 210 may be formed by a capillary flow process after integrated circuit devices 202 and 203 are bonded to interposer wafer 100, or may be formed by a suitable deposition method before integrated circuit devices 202 and 203 are bonded to interposer wafer 100. Underfill 210 may be applied in a liquid or semi-liquid form and then cured.

[0042] exist Figure 11 In the process, encapsulant 212 is formed over and around the various components. Once formed, encapsulant 212 encapsulates underfill 210 and integrated circuit devices 202 and 203. Encapsulant 212 may be a molding compound, epoxy resin, or the like. Encapsulant 212 may be applied by compression molding, transfer molding, or the like and formed over interposer wafer 100 such that integrated circuit devices 202 and 203 are buried or covered. Encapsulant 212 may be applied in liquid or semi-liquid form and then cured.

[0043] Optionally, the encapsulation 212 may be thinned (not separately shown) to expose the integrated circuit devices 202 and 203. The thinning process may be a grinding process, CMP, etch-back, or a combination thereof. After the thinning process, the top surfaces of the integrated circuit devices 202 and 203 and the encapsulation 212 are substantially coplanar (within process variations). Thinning is performed until a desired amount of the integrated circuit devices 202 and 203 and the encapsulation 212 are removed.

[0044] exist Figure 12 In the embodiment of the present invention, a carrier exchange is performed, the buffer layer 154 is removed to expose the UBM 146, and a conductive connector 226 is formed on the UBM 146. During the carrier exchange, the carrier 213 may be attached to the encapsulation 212, and the carrier substrate 152 may be removed from the front-side redistribution structure 140. The carrier 213 may be the same as or similar to the carrier substrate 102. The carrier 213 may be attached to the encapsulation 212 via a release layer 214, which may be the same as or similar to the release layer 104. The carrier substrate 152 may be removed by a grinding process, etc. The buffer layer 154 may be removed by a suitable etching process, etc. The conductive connector 226 may be made of the same or similar material as the conductive connector 204 and formed by the same or similar method as the conductive connector 204.

[0045] exist Figure 13 In the embodiment, the carrier 213 is removed, the structure is placed on a tape 215 supported by a frame 216, and the structure on the tape 215 is separated. The removal of the carrier 213 can be the same as or similar to the removal of the carrier substrate 102. The structure on the tape 215 can be separated by sawing, cutting, etc. The separation process can be performed along the scribed lines 218 between the package areas 100P to produce individual integrated circuit package assemblies 200. Each package area 100P can correspond to an integrated circuit package assembly 200. The separation process can also form an interposer 229 in each integrated circuit package assembly 200 by dividing the interposer wafer 100 (see Figure 14A As a result of the singulation process, the interposer 229 and the outer sidewall of the encapsulation body 212 are laterally connected (within the process variation range).

[0046] exist Figure 14A and 14B In the embodiment, the integrated circuit package assembly 200 is bonded to the package substrate 220 , and an underfill 228 is formed between the integrated circuit package assembly 200 and the package substrate 220 . Figure 14A The cross-section shown can be taken along Figure 14B The reference cross-section AA' shown in top view is obtained, wherein like reference numerals denote like features. For illustrative purposes, the integrated circuit devices 202 and 203 and the underfill 210 are shown in FIG. Figure 14B. The package substrate 220 may include a substrate base material 222, which may be formed of a semiconductor material such as silicon, germanium, diamond, etc. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, or combinations thereof may also be used. In addition, the substrate base material 222 may be an SOI substrate. Generally speaking, an SOI substrate includes a semiconductor material layer such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or a combination thereof. In some embodiments, the substrate base material 222 is an insulating core, such as a glass fiber reinforced resin core. An exemplary core material is a glass fiber resin, such as FR4. Other examples of core materials include bismaleimide-triazine (BT) resin, or alternatively, other printed circuit board (PCB) materials or films. The substrate base 222 may be a build-up film, such as Ajinomoto build-up film (ABF) or other laminated materials.

[0047] The package substrate 220 may also include active and passive devices (not shown separately). Devices such as transistors, capacitors, resistors, combinations thereof, etc. may be used to meet the structural and functional requirements of the system design. The devices may be formed using any suitable method. In some embodiments, the package substrate 220 is substantially free of active and passive devices. The package substrate 220 may include metallization layers (not shown separately), through-holes (not shown separately), and bonding pads 224 on the metallization layers and through-holes. The metallization layers may be located above the active and passive devices and are designed to connect the various devices to form functional circuits. The metallization layers may be formed of alternating layers of dielectric material (e.g., low-k dielectric material) and conductive material (e.g., copper), wherein the through-holes interconnect the conductive material layers and may be formed by any suitable process (e.g., deposition, inlaying, etc.). The bonding pads 224 may be located on the surface of the package substrate 220 and may be connected to the conductive connectors 226 when the integrated circuit package assembly 200 is bonded to the package substrate 220. As a result, the integrated circuit package assembly 200 can be electrically connected to the package substrate 220 through the conductive connector 226. The package substrate 220 can also include a conductive connector 225. The conductive connector 225 can be electrically connected to the conductive members of the package substrate 220 and can be connected to an external device (not separately shown).

[0048] An underfill 228 can be formed around the conductive connectors 226 and, in a top view, can surround the integrated circuit package assembly 200. The underfill 228 can be a continuous material extending from the integrated circuit package assembly 200 to the package substrate 220. The underfill 228 can also extend along the sidewalls of the integrated circuit package assembly 200. The underfill 228 can reduce stress and protect the joints created by reflowing solder on the conductive connectors 226. The underfill 228 can be made of the same or similar materials and formed using the same or similar methods as the underfill 210.

[0049] exist Figure 15A 、 15B In FIG. 15C , a stiffener ring 230 is attached to the package substrate 220 via an adhesive 232 . The stiffener ring 230 may be referred to as a ring-shaped structure. The stiffener ring 230 may reduce warpage of the package substrate 220 without inducing harmful stress in the underfill 210 and the underfill 228 in the integrated circuit package assembly 200 . Figure 15A and Figure 15C The cross-sectional views shown can be taken along Figure 15B The reference cross-sections AA' and BB' shown in top view are obtained, wherein like reference numerals denote like features. For illustrative purposes, the integrated circuit devices 202 and 203, the underfill 210, and the adhesive 232 are shown in FIG. Figure 15B Shown in dashed lines. Figure 15A 、 15B The structure shown in Figures 15 and 15C may be referred to as an integrated circuit package 300A.

[0050] The reinforcement ring 230 may include attached segments 230A and suspended segments 230B. For the purpose of illustration, the attached segments 230A and the suspended segments 230B are shown in FIG. Figure 15B and Figure 15C The hanging section 230B and the attachment section 230A may be a continuous piece of material. The attachment section 230A may be attached to the package substrate 220 by an adhesive 232 (see FIG. Figure 15C ), wherein the bottom surface of the attachment segment 230A may be covered by the adhesive 232, and the adhesive 232 may physically contact and extend between the attachment segment 230A and the package substrate 220. For illustrative purposes, Figure 15B Adhesive 232 is shown partially covering the bottom surface of attachment section 230A. Figure 15CAs shown, the bottom surface of the attachment segment 230A may be completely covered by the adhesive 232. The dangling segment 230B may be suspended above the package substrate 220, with the bottom surface of the dangling segment 230B and the cavities 233 between the dangling segment 230B and the package substrate 220 being free of the adhesive 232. As a result, the integrated circuit package assembly 200 and the package substrate 220 may have greater freedom of movement when heated during operation, and stresses in the underfill 210 and the underfill 228 caused by the mismatch in the coefficient of thermal expansion (CTE) between the stiffener ring 230 and the package substrate 220 may be reduced. Consequently, delamination of the underfill 210 from the integrated circuit devices 202 and 203, cracks in the underfill 210, delamination of the underfill 228 from the integrated circuit package assembly 200, and / or cracks in the underfill 228 may be prevented or reduced.

[0051] The reinforcement ring 230 may comprise a high-hardness material, such as copper, stainless steel (e.g., SUS430), Alloy 42, or the like. In some embodiments, the reinforcement ring 230 has a higher CTE than the package substrate 220. In some embodiments, the reinforcement ring 230 has a lower CTE than the package substrate 220. The adhesive 232 may be, for example, epoxy, glue, or a thermally conductive adhesive (e.g., SE4450). The adhesive 232 may be applied in a liquid or semi-liquid form and then cured.

[0052] In a top view, the stiffener ring 230 may surround the integrated circuit package assembly 200. Figure 15B In the illustrated embodiment, the reinforcement ring 230 may include two attachment segments 230A interconnected by a dangling segment 230B. The dangling segments 230B may extend along opposing edges of the package substrate 220. Each attachment segment 230A may be bracket-shaped, and each dangling segment 230B may be bow-shaped. The dangling segments 230B may protrude from the inner sidewalls of the attachment segments 230A toward the integrated circuit package assembly 200. In some embodiments, the longitudinal axes of the dangling segments 230B are substantially perpendicular to the interface between the logic device 202A and the memory device 203A and / or the interface between the logic device 202B and the memory device 203B in the integrated circuit package assembly 200. In some embodiments, the dangling segments 230B are positioned elsewhere between the attachment segments 230A relative to the inner sidewalls of the attachment segments 230A.

[0053] The reinforcement ring 230 may have a length L1 along the long axis of the hanging segment 230B. The length L1 may be in the range of about 50 mm to about 150 mm. The length L1 may be the length of a portion of the reinforcement ring 230, which includes a portion of each of one hanging segment 230B and two attachment segments 230A, such as Figure 15B As shown. The reinforcement ring 230 may have a length L2 perpendicular to the long axis of the hanging segment 230B. The length L2 may be in the range of about 50 mm to about 150 mm. The length L1 and the length L2 may be the same or different. The two attachment segments 230A may be separated by a distance D1, which may correspond to the long axis length of the hanging segment 230B. The distance D1 may also correspond to the length of the cavity 233 (see Figure 15C ). A ratio R1 of distance D1 to length L1 may be in a range of approximately 20% to approximately 60%. When the ratio R1 is in a range of approximately 20% to approximately 60%, the reinforcement ring 230 can be sufficiently attached to the package substrate 220 by the adhesive 232, and the stress in the underfill 210 and the underfill 228 caused by the CTE mismatch between the reinforcement ring 230 and the package substrate 220 can be sufficiently reduced to prevent or reduce delamination. The attachment segment 230A may have a width W1. A ratio R2 of width W1 to length L1 may be in a range of approximately 6% to approximately 20%. The hanging segment 230B may have a width W2. A ratio R3 of width W2 to width W1 may be in a range of approximately 50% to approximately 100%. In some embodiments, width W2 is less than width W1.

[0054] The attachment segment 230A may be spaced apart from the integrated circuit package assembly 200 by a distance D2. A ratio R3 of distance D2 to length L1 may be in a range of approximately 5% to approximately 15%. The overhang segment 230B may be spaced apart from the integrated circuit package assembly 200 by a distance D3. A ratio R4 of distance D3 to length L1 may be in a range of approximately 3% to approximately 12%. In some embodiments, distance D3 is less than distance D2. The inner sidewall of the overhang segment 230B closest to the integrated circuit package assembly 200 may be spaced apart from the inner sidewall of the attachment segment 230A by a distance D5, which may be referred to as the bending distance of the overhang segment 230B. Distance D5 may be greater than 0 and less than approximately 12% of length L1. The attachment segment 230A may be spaced apart from the corresponding edge of the package substrate 220 by a distance D4, which may be in a range of approximately 0.5% to approximately 10% of length L1. The reinforcement ring 230 including the attachment section 230A and the hanging section 230B may have a height H1 ranging from about 2 mm to about 6 mm. The height H1 may refer to a distance between a top surface of the reinforcement ring 230 and a bottom surface of the reinforcement ring 230 .

[0055] Figure 15D FIG. 3 shows an integrated circuit package 300B according to some embodiments. The integrated circuit package 300B has Figure 15A 、 Figure 15B and Figure 15C The integrated circuit package 300A shown in FIG. 1 is similar in structure to the integrated circuit package 300A shown in FIG. 1 , where like reference numerals denote like features. Figure 15D In the illustrated embodiment, the stiffener ring 230 in the integrated circuit package 300B may include four attachment segments 230A interconnected by hanging segments 230B. The attachment segments 230A may be positioned at corners of the package substrate 220. The hanging segments 230B may extend along the edges of the package substrate 220. Each attachment segment 230A may be L-shaped, and each hanging segment 230B may be arcuate. The hanging segments 230B may protrude from the inner sidewalls of the attachment segments 230A toward the integrated circuit package assembly 200.

[0056] Figure 16A FIG. 3 shows an integrated circuit package 302A according to some embodiments. The integrated circuit package 302A has Figure 15A 、 Figure 15B and Figure 15C The integrated circuit package 300A shown in FIG. 1 is similar in structure to the integrated circuit package 300A shown in FIG. 1 , where like reference numerals denote like features. Figure 16A In the illustrated embodiment, the reinforcement ring 230 may include two attachment segments 230A interconnected by a dangling segment 230B. The dangling segments 230B may extend along opposing edges of the package substrate 220. Each attachment segment 230A may have a bracket shape, and each dangling segment 230B may have an arcuate shape. The dangling segments 230B in the integrated circuit package 302A may protrude from the outer sidewalls of the attachment segments 230A, away from the integrated circuit package assembly 200. In some embodiments, the dangling segments 230B are positioned elsewhere between the attachment segments 230A relative to the outer sidewalls of the attachment segments 230A. The outer sidewalls of the dangling segments 230B closest to the edge of the package substrate 220 may be spaced apart from the outer sidewalls of the attachment segments 230A by a distance D6, which may be referred to as the bend distance of the dangling segments 230B. Distance D6 may be greater than 0 and less than approximately 12% of the length L1.

[0057] Figure 16B FIG. 3 shows an integrated circuit package 302B according to some embodiments. The integrated circuit package 302B has Figure 16A The integrated circuit package 302A is similar in structure to the one shown, where like reference numerals indicate like features. Figure 16B In the illustrated embodiment, the stiffener ring 230 in the integrated circuit package 300B may include four attachment segments 230A interconnected by hanging segments 230B. The attachment segments 230A may be positioned at the corners of the package substrate 220. The hanging segments 230B may extend along the edges of the package substrate 220. Each attachment segment 230A may be L-shaped, and each hanging segment 230B may be arcuate. The hanging segments 230B may protrude from the outer sidewalls of the attachment segments 230A away from the integrated circuit package assembly 200.

[0058] Figure 17A FIG. 3 shows an integrated circuit package 304A according to some embodiments. The integrated circuit package 304A has Figure 15A 、 Figure 15B 、 Figure 15C and Figure 16A The integrated circuit packages 300A and 302A shown in FIG. 3 are similar in structure, where like reference numerals denote like features. Figure 17A In the illustrated embodiment, the stiffener ring 230 may include two attachment segments 230A interconnected by a dangling segment 230B that protrudes toward and away from the integrated circuit package assembly 200. The dangling segments 230B may extend along opposing edges of the package substrate 220. Each attachment segment 230A may be bracket-shaped, and each dangling segment 230B may have an arcuate first portion protruding toward the integrated circuit package assembly 200 and an arcuate second portion protruding away from the integrated circuit package assembly 200. A distance D8 may be located between the two protruding portions of the dangling segment 230B. A ratio R5 of the distance D8 to the width W2 may range from approximately 10% to approximately 400%.

[0059] Figure 17B FIG. 3 shows an integrated circuit package 304B according to some embodiments. The integrated circuit package 304B has Figure 15D and Figure 17A The integrated circuit packages 300B and 304A are similar in structure, with like reference numerals indicating like features. Figure 17B In the illustrated embodiment, the stiffener ring 230 in the integrated circuit package 304B may include four attachment segments 230A interconnected by hanging segments 230B. The attachment segments 230A may be disposed at the corners of the package substrate 220. The hanging segments 230B may extend along the edge of the package substrate 220. Each attachment segment 230A may be L-shaped, and each hanging segment 230B may have a first portion that is arched and protrudes toward the integrated circuit package assembly 200, and a second portion that is arched and protrudes away from the integrated circuit package assembly 200.

[0060] Figure 18A FIG. 3 shows an integrated circuit package 306A according to some embodiments. The integrated circuit package 306A has Figure 17A The integrated circuit package 304A is similar in structure to the one shown, where like reference numerals indicate like features. Figure 18A In the illustrated embodiment, the reinforcement ring 230 may include two attachment segments 230A interconnected by a hanging segment 230B. The hanging segments 230B may extend along opposite edges of the package substrate 220. Each attachment segment 230A may be bracket-shaped, and each hanging segment 230B may include two or more strips spaced apart from each other. Figure 18AThe illustrated embodiment shows two strips, and other embodiments may have more strips. Some strips of the hanging segments 230B in the integrated circuit package 306A may have sidewalls that are flush with the outer sidewalls of the attachment segment 230A, and some strips of the hanging segments 230B may have sidewalls that are flush with the inner sidewalls of the attachment segment 230A. The strips of the hanging segments 230B may have a width W3. A ratio R6 of width W3 to width W1 may be in a range of approximately 20% to approximately 40%. In some embodiments, width W3 is less than width W1. A distance D9 may be located between two adjacent hanging segments 230B along the same edge of the package substrate 220. A ratio R7 of distance D9 to width W2 may be in a range of approximately 20% to approximately 80%.

[0061] Figure 18B FIG. 3 shows an integrated circuit package 306B according to some embodiments. The integrated circuit package 306B has Figure 17B and 18A The integrated circuit packages 304B and 306A are similar in structure, with like reference numerals indicating like features. Figure 18B In the illustrated embodiment, the stiffener ring 230 in the integrated circuit package 306B may include four attachment segments 230A interconnected by hanging segments 230B. The attachment segments 230A may be disposed at the corners of the package substrate 220. The hanging segments 230B may extend along the edges of the package substrate 220. Each attachment segment 230A may be bracket-shaped, and each hanging segment 230B may include two or more strips spaced apart from each other. Figure 18B The illustrated embodiment shows two strips, and other embodiments may have more strips. Some strips of the hanging segment 230B in the integrated circuit package 306B may have sidewalls that are flush with the outer sidewalls of the attachment segment 230A, and some strips of the hanging segment 230B may have sidewalls that are flush with the inner sidewalls of the attachment segment 230A.

[0062] Figure 19A FIG. 3 shows an integrated circuit package 308A according to some embodiments. The integrated circuit package 308A has Figure 15A 、 Figure 15B and Figure 15C The integrated circuit package 300A shown in FIG. 1 is similar in structure to the integrated circuit package 300A shown in FIG. 1 , where like reference numerals denote like features. Figure 18A In the illustrated embodiment, the reinforcement ring 230 may include two attachment segments 230A interconnected by a hanging segment 230B. The attachment segments 230A may each include a protrusion 234 that may protrude from the inner sidewall of the attachment segment 230A toward the integrated circuit package assembly 200. For illustrative purposes, Figure 19AThe middle protrusion 234 is enclosed by a dashed line. The protrusion 234 may also be attached to the package substrate 220 via the adhesive 232 and may enhance the adhesion of the stiffener ring 230 to the package substrate 220. The hanging segments 230B may extend along opposite edges of the package substrate 220. Each attachment segment 230A may be bracket-shaped, and each hanging segment 230B may be arcuate. The stiffener ring 230 of the integrated circuit packages 302A, 304A, and 306A may also include the protrusion 234 shown in the integrated circuit package 308A.

[0063] Figure 19B FIG. 3 shows an integrated circuit package 308B according to some embodiments. The integrated circuit package 308B has Figure 15D The integrated circuit package 300B shown is similar in structure, where like reference numerals indicate like features. Figure 19B In the illustrated embodiment, the stiffener ring 230 in the integrated circuit package 308B may include four attachment segments 230A interconnected by hanging segments 230B. The attachment segments 230A may be disposed at one or more corners of the package substrate 220. The attachment segments 230A may each include a protrusion 234 that may protrude from the inner sidewall of the attachment segment 230A toward the integrated circuit package assembly 200. For illustrative purposes, the attachment segments 230A may be disposed at one or more corners of the package substrate 220. Figure 19A The middle protrusion 234 is enclosed by a dashed line. The protrusion 234 may also be attached to the package substrate 220 via adhesive 232 and may enhance the adhesion of the stiffener ring 230 to the package substrate 220. The hanging segments 230B may extend along the edge of the package substrate 220. Each attachment segment 230A may be L-shaped, and each hanging segment 230B may be arcuate. The stiffener rings 230 of integrated circuit packages 300B, 302B, 304B, and 306B may also include the protrusion 234 shown in integrated circuit package 308B.

[0064] Figure 20A 、 20B 20C shows an integrated circuit package 310 according to some embodiments. The integrated circuit package 310 has Figure 15A 、 Figure 15B and Figure 15C The integrated circuit package 300A shown in FIG. 1 is similar in structure to the integrated circuit package 300A shown in FIG. 1 , where like reference numerals denote like features. Figure 20A 、 Figure 20B and Figure 20C In the illustrated embodiment, the attachment section 230A of the reinforcement ring 230 may have a height H1, and the hanging section 230B of the reinforcement ring 230 may have a height H2 that is different from the height H1, as shown. Figure 20C In some embodiments, the height H2 is less than the height H1. The ratio R8 of the height H2 to the height H1 may be in the range of about 50% to about 80%. As an example, Figure 20CThe overhanging segment 230B is shown in a position where the bottom surface of the overhanging segment 230B is flush with the bottom surface of the attachment segment 230A. In some embodiments, the bottom surface of the overhanging segment 230B can be positioned at a higher position relative to the bottom surface of the attachment segment 230A. The attachment segments 230A and the overhanging segments 230B of the stiffening ring 230 of the integrated circuit packages 300B, 302A, 302B, 304A, 304B, 306A, 306B, 308A, and 308B can also have similar heights as the attachment segments 230A and the overhanging segments 230B of the stiffening ring 230 of the integrated circuit package 310, as shown.

[0065] Embodiments can achieve certain advantages. By using a stiffener ring 230 including hanging segments 230B in integrated circuit packages 300A, 300B, 302A, 302B, 304A, 304B, 306A, 306B, 308A, 308B, and 310, the integrated circuit package assembly 200 and the package substrate 220 can have greater freedom of movement when heated during operation, and delamination and / or cracking of the underfill 210 and / or underfill 228 can be prevented or reduced. As a result, the long-term reliability of the aforementioned integrated circuit packages including the stiffener ring 230 can be improved.

[0066] In one embodiment, a semiconductor package includes: a substrate; an integrated circuit package component bonded to the substrate, wherein the integrated circuit package component includes a semiconductor die; and a ring-shaped structure located on the substrate, wherein, in a top view, the ring-shaped structure surrounds the integrated circuit package component and includes: a first attachment segment attached to the substrate by an adhesive, wherein the first attachment segment is spaced a first distance from the package component; a second attachment segment attached to the substrate by an adhesive, wherein the second attachment segment is spaced a second distance from the package component; and a first hanging segment located between the first attachment segment and the second attachment segment, wherein the first hanging segment is suspended above the substrate, wherein the first hanging segment is spaced a third distance from the package component, wherein the third distance is different from the first and second distances. In one embodiment, the third distance is less than the first and second distances. In one embodiment, the third distance is greater than the first and second distances. In one embodiment, the width of the first hanging segment is less than the width of the first and second attachment segments. In one embodiment, the height of the first hanging segment is less than the height of the first and second attachment segments. In one embodiment, the first attachment segment, the second attachment segment, and the first attachment segment are formed from a single, continuous piece of material. In one embodiment, the first attachment segment, the second attachment segment, and the first hanging segment comprise copper. In one embodiment, the first hanging segment comprises a first portion protruding toward the integrated circuit package assembly and a second portion protruding away from the integrated circuit package assembly.

[0067] In one embodiment, a semiconductor package includes: a substrate comprising a first edge and a second edge, wherein the first edge intersects the second edge; an integrated circuit package assembly bonded to the substrate, wherein the package assembly includes a semiconductor die; an underfill disposed between the integrated circuit package assembly and the substrate; and a stiffener ring disposed on the substrate, wherein, in a top view, the stiffener ring surrounds the integrated circuit package assembly, and wherein a first portion of the stiffener ring extends along the first edge of the substrate, the first portion comprising: a first attachment segment having a first width, wherein a bottom surface of the first attachment segment is covered by an adhesive; and a second attachment segment having a second width, wherein a bottom surface of the second attachment segment is covered by the adhesive. A first hanging segment extends from the first attachment segment to the second attachment segment, the first hanging segment having a third width, wherein the third width is less than the first and second widths, and wherein a bottom surface of the first hanging segment is free of adhesive. In one embodiment, the first hanging segment protrudes from an inner sidewall of the first attachment segment and an inner sidewall of the second attachment segment toward the integrated circuit package assembly. In one embodiment, the first hanging segment protrudes from an outer sidewall of the first attachment segment and an outer sidewall of the second attachment segment away from the integrated circuit package assembly. In one embodiment, the second portion of the reinforcement ring extends along the second edge of the substrate, the second portion comprising: a third attachment segment having a fourth width, wherein a bottom surface of the third attachment segment is covered by adhesive; a fourth attachment segment having a fifth width, wherein a bottom surface of the fourth attachment segment is covered by adhesive; and a second hanging segment extending from the third attachment segment to the fourth attachment segment, the second hanging segment having a sixth width, wherein the sixth width is less than the fourth width and the fifth width, wherein a bottom surface of the second hanging segment is free of adhesive. In one embodiment, in a top view, the first hanging segment comprises a first portion and a second portion, each of the first portion and the second portion extending from the first attachment segment to the second attachment segment, the first portion being spaced apart from the second portion.

[0068] In one embodiment, a method of manufacturing a semiconductor package includes bonding an integrated circuit package assembly to a substrate, wherein the integrated circuit package assembly includes a semiconductor die, and wherein the substrate includes a first edge and a second edge, wherein the first edge intersects the second edge; placing an underfill between the integrated circuit package assembly and the substrate; and attaching a ring structure to the substrate, wherein the ring structure surrounds the integrated circuit package assembly in a top view, and wherein a first portion of the ring structure extends along the first edge of the substrate, the first portion including: a first attachment segment attached to the substrate by an adhesive, wherein the first attachment segment is spaced a first distance from the integrated circuit package assembly; a second attachment segment attached to the substrate by an adhesive, wherein the second attachment segment is spaced a second distance from the integrated circuit package assembly; and a first hanging segment positioned between the first and second attachment segments, wherein the first hanging segment contacts the first and second attachment segments, wherein the first hanging segment is spaced a first cavity from the substrate, wherein the first hanging segment is spaced a third distance from the integrated circuit package assembly, and wherein the third distance is different from the first and second distances. In one embodiment, the third distance is less than the first and second distances. In one embodiment, the third distance is greater than the first and second distances. In one embodiment, the height of the first hanging segment is less than the height of the first attachment segment and the height of the second attachment segment. In one embodiment, the second portion of the annular structure extends along the second edge of the substrate, wherein the second portion includes a protrusion extending toward the package component, and wherein the protrusion is connected to the substrate by an adhesive. In one embodiment, the second portion of the annular structure extends along the second edge of the substrate, the second portion includes: a third attachment segment attached to the substrate by an adhesive; a fourth attachment segment attached to the substrate by an adhesive; and a second hanging segment located between the third attachment segment and the fourth attachment segment, wherein the second hanging segment contacts the third attachment segment and the fourth attachment segment, and wherein the second hanging segment is separated from the substrate by a second cavity. In one embodiment, the first portion of the annular structure intersects the second portion at a first corner of the annular structure, and wherein the first corner includes a protrusion extending toward the integrated circuit package component, and wherein the protrusion is connected to the substrate by an adhesive.

[0069] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present invention. Those skilled in the art will understand that they can easily use the present invention as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present invention, and that they can make various changes, substitutions, and modifications without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor package, characterized in that: include: substrate; an integrated circuit package assembly bonded to the substrate, wherein the integrated circuit package assembly includes a semiconductor die; as well as a ring structure located on the substrate, wherein in a top view, the ring structure surrounds the integrated circuit package component, wherein the ring structure comprises: a first attachment section attached to the substrate by an adhesive, wherein the first attachment section is spaced a first distance from the package component; a second attachment section attached to the substrate by the adhesive, wherein the second attachment section is spaced apart from the package component by a second distance; and A first suspension segment is positioned between the first attachment segment and the second attachment segment, wherein the first suspension segment is suspended above the substrate, wherein the first suspension segment is spaced apart from the package component by a third distance, and wherein the third distance is different from the first distance and the second distance.

2. The semiconductor package according to claim 1, wherein The third distance is smaller than the first distance and the second distance.

3. The semiconductor package according to claim 1, wherein The third distance is greater than the first distance and the second distance.

4. The semiconductor package according to claim 1, wherein The width of the first hanging section is smaller than the width of the first attachment section and the width of the second attachment section.

5. The semiconductor package according to claim 1, wherein The height of the first hanging section is smaller than the height of the first attachment section and the height of the second attachment section.

6. The semiconductor package according to claim 1, wherein The first hanging segment includes a first portion protruding toward the integrated circuit package assembly and a second portion protruding away from the integrated circuit package assembly.

7. A semiconductor package, characterized in that: include: a substrate comprising a first edge and a second edge, wherein the first edge intersects the second edge; an integrated circuit package assembly bonded to the substrate, wherein the package assembly includes a semiconductor die; an underfill between the integrated circuit package and the substrate; as well as a stiffener ring positioned on the substrate, wherein in a top view, the stiffener ring surrounds the integrated circuit package assembly, and wherein a first portion of the stiffener ring extends along the first edge of the substrate, the first portion comprising: a first attachment section having a first width, wherein a bottom surface of the first attachment section is covered by an adhesive; a second attachment section having a second width, wherein a bottom surface of the second attachment section is covered by the adhesive; and A first hanging segment extends from the first attachment segment to the second attachment segment, the first hanging segment having a third width, wherein the third width is smaller than the first width and the second width, wherein a bottom surface of the first hanging segment is free of the adhesive.

8. The semiconductor package according to claim 7, wherein: The first hanging section protrudes from an inner sidewall of the first attachment section and an inner sidewall of the second attachment section toward the integrated circuit package assembly.

9. The semiconductor package according to claim 7, wherein: The first hanging segment protrudes away from the integrated circuit package assembly from the outer sidewalls of the first attachment segment and the second attachment segment.

10. The semiconductor package according to claim 7, wherein A second portion of the reinforcement ring extends along the second edge of the substrate, the second portion comprising: a third attachment segment having a fourth width, wherein a bottom surface of the third attachment segment is covered by the adhesive; a fourth attachment segment having a fifth width, wherein a bottom surface of the fourth attachment segment is covered by the adhesive; and The second hanging segment extends from the third attachment segment to the fourth attachment segment, and has a sixth width, wherein the sixth width is smaller than the fourth width and the fifth width, and the bottom surface of the second hanging segment is free of the adhesive.

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