Radio frequency chip

Abstract

The utility model provides a radio frequency chip. The radio frequency chip comprises a radio frequency chip main body, a waterproof ring, a chip isolation ring, at least two sealing rings, at least one stress relief ring and a cutting belt, wherein the radio frequency chip main body comprises a semiconductor device, and the semiconductor device is located on a device layer of an SOI wafer substrate; the waterproof ring is arranged around the radio frequency chip main body; the chip isolating ring is arranged around the radio frequency chip main body and is located at the periphery of the waterproof ring; the two sealing rings comprise a first sealing ring and a second sealing ring, and the sealing rings are arranged around the radio frequency chip main body and are located outside the chip isolation ring; an air gap is formed in the stress relief ring, and the stress relief ring is arranged around the sealing ring; the cutting tape is disposed around the stress relief ring. According to the radio frequency chip provided by the utility model, the stress relief ring is arranged outside the sealing ring, so that the internal and external stress is further relieved, and the radio frequency chip main body is better protected.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductor radio frequency chips, in particular to a radio frequency chip. Background Art

[0002] The package seal ring that protects the chip on the wafer usually consists of three parts: an outer seal ring, an inner seal ring, and a chip isolation ring. The outer seal ring is mainly used to relieve stress caused by cutting, the inner seal ring is mainly used to relieve stress inside and outside the chip, and the chip isolation ring is mainly used to relieve stress within the chip.

[0003] However, with the development of 5G technology, RF switches, low-noise power amplifiers, and other components will be integrated onto RF SOI wafer substrates. Furthermore, various advanced technologies have been introduced to improve chip performance at high frequencies, making RF chips increasingly expensive. To improve the utilization of RF SOI wafer substrates, the dicing tape is becoming increasingly smaller. RF SOI wafer substrates are multi-layer thin-film structures, making the RF chip's peripheral protection structure increasingly important during the dicing process.

[0004] Therefore, how to effectively protect the main body of the RF chip has become a technical problem that the industry urgently needs to solve. Utility Model Content

[0005] The utility model aims to provide a radio frequency chip to solve the problem of how to effectively protect the radio frequency chip body when the chip is cut.

[0006] In order to solve the above technical problems, the present invention provides a radio frequency chip, comprising:

[0007] A radio frequency chip body, the radio frequency chip body including a semiconductor device, the semiconductor device being located in a device layer of an SOI wafer substrate;

[0008] A waterproof ring, which is arranged around the radio frequency chip body;

[0009] A chip isolation ring, which is arranged around the RF chip body and located on the periphery of the waterproof ring;

[0010] At least two sealing rings: a first sealing ring and a second sealing ring, wherein the sealing rings are arranged around the RF chip body and are located outside the chip isolation ring;

[0011] At least one stress relief ring is provided with an air gap therein; the stress relief ring is provided around the sealing ring; wherein a cutting belt is provided on the periphery of the stress relief ring.

[0012] Optionally, the stress relief ring includes a first isolation groove and a first dielectric layer deposited in the first isolation groove; the waterproof ring includes a second isolation groove and a second dielectric layer deposited in the second isolation groove; and the air gap is formed in the first dielectric layer and the second dielectric layer.

[0013] Optionally, the depth of the first isolation trench is greater than or equal to that of the second isolation trench.

[0014] Optionally, the aspect ratio of the first isolation trench is greater than or equal to 8.

[0015] Optionally, both the first dielectric layer and the second dielectric layer include:

[0016] a first silicon oxide dielectric layer deposited on the inner wall of the first isolation trench / the second isolation trench;

[0017] a silicon nitride dielectric layer, deposited on the first silicon oxide dielectric layer;

[0018] A second silicon oxide dielectric layer is deposited on the silicon nitride dielectric layer and fills the first isolation trench / the second isolation trench; wherein the air gap is formed in the second silicon oxide dielectric layer.

[0019] Optionally, the thickness of the first silicon oxide dielectric layer is 50-300 angstroms.

[0020] Optionally, the thickness of the silicon nitride dielectric layer is 100-1000 angstroms.

[0021] Optionally, the number of the stress relief rings is at least three; and the stress relief rings are arranged between the chip isolation ring and the cutting tape.

[0022] Optionally, the three stress relief rings are respectively arranged between the chip isolation ring and the first sealing ring, between the first sealing ring and the second sealing ring, and between the second sealing ring and the cutting tape.

[0023] Optionally, the number of stress relief rings at the same position is more than two.

[0024] Optionally, the depths of the waterproof ring and the stress relief ring penetrate the device layer of the SOI wafer substrate to the buried oxide layer of the SOI wafer substrate.

[0025] Compared with the prior art, the present invention has the following beneficial effects:

[0026] In a radio frequency chip provided by the present invention, the peripheral protection structure of the radio frequency chip body includes a waterproof ring, a chip isolation ring, a first sealing ring, a second sealing ring, and a stress relief ring. By adding a stress relief ring with an air gap to the outside of the sealing ring, the peripheral protection structure of the radio frequency chip body can better relieve stress from both inside and outside during cutting, thereby improving the protection of the radio frequency chip body. On this basis, it is beneficial to optimize the design, cost, and packaging of the radio frequency chip. In addition, the stress relief ring can be manufactured simultaneously with the waterproof ring, without the need for a new process.

[0027] In addition, after setting the stress relief ring, the peripheral protection structure of the RF chip can also better relieve the stress caused by cutting, so that the cutting belt can be further reduced, and the chip isolation ring, the first sealing ring and the second sealing ring outside the RF chip body can also be further reduced, so that the utilization rate of the RF SOI wafer substrate is further improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 This is a schematic diagram of a radio frequency chip provided by an embodiment of the present invention. Figure 1 ;

[0029] Figure 2 This is a schematic diagram of a radio frequency chip provided by an embodiment of the present invention. Figure 2 ;

[0030] Figure 3 is a schematic diagram of a radio frequency chip provided by another embodiment of the present utility model;

[0031] Figure 4 It is along Figure 1 A schematic diagram of the cross-sectional structure in the direction A1-A2 shown;

[0032] Figure 5a-5f is based on Figure 3 The structure of the RF chip shown is a schematic diagram corresponding to different process stages of forming a stress relief ring and a waterproof ring.

[0033] Reference numerals:

[0034] 1- RF chip body;

[0035] 2- waterproof ring;

[0036] 3-Chip isolation ring;

[0037] 4-first sealing ring;

[0038] 5- second sealing ring;

[0039] 6-stress relief ring;

[0040] 7- cutting belt;

[0041] 8- air gap;

[0042] 9-metal interconnection layer;

[0043] 10-passivation film;

[0044] 11-device layer;

[0045] 12-first isolation trench;

[0046] 13- second isolation groove;

[0047] 14-External window;

[0048] 601-first silicon oxide dielectric layer;

[0049] 602-silicon nitride dielectric layer;

[0050] 603 - second silicon oxide dielectric layer. DETAILED DESCRIPTION

[0051] The following will be combined with the accompanying drawings to clearly and completely describe the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without inventive effort are within the scope of protection of the present invention. The terms "first," "second," "third," etc. in the specification and claims of the present invention and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" and "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus that includes a series of steps or elements is not necessarily limited to those steps or elements explicitly listed, but may include other steps or elements that are not explicitly listed or that are inherent to such process, method, product, or apparatus.

[0052] As described in the background technology, the peripheral protection structure of the RF chip in the prior art usually only includes a waterproof ring, a chip isolation ring, a first sealing ring and a second sealing ring. However, as the cutting tape becomes narrower and narrower, the peripheral protection structure of the RF chip in the prior art cannot protect the chip body well.

[0053] In view of this, the present invention creatively proposes a radio frequency chip, which includes: a radio frequency chip body, a waterproof ring, a chip isolation ring, at least two sealing rings, at least one stress relief ring and a cutting tape; wherein, the radio frequency chip body includes a semiconductor device, and the semiconductor device is located in the device layer of the SOI wafer substrate; the waterproof ring is arranged around the radio frequency chip body; the chip isolation ring is arranged around the radio frequency chip body and is located outside the waterproof ring; the two sealing rings include a first sealing ring and a second sealing ring, and the sealing rings are arranged around the radio frequency chip body and are located outside the chip isolation ring; an air gap is provided in the stress relief ring, and the stress relief ring is arranged around the sealing ring; the cutting tape is arranged around the stress relief ring.

[0054] The RF chip provided by this utility model adds a stress relief ring with an air gap outside the sealing ring, allowing the peripheral protective structure of the RF chip body to better relieve stress from both inside and outside the chip during chip cutting, thereby improving the protection of the RF chip body. This helps optimize the design, cost, and packaging of the RF chip. Furthermore, the stress relief ring can be manufactured simultaneously with the waterproof ring, eliminating the need for additional processing.

[0055] In order to make the above-mentioned objectives, features and beneficial effects of the present invention more obvious and easy to understand, the technical solution of the present invention is described in detail below with reference to the accompanying drawings.

[0056] in, Figure 1 This is a schematic diagram of a radio frequency chip provided by an embodiment of the present invention. Figure 1 .

[0057] Please refer to Figure 1 In one embodiment of the present invention, a radio frequency chip is provided, including: a radio frequency chip body 1, a waterproof ring 2, a chip isolation ring 3, at least two sealing rings, a stress relief ring 6 and a cutting tape 7.

[0058] Among them, the RF chip body 1 includes a semiconductor device, and the semiconductor device is located on the device layer of the SOI wafer substrate. The semiconductor device can be understood to include a RF semiconductor device. The SOI wafer substrate is a silicon substrate on an insulator, that is, a buried oxide layer is added between the top silicon and the bottom substrate. SOI wafer substrates are widely used in CMOS devices, RF devices and silicon photonic devices. Of course, the present invention is not limited to this. The substrate in the embodiment of the present invention can also be other types of substrates, such as a germanium substrate on an insulator.

[0059] The waterproof ring 2 is disposed around the RF chip body 1; this can be understood as being disposed around the RF chip body 1 and on its periphery. The provision of the waterproof ring 2 prevents moisture from penetrating the chip, improving chip reliability. While one or more waterproof rings 2 are provided in this embodiment, one is used as an example. However, those skilled in the art will appreciate that two or more waterproof rings 2 may be provided.

[0060] The chip isolation ring 3 is arranged around the RF chip body 1 and is located outside the waterproof ring 2; it can be understood that the chip isolation ring 3 is arranged around the waterproof ring 2 and outside the waterproof ring 2. Since the waterproof ring 2 is arranged around the RF chip body 1, the chip isolation ring 3 is actually also arranged around the RF chip body 1, but is located outside the waterproof ring 2.

[0061] The number of sealing rings is, for example, two, specifically a first sealing ring 4 and a second sealing ring 5; the first sealing ring 4 and the second sealing ring 5 are both arranged around the RF chip body 1 and located outside the chip isolation ring 3; specifically, the first sealing ring 4 is located on the periphery of the chip isolation ring 3, and the second sealing ring 5 is located on the periphery of the first sealing ring 4. Of course, those skilled in the art should appreciate that the number of sealing rings is not limited to two, and can be more than two, for example, three or four. When the number of sealing rings is three or more, their setting positions can be appropriately adjusted with reference to the position settings of the two sealing rings. For example, when the number of sealing rings is three, the third sealing ring is located on the periphery of the second sealing ring 5.

[0062] Please refer to Figure 1 As an embodiment, the chip isolation ring 3, first sealing ring 4, and second sealing ring 5 are all intermittent rings, arranged around the RF chip body 1. The chip isolation ring 3, first sealing ring 4, and second sealing ring 5 are intermittently staggered. These three intermittent rings, arranged in staggered steps around the RF chip body, effectively reduce noise transmission.

[0063] in, Figure 2 This is a schematic diagram of a radio frequency chip provided by an embodiment of the present invention. Figure 2 .

[0064] Please refer to Figure 2 As another embodiment, the chip isolation ring 3, the first sealing ring 4 and the second sealing ring 5 are all continuous rings, which are arranged around the RF chip body 1 and can protect the RF chip body 1.

[0065] An air gap is provided in the stress relief ring 6, and the stress relief ring 6 is provided around the sealing ring, that is, the stress relief ring 6 is provided on the periphery of the second sealing ring 5, and the cutting tape 7 is provided on the periphery of the stress relief ring 6. By providing the stress relief ring 6 between the cutting tape 7 and the sealing ring, the stress from the cutting tape 7 when cutting the chip along the cutting tape 7 can be relieved, which is beneficial to protecting the RF chip body 1. Moreover, since an air gap is provided in the stress relief ring 6, the stress relief effect can be greatly increased, and the RF chip body 1 can be protected more effectively. In the prior art, in order to ensure that the RF chip is not affected by stress during the cutting process and thus cracks occur, the cutting tape width is often set to 60 microns. The present invention forms a stress relief ring, which relieves the stress caused by cutting, thereby ensuring that the cutting stress problem of the RF chip is not affected when the cutting tape is reduced, so that the cutting tape can be reduced to 30-40 microns, while ensuring the performance of the RF chip body and improving the utilization rate of the RF SOI wafer.

[0066] In the RF chip provided by one embodiment of the present invention, a waterproof ring 2, a chip isolation ring 3, a first sealing ring 4, a second sealing ring 5, and a stress relief ring 6 are sequentially arranged from the inside out between the periphery of the RF chip body 1 and the dicing tape 7. The waterproof ring 2, chip isolation ring 3, first sealing ring 4, second sealing ring 5, and stress relief ring 6 constitute the peripheral protection structure of the RF chip body 1, achieving both waterproof and stress protection for the RF chip. Furthermore, an air gap is provided in the stress relief ring 6, thereby significantly enhancing the stress relief effect and more effectively protecting the RF chip body.

[0067] Among them, Figure 1 In the embodiment shown, the number of stress relief rings 6 is one. Of course, in different embodiments, the number of stress relief rings 6 can also be other different values, for example, Figure 3 As shown, in another embodiment of the present invention, the number of the stress relief rings 6 is three; the three stress relief rings 6 are arranged between the chip isolation ring 3 and the dicing tape 7. Specifically, the three stress relief rings 6 are respectively arranged between the chip isolation ring 3 and the first sealing ring 4, between the first sealing ring 4 and the second sealing ring 5, and between the second sealing ring 5 and the dicing tape 7.

[0068] It should be noted that the number of stress relief rings 6 can also be other values, such as 2, 4, etc.; of course, in actual situations, if the limitation of chip area is taken into account, the number of stress relief rings 6 generally does not exceed 4. And when multiple stress relief rings 6 need to be set, the positions of the stress relief rings 6 in different embodiments can be different, and the present invention is not limited to this. For example, when the number of stress relief rings 6 is two, one stress relief ring 6 is set between the sealing ring and the cutting tape 7, and the other stress relief ring 6 can be set between the chip isolation ring 3 and the sealing ring or between the first sealing ring 4 and the second sealing ring 5. There are multiple options for the position setting of multiple stress relief rings 6, and multiple stress relief rings 6 can be set at one position, which is not limited by the present invention.

[0069] in, Figure 4 It is along Figure 1 Schematic diagram of the cross-sectional structure in the A1-A2 direction shown.

[0070] Please refer to Figure 4 In a specific embodiment, the stress relief ring 6 includes a first isolation groove and a first dielectric layer deposited in the first isolation groove; the waterproof ring 2 includes a second isolation groove and a second dielectric layer deposited in the second isolation groove; and the air gap 8 is formed between the first dielectric layer and the second dielectric layer. The air gap 8 is naturally formed during the deposition of the dielectric layers.

[0071] In a specific embodiment, the first isolation trench has an aspect ratio greater than or equal to 8. This makes it difficult to completely fill the first isolation trench using existing processes, thereby relatively easily forming an air gap in the first isolation trench when depositing the first dielectric layer. Of course, it should be understood that the present invention is not limited to this aspect ratio, and the first isolation trench may have other aspect ratios, as long as an air gap is formed when depositing the first dielectric layer.

[0072] As a specific embodiment, the depth of the waterproof ring 2 and the stress relief ring 6 penetrates the device layer 11 of the SOI wafer substrate to the buried oxide layer of the SOI wafer substrate to improve the protection of the RF chip body 1.

[0073] As a specific embodiment, the first dielectric layer and the second dielectric layer respectively include:

[0074] A first silicon oxide dielectric layer 601 is deposited on the inner wall of the first isolation trench 12 / the second isolation trench 13;

[0075] A silicon nitride dielectric layer 602 is deposited on the first silicon oxide dielectric layer 601;

[0076] The second silicon oxide dielectric layer 603 is deposited on the silicon nitride dielectric layer 602 and fills the first isolation trench 12 / the second isolation trench 13 ; wherein the air gap 8 is formed in the second silicon oxide dielectric layer 603 .

[0077] As an example, the thickness of the first silicon oxide dielectric layer 601 is 50-300 angstroms.

[0078] As an example, the thickness of the silicon nitride dielectric layer 602 is 100-1000 angstroms.

[0079] The following is a detailed description of the preparation process of the stress relief ring and the waterproof ring of the present invention.

[0080] in, Figures 5a-5f is based on Figure 4 The structure of the RF chip shown is a schematic diagram corresponding to different process stages of forming the stress relief ring 6 and the waterproof ring 2.

[0081] Specifically, please refer to Figures 5a-5f The process steps for forming the stress relief ring 6 and the waterproof ring 2 include:

[0082] S1: Provide an SOI wafer substrate, fabricate an RF chip on the SOI wafer substrate and form a metal interconnection layer 9 to form an RF chip body 1; and while forming the metal interconnection layer 9, form a chip isolation ring 3, a first sealing ring 4, and a second sealing ring 5 in the peripheral area of ​​the RF chip body 1; wherein the chip isolation ring 3, the first sealing ring 4, and the second sealing ring 5 are sequentially distributed between the RF chip body 1 and the dicing tape 7 from the inside to the outside; Figure 5a shown.

[0083] Furthermore, as a preferred embodiment, after forming the chip isolation ring 3, the first sealing ring 4 and the second sealing ring 5, an oxide layer is deposited on the wafer surface to protect the top metal layer and prevent subsequent processes from damaging the metal interconnect layer 9;

[0084] S2: A first isolation trench 12 and a second isolation trench 13 are respectively formed between the second sealing ring 5 and the dicing tape 7 and between the RF chip body 1 and the chip isolation ring 3 by etching. Specifically, the first isolation trench 12 and the second isolation trench 13 penetrate the device layer 11 of the SOI wafer substrate to the buried oxide layer of the SOI wafer substrate, as shown in FIG. Figure 5b shown.

[0085] S3: A first silicon oxide dielectric layer 601, a silicon nitride dielectric layer 602, and a second silicon oxide dielectric layer 603 are deposited in the first isolation trench 12 and the second isolation trench 13 in sequence to form a stress relief ring 6 and a waterproof ring 2 respectively; wherein the first silicon oxide dielectric layer 601 covers the sidewalls and the bottom of the first isolation trench and the second isolation trench, the silicon nitride dielectric layer 602 covers the first silicon oxide dielectric layer 601, and the second silicon oxide dielectric layer 603 fills the first isolation trench and the second isolation trench; wherein, due to the aspect ratio of the first isolation trench and the second isolation trench, an air gap 8 is formed in the second silicon oxide dielectric layer 603; Figure 5c-5e shown.

[0086] As an example, the first silicon oxide dielectric layer 601, the silicon nitride dielectric layer 602, and the second silicon oxide dielectric layer 603 can be deposited by chemical vapor deposition; however, it should be appreciated that the present invention is not limited thereto, and each dielectric layer can also be formed by other methods.

[0087] S4: Grind the second silicon oxide dielectric layer 603 flat, then deposit the passivation film 10, and then etch to form an external window 14 with the metal interconnection layer 9; Figure 5f shown.

[0088] As an example, the second silicon oxide dielectric layer 603 may be polished by chemical mechanical polishing; however, it should be appreciated that the present invention is not limited thereto, and the second silicon oxide dielectric layer 603 may also be polished by other methods.

[0089] In summary, the embodiment of the present invention provides a radio frequency chip. By adding a stress relief ring with an air gap to the outside of the sealing ring, the peripheral protection structure of the radio frequency chip body can better relieve the stress from the inside and outside when the chip is cut, thereby improving the protection of the radio frequency chip body. On this basis, it is beneficial to optimize the design, cost and packaging of the radio frequency chip. In addition, the stress relief ring can be manufactured at the same time as the waterproof ring without the need for a new process; further, the stress relief ring can reduce the possibility of the radio frequency chip body being affected by cutting stress when the cutting band is reduced.

[0090] Although the present invention is disclosed as above, it is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope defined by the claims.

Claims

1. A radio frequency chip, characterized in that: include: A radio frequency chip body, the radio frequency chip body including a semiconductor device, the semiconductor device being located in a device layer of an SOI wafer substrate; A waterproof ring, which is arranged around the radio frequency chip body; A chip isolation ring, which is arranged around the RF chip body and located on the periphery of the waterproof ring; At least two sealing rings: a first sealing ring and a second sealing ring, wherein the sealing rings are arranged around the RF chip body and are located outside the chip isolation ring; at least one stress relief ring, wherein an air gap is provided in the stress relief ring; The stress relief ring is arranged around the sealing ring; wherein a cutting belt is arranged on the periphery of the stress relief ring.

2. The radio frequency chip according to claim 1, characterized in that: The stress relief ring includes a first isolation groove and a first dielectric layer deposited in the first isolation groove; the waterproof ring includes a second isolation groove and a second dielectric layer deposited in the second isolation groove; the air gap is formed in the first dielectric layer and the second dielectric layer.

3. The radio frequency chip according to claim 2, characterized in that: The aspect ratio of the first isolation trench is greater than or equal to 8.

4. The radio frequency chip according to claim 3, characterized in that: The first dielectric layer and the second dielectric layer both include: a first silicon oxide dielectric layer deposited on the inner wall of the first isolation trench / the second isolation trench; a silicon nitride dielectric layer, deposited on the first silicon oxide dielectric layer; A second silicon oxide dielectric layer is deposited on the silicon nitride dielectric layer and fills the first isolation trench / the second isolation trench; wherein the air gap is formed in the second silicon oxide dielectric layer.

5. The radio frequency chip according to claim 4, characterized in that: The thickness of the first silicon oxide dielectric layer is 50-300 angstroms.

6. The radio frequency chip according to claim 5, characterized in that: The thickness of the silicon nitride dielectric layer is 100-1000 angstroms.

7. The radio frequency chip according to any one of claims 1 to 6, characterized in that: The number of the stress relief rings is at least three; and the stress relief rings are arranged between the chip isolation ring and the cutting tape.

8. The radio frequency chip according to claim 7, characterized in that: The three stress relief rings are respectively arranged between the chip isolation ring and the first sealing ring, between the first sealing ring and the second sealing ring, and between the second sealing ring and the dicing tape.

9. The radio frequency chip according to claim 8, characterized in that: There are two or more stress relief rings at the same position.

10. The radio frequency chip according to any one of claims 1 to 9, characterized in that: The depths of the waterproof ring and the stress relief ring penetrate the device layer of the SOI wafer substrate to the buried oxide layer of the SOI wafer substrate.

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