Detection control circuit, battery management circuit and battery pack

Abstract

The utility model provides a detection control circuit, a battery management circuit and a battery pack. The detection control circuit is used on a sampling line of a battery cell and connected between a positive electrode or a negative electrode of the battery cell and a sampling resistor on the sampling line, the detection control circuit comprises a resistor, a switching tube, an operational amplifier circuit and a control circuit, and when a first voltage value is larger than a preset value, the control circuit controls the switching tube to be switched off; after the switch tube is switched off for a preset time, the control circuit controls the switch tube to be switched on again; when the second voltage value is larger than the preset value, the control circuit controls the switch tube to be disconnected again, and when the second voltage value is smaller than or equal to the preset value, the control circuit controls the switch tube to be kept on. Whether abnormal surge current or short-circuit large current is generated on the sampling line is actively monitored, meanwhile, on-off control over the sampling line is achieved, the sampling line is cut off when the abnormal surge current or the short-circuit large current is generated, and the problem of device damage such as abnormal fusing of a fuse is prevented.

Description

Technical Field

[0001] The present application relates to the field of battery technology, and in particular to a detection control circuit, a battery management circuit, and a battery pack. Background Art

[0002] Current battery management systems generally use two protectors. The first protector, which can be any overcurrent or overvoltage protection element, protects the sampling cell. The second protector, typically a fuse, protects the battery pack. In other words, the first protector is located between the second protector and the sampling cell. If the first protector fails, the sampling circuit it connects to is disconnected, and the existing sampling circuit function ceases to operate properly. Similarly, if the second protector fails, the sampling circuit is also disconnected, and the existing sampling circuit function ceases to operate properly. In both cases, damage disrupts the existing sampling circuit function, leading to product failure. Furthermore, because the sampling circuit is disconnected regardless of the type of damage, it is impossible to determine whether the sampling circuit is damaged by a short circuit, overcurrent, or surge. Utility Model Content

[0003] In view of this, the present application provides at least one detection control circuit, a battery management circuit and a battery pack.

[0004] The present application provides a detection control circuit, which is used on a sampling line of a battery cell and is connected between the positive or negative electrode of the battery cell and a sampling resistor on the sampling line. The circuit includes: a resistor, one end of which is connected to the positive or negative electrode of the battery cell; a switch tube, a first end of which is connected to the other end of the resistor, and a second end of which is connected to the sampling resistor; an operational amplifier circuit, a first input end of which is connected to one end of the resistor, and a second input end of which is connected to the other end of the resistor; and a control circuit connected to the control end of the switch tube. The control circuit controls the switch tube to be turned on so as to obtain a first voltage value on the sampling line through detection by the resistor and the operational amplifier circuit. When the first voltage value is greater than a preset value, the control circuit controls the switch tube to be turned off. After the switch tube is turned off for a preset time, the control circuit controls the switch tube to be turned on again so as to obtain a second voltage value on the sampling line through re-detection by the resistor and the operational amplifier circuit. When the second voltage value is greater than the preset value, the control circuit controls the switch tube to be turned off again. When the second voltage value is less than or equal to the preset value, the control circuit controls the switch tube to remain turned on.

[0005] In the above scheme, the detection control circuit includes a resistor, a switch tube, an operational amplifier circuit and a control circuit. When the first voltage value is greater than a preset value, the control circuit controls the switch tube to be disconnected; after the switch tube is disconnected for a preset time, the control circuit controls the switch tube to be turned on again, so as to re-detect and obtain the second voltage value on the sampling line through the resistor and the operational amplifier circuit; when the second voltage value is greater than the preset value, the control circuit controls the switch tube to be disconnected again, and when the second voltage value is less than or equal to the preset value, the control circuit controls the switch tube to remain turned on, thereby actively monitoring whether there is abnormal surge current or short-circuit high current generated on the sampling line, and at the same time realizing on-off control of the sampling line, cutting off the sampling line when abnormal surge current or short-circuit high current is generated, thereby preventing device damage such as abnormal fuse blowing.

[0006] In some embodiments, the control circuit includes a single-chip microcomputer; the detection control circuit also includes an analog-to-digital converter, and the analog-to-digital converter is connected between the output end of the operational amplifier circuit and the single-chip microcomputer.

[0007] In the above scheme, the detection control circuit is effectively implemented through the single-chip microcomputer and analog-to-digital converter in the control circuit, and active monitoring is achieved to see whether there is abnormal surge current or short-circuit high current on the sampling line. At the same time, the on-off control of the sampling line is achieved, and the sampling line is cut off when abnormal surge current or short-circuit high current occurs, thereby preventing device damage such as abnormal fuse blowing.

[0008] In some embodiments, the operational amplifier circuit includes a first operational amplifier resistor, a second operational amplifier resistor, a third operational amplifier resistor, a fourth operational amplifier resistor and an operational amplifier; wherein, one end of the first operational amplifier resistor is connected to the other end of the resistor as the second input end, and the other end is connected to the inverting input end of the operational amplifier and connected to the output end of the operational amplifier through the third operational amplifier resistor; one end of the second operational amplifier resistor is connected to one end of the resistor as the first input end, and the other end is connected to the same-direction input end of the operational amplifier and grounded through the fourth operational amplifier resistor; the output end of the operational amplifier serves as the output end of the operational amplifier circuit.

[0009] In the above scheme, the voltage difference across the resistor is obtained by connecting the first operational amplifier resistor, the second operational amplifier resistor, the third operational amplifier resistor, the fourth operational amplifier resistor and the operational amplifier in the operational amplifier circuit, so as to effectively realize the detection control circuit, and then realize active monitoring of whether there is abnormal surge current or short-circuit high current generated on the sampling line, and at the same time realize the on-off control of the sampling line, cutting off the sampling line when abnormal surge current or short-circuit high current is generated, and preventing device damage such as abnormal melting of the fuse.

[0010] In some embodiments, the resistance values ​​of the first op amp resistor, the second op amp resistor, the third op amp resistor, and the fourth op amp resistor are the same.

[0011] In the above scheme, by setting the resistance values ​​of the first operational amplifier resistor, the second operational amplifier resistor, the third operational amplifier resistor, and the fourth operational amplifier resistor in the operational amplifier circuit to be the same, the output of the operational amplifier, that is, the voltage difference across the resistor, is effectively implemented to detect the control circuit, thereby actively monitoring whether there is abnormal surge current or short-circuit high current generated on the sampling line, and at the same time realizing the on-off control of the sampling line, cutting off the sampling line when abnormal surge current or short-circuit high current is generated, and preventing device damage such as abnormal melting of the fuse.

[0012] The present application also provides a battery management circuit for at least one battery cell, comprising at least two detection control circuits, wherein each detection control circuit is connected between the positive electrode or negative electrode of the corresponding battery cell in at least one battery cell and the sampling resistor on the sampling line of the corresponding battery cell.

[0013] In the above scheme, the battery management circuit includes at least two detection control circuits. By connecting each detection control circuit between the positive or negative pole of the corresponding battery cell in at least one battery cell and the sampling resistor on the sampling line of the corresponding battery cell, active monitoring of whether abnormal surge current or short-circuit high current is generated on the sampling line is achieved, and at the same time, on-off control of the sampling line is achieved. When abnormal surge current or short-circuit high current is generated, the sampling line is cut off to prevent device damage such as abnormal fuse blowing.

[0014] In some embodiments, the battery management circuit further includes at least two fuses, each fuse being connected between the positive electrode or the negative electrode of a corresponding battery cell in at least one battery cell and the corresponding detection control circuit.

[0015] In the above scheme, by connecting each of the at least two fuses between the positive or negative pole of the corresponding battery cell in at least one battery cell and the corresponding detection control circuit, the battery management circuit is effectively realized, thereby actively monitoring whether there is abnormal surge current or short-circuit high current generated on the sampling line, and at the same time realizing the on-off control of the sampling line, cutting off the sampling line when abnormal surge current or short-circuit high current is generated, and preventing device damage such as abnormal fuse melting.

[0016] In some embodiments, at least two fuses are arranged on the first circuit board, and the sampling resistor is arranged on the second circuit board; at least two detection control circuits are arranged on the first circuit board, or at least two detection control circuits are arranged on the second circuit board, or at least two detection control circuits are arranged on a third circuit board different from the first circuit board and the second circuit board.

[0017] In the above scheme, the detection control circuit is arranged on the first circuit board where the fuse is located, or the detection control circuit is arranged on the second circuit board where the sampling resistor is located, or the detection control circuit is arranged on a third circuit board different from the first circuit board and the second circuit board. The detection control circuit is used to actively monitor whether there is abnormal surge current or short-circuit high current generated on the sampling line, and at the same time, the on-off control of the sampling line is realized. When abnormal surge current or short-circuit high current is generated, the sampling line is cut off to prevent damage to the components on the first circuit board and the second circuit board.

[0018] The present application also provides a battery pack, comprising N battery cells, a sampling circuit, and a battery management circuit; the N battery cells are connected in series, and the battery management circuit includes M detection control circuits in the above embodiments; wherein N and M are both positive integers, and N is greater than or equal to 1, M=N+1, and each detection control circuit is connected between the positive or negative pole of a battery cell and the sampling resistor of the sampling circuit.

[0019] In the above scheme, the battery pack includes N battery cells, a sampling circuit and a battery management circuit; the N battery cells are connected in series in sequence, and the battery management circuit includes M detection control circuits, each detection control circuit is connected between the positive or negative pole of a battery cell and the sampling resistor of the sampling circuit. The detection control circuit is used to actively monitor whether there is abnormal surge current or short-circuit high current generated on the sampling line, and at the same time realize the on-off control of the sampling line. When abnormal surge current or short-circuit high current is generated, the sampling line is cut off to prevent abnormal fuse melting and other device damage problems.

[0020] In some embodiments, the number of control circuits in the M detection control circuits is 1, and the number of resistors, switch tubes, and operational amplifier circuits are all M.

[0021] In the above scheme, the M detection control circuits include M resistors, M switching tubes, M operational amplifier circuits and 1 control circuit. The control circuit can control the conduction and shutdown of the M switching tubes based on the voltage values ​​across the M resistors, thereby actively monitoring whether there is abnormal surge current or short-circuit high current generated on the sampling line, and at the same time realize the on-off control of the sampling line, cutting off the sampling line when abnormal surge current or short-circuit high current is generated, to prevent abnormal fuse melting and other device damage problems.

[0022] In some embodiments, the M detection control circuits also include a multiplexing circuit; the number of control circuits and operational amplifier circuits in the M detection control circuits is 1, and the number of resistors and switching tubes is M, where the two ends of the M resistors are connected to the operational amplifier circuit through the multiplexing circuit; the multiplexing circuit is also connected to the control circuit.

[0023] In the above scheme, by using a multiplexing circuit in the detection control circuit, the use of operational amplifiers is reduced, and the design is simplified. Then, the detection control circuit can be used to actively monitor whether there is abnormal surge current or short-circuit high current generated on the sampling line, and at the same time, the on-off control of the sampling line is realized. When abnormal surge current or short-circuit high current is generated, the sampling line is cut off to prevent abnormal fuse blowing and other device damage problems.

[0024] In some embodiments, the multiplexing circuit includes a first multiplexer and a second multiplexer, wherein one end of the M resistors is connected to the first input end of the operational amplifier circuit through the first multiplexer, and the other end is connected to the second input end of the operational amplifier circuit through the second multiplexer; the first multiplexer is also connected to the control circuit, and the second multiplexer is also connected to the control circuit.

[0025] In the above scheme, the multiplexing circuit includes two multiplexers, which reduces the use of operational amplifiers and simplifies the design. Then, through the detection control circuit, it is possible to actively monitor whether there is abnormal surge current or short-circuit high current on the sampling line, and at the same time realize the on-off control of the sampling line. When abnormal surge current or short-circuit high current occurs, the sampling line is cut off to prevent abnormal fuse melting and other device damage problems.

[0026] In some embodiments, the battery management circuit includes the M+1th detection control circuit in the above embodiment, and the M+1th detection control circuit is connected between the positive electrodes of the N battery cells connected in series and the power supply end of the sampling circuit.

[0027] In the above scheme, the M+1th detection control circuit in the battery management circuit is connected between the positive poles of the N battery cells connected in series and the power supply end of the sampling circuit to realize circuit protection. The detection control circuit actively monitors whether there is abnormal surge current or short-circuit high current on the sampling line, and realizes the on-off control of the sampling line at the same time. When abnormal surge current or short-circuit high current occurs, the sampling line is cut off to prevent abnormal fuse blowing and other device damage problems.

[0028] In some embodiments, the battery management circuit further includes M fuses or M+1 fuses, each fuse being connected between the positive electrode or the negative electrode of the corresponding battery cell and the corresponding detection control circuit.

[0029] In the above scheme, the battery management circuit includes M fuses or M+1 fuses, each fuse is connected between the positive or negative pole of the corresponding battery cell and the corresponding detection control circuit to achieve battery cell protection. The detection control circuit is used to actively monitor whether there is abnormal surge current or short-circuit high current generated on the sampling line, and at the same time realize the on-off control of the sampling line. When abnormal surge current or short-circuit high current is generated, the sampling line is cut off to prevent abnormal fuse melting and other device damage problems.

[0030] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The drawings herein are incorporated into and constitute a part of the specification. These drawings illustrate embodiments consistent with the present application and, together with the specification, are used to illustrate the technical solutions of the present application.

[0032] Figure 1 This is a circuit diagram of the detection control circuit of some embodiments of the present application Figure 1 ;

[0033] Figure 2 This is a circuit diagram of the detection control circuit of some embodiments of the present application Figure 2 ;

[0034] Figure 3 This is a circuit diagram of the detection control circuit of some embodiments of the present application Figure 3 ;

[0035] Figure 4 This is a circuit diagram of the battery management circuit of some embodiments of the present application Figure 1 ;

[0036] Figure 5 This is a circuit diagram of the battery management circuit of some embodiments of the present application Figure 2 ;

[0037] Figure 6 This is a schematic diagram of the structure of the first circuit board and the second circuit board in some embodiments of the present application. Figure 1 ;

[0038] Figure 7 This is a schematic diagram of the structure of the first circuit board and the second circuit board in some embodiments of the present application. Figure 2 ;

[0039] Figure 8 This is a schematic diagram of the structure of the first circuit board and the second circuit board in some embodiments of the present application. Figure 3 ;

[0040] Figure 9 is a schematic structural diagram of a first circuit board, a second circuit board, and a third circuit board in some embodiments of the present application;

[0041] Figure 10 This is a circuit diagram of the battery pack of some embodiments of the present application Figure 1 ;

[0042] Figure 11 This is a circuit diagram of the battery pack of some embodiments of the present application Figure 2 ;

[0043] Figure 12 This is a circuit diagram of the detection control circuit of some embodiments of the present application Figure 4 ;

[0044] Figure 13 This is a circuit diagram of the battery pack of some embodiments of the present application Figure 3 ;

[0045] Figure 14 This is a circuit diagram of the battery pack of some embodiments of the present application Figure 4 ;

[0046] Figure 15 This is a circuit diagram of the battery pack of some embodiments of the present application Figure 5 ;

[0047] Figure 16 This is a circuit diagram of the battery pack of some embodiments of the present application Figure 6 ;

[0048] Figure 17 This is a circuit diagram of the battery pack of some embodiments of the present application Figure 7 ;

[0049] Figure 18 This is a circuit diagram of the battery pack of some embodiments of the present application Figure 8 ;

[0050] Figure 19 This is a circuit diagram of the battery pack of some embodiments of the present application Figure 9 . DETAILED DESCRIPTION

[0051] The following describes the embodiments of the present application in detail with reference to the accompanying drawings.

[0052] In the following description, for the purpose of explanation rather than limitation, specific details such as specific system structures, interfaces, and technologies are provided to facilitate a thorough understanding of the present application.

[0053] The term "and / or" in this article is simply a description of the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent three situations: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects are in an "or" relationship. In addition, "many" in this article means two or more than two. In addition, the term "at least one" in this article means any combination of at least two of any one or more of a plurality of. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.

[0054] Currently, in battery management circuits, damage to either protector will cause the original sampling circuit to malfunction, leading to product failure. Furthermore, because the sampling circuit is disconnected regardless of the type of damage, it is impossible to determine whether the sampling circuit is damaged by a short circuit, overcurrent, or surge.

[0055] To this end, in the above scheme, the detection control circuit includes a resistor, a switch tube, an operational amplifier circuit and a control circuit. When the first voltage value is greater than a preset value, the control circuit controls the switch tube to be disconnected; after the switch tube is disconnected for a preset time, the control circuit controls the switch tube to be turned on again, so as to re-detect and obtain the second voltage value on the sampling line through the resistor and the operational amplifier circuit; when the second voltage value is greater than the preset value, the control circuit controls the switch tube to be disconnected again, and when the second voltage value is less than or equal to the preset value, the control circuit controls the switch tube to remain turned on, thereby actively monitoring whether there is abnormal surge current or short-circuit high current generated on the sampling line, and at the same time realizing on-off control of the sampling line, cutting off the sampling line when abnormal surge current or short-circuit high current is generated, thereby preventing device damage such as abnormal fuse blowing.

[0056] See also Figure 1 , Figure 1 This is a circuit diagram of the detection control circuit of some embodiments of the present application Figure 1 .like Figure 1 As shown, a detection control circuit 10 is used on the sampling line of the battery cell 20, connected between the positive electrode or negative electrode of the battery cell 20 and the sampling resistor 40 on the sampling line, including: a resistor 11, one end of which is connected to the positive electrode or negative electrode of the battery cell 20; a switch tube 12, a first end of which is connected to the other end of the resistor 11, and a second end of which is connected to the sampling resistor 40; an operational amplifier circuit 13, a first input end of which is connected to one end of the resistor 11, and a second input end of which is connected to the other end of the resistor 11; a control circuit 14, connected to the output end of the operational amplifier circuit 13 and the control end of the switch tube 12; wherein the control circuit 14 controls The control circuit 14 controls the switch tube 12 to be turned on, so as to detect a first voltage value on the sampling line through the resistor 11 and the operational amplifier circuit 13; when the first voltage value is greater than a preset value, the control circuit 14 controls the switch tube 12 to be turned off; after the switch tube 12 is turned off for a preset time, the control circuit 14 controls the switch tube 12 to be turned on again, so as to re-detect a second voltage value on the sampling line through the resistor 11 and the operational amplifier circuit 13; when the second voltage value is greater than the preset value, the control circuit 14 controls the switch tube 12 to be turned off again; when the second voltage value is less than or equal to the preset value, the control circuit 14 controls the switch tube 12 to remain turned on.

[0057] The line between the battery cell 20 and the sampling resistor 40 can be called the sampling line of the battery cell 20. In addition to the detection control circuit 10, the sampling line may also include a fuse 30. The sampling resistor 40 may also be connected to a sampling chip 60 to implement the sampling circuit function. The sampling resistor 40 may also be connected in parallel with an equalizing resistor 50 to connect to the sampling chip 60 to implement the equalization function of the sampling line. The resistor 11 can be a small precision resistor, and its resistance can be selected according to design requirements. For example, its resistance is 500mΩ. The switch transistor 12 can be an NMOS (N-Metal-Oxide-Semiconductor) transistor or a PMOS (P-Metal-Oxide-Semiconductor) transistor. In the example where the switch transistor 12 is an NMOS transistor, the first terminal of the switch transistor 12 is the drain of the NMOS transistor, the second terminal of the switch transistor 12 is the source of the NMOS transistor, and the control terminal of the switch transistor 12 is the gate of the NMOS transistor. The preset value may be the voltage value of the sampling line when the balancing function is turned on, for example, 0.05 V. The preset time may be designed according to actual needs, for example, 10 seconds.

[0058] When the control circuit 14 controls the switch tube 12 to be turned on, the current of the battery cell 20 flows through the resistor 11 on the sampling line, thereby obtaining a voltage value across the resistor 11. After amplification by the operational amplifier circuit 13, an amplified voltage value is obtained, which is used to represent the voltage value on the sampling line.

[0059] The control circuit 14 transmits high and low levels to the control terminal of the switch tube 12, causing the gate voltage of the switch tube 12 to change, thereby controlling the conduction or disconnection of the switch tube 12. On the sampling line, under normal operating conditions, the control circuit 14 always outputs a high level, the switch tube 12 remains on, and the current of the battery cell 20 flows through the resistor 11, thereby obtaining a voltage value across the resistor 11. After amplification by the operational amplifier circuit 13, an amplified voltage value, i.e., a first voltage value, is obtained. The control circuit 14 determines the relationship between the first voltage value and a preset value. When the first voltage value is greater than the preset value, the control circuit 14 transmits a low level to the control terminal of the switch tube 12, causing the voltage at the control terminal of the switch tube 12 to change from high to low. The switch tube 12 is disconnected, and the sampling line is cut off, protecting all components on the sampling line, such as the fuse 30, the sampling resistor 40, and the sampling chip 60, from damage by the current. After a preset time, for example, 10 seconds, after the switch tube 12 is disconnected, the control circuit 14 transmits a high level to the switch tube 12, causing the gate voltage of the switch tube 12 to change from low to high, the switch tube 12 is turned on again, and the sampling line is restored. At this time, the current of the battery cell 20 flows through the resistor 11, so that the voltage value across the resistor 11 can be obtained. After amplification by the operational amplifier circuit 13, another amplified voltage value, i.e., a second voltage value, is obtained. The control circuit 14 determines the relationship between the second voltage value and the preset value. When the second voltage value is greater than the preset value, it indicates that there may be an abnormal short circuit point in the sampling line, resulting in a continuous abnormal current. At this time, the control circuit 14 transmits a low level to the switch tube 12, causing the gate voltage of the switch tube 12 to change from high to low, the switch tube 12 is disconnected again, and the sampling line is cut off. When the second voltage value is less than the preset value, it indicates that the abnormal current corresponding to the first voltage value before the sampling line may be a transient surge current. At this time, the control circuit 14 transmits a high level to the switch tube 12, causing the gate voltage of the switch tube 12 to change from low to high. The switch tube 12 remains turned on, the sampling line is restored, and normal operation continues.

[0060] In the above scheme, the detection control circuit 10 includes a resistor 11, a switch tube 12, an operational amplifier circuit 13 and a control circuit 14. When the first voltage value is greater than a preset value, the control circuit 14 controls the switch tube 12 to be disconnected; after the switch tube 12 is disconnected for a preset time, the control circuit 14 controls the switch tube 12 to be turned on again, so as to re-detect and obtain a second voltage value on the sampling line through the resistor 11 and the operational amplifier circuit 13; when the second voltage value is greater than the preset value, the control circuit 14 controls the switch tube 12 to be turned off again, and when the second voltage value is less than or equal to the preset value, the control circuit 14 controls the switch tube 12 to remain turned on, thereby actively monitoring whether there is an abnormal surge current or a short-circuit high current generated on the sampling line, and at the same time realizing the on-off control of the sampling line, cutting off the sampling line when an abnormal surge current or a short-circuit high current is generated, thereby preventing device damage such as abnormal melting of the fuse 30.

[0061] In some embodiments, see Figure 2 , Figure 2 This is a circuit diagram of the detection control circuit of some embodiments of the present application Figure 2 .like Figure 2 As shown, the control circuit 14 includes a single-chip microcomputer 141 ; the detection control circuit 10 further includes an analog-to-digital converter 15 , which is connected between the output end of the operational amplifier circuit 13 and the single-chip microcomputer 141 .

[0062] The analog-to-digital converter 15 can convert the analog voltage value at the output of the operational amplifier circuit 13 into a digital value and transmit it to the microcontroller 141. In the microcontroller 141, it can be set to determine that an abnormal surge current or a short-circuit current is generated on the sampling line when the voltage value of the sampling line is greater than a preset value, for example, greater than 0.05V. The microcontroller 141 can then control the conduction and disconnection of the switch tube 12 based on the received digital value.

[0063] In the above scheme, the single-chip microcomputer 141 and the analog-to-digital converter 15 in the control circuit 14 effectively realize the detection control circuit 10, realize active monitoring of whether there is abnormal surge current or short-circuit high current generated on the sampling line, and realize on-off control of the sampling line at the same time, cut off the sampling line when abnormal surge current or short-circuit high current is generated, and prevent the fuse 30 from abnormally melting and other device damage problems.

[0064] In some embodiments, see Figure 3 , Figure 3 This is a circuit diagram of the detection control circuit of some embodiments of the present application Figure 3 .like Figure 3 As shown, the operational amplifier circuit 13 includes a first operational amplifier resistor 131, a second operational amplifier resistor 132, a third operational amplifier resistor 133, a fourth operational amplifier resistor 134 and an operational amplifier 135; wherein, one end of the first operational amplifier resistor 131 is connected to the other end of the resistor 11 as a second input end, and the other end is connected to the inverting input end of the operational amplifier 135 and connected to the output end of the operational amplifier 135 through the third operational amplifier resistor 133; one end of the second operational amplifier resistor 132 is connected to one end of the resistor 11 as a first input end, and the other end is connected to the non-inverting input end of the operational amplifier 135 and grounded through the fourth operational amplifier resistor 134; the output end of the operational amplifier 135 serves as the output end of the operational amplifier circuit 13.

[0065] One end of the first operational amplifier resistor 131 is connected to the other end of the resistor 11 as the second input end of the operational amplifier circuit 13. The other end of the first operational amplifier resistor 131 is connected to the inverting input end of the operational amplifier 135 and is connected in parallel to the output end of the operational amplifier 135 through the third operational amplifier resistor 133. One end of the second operational amplifier resistor 132 is connected to one end of the resistor 11 as the first output end of the operational amplifier circuit 13. The other end of the second operational amplifier resistor 132 is connected to the non-inverting input end of the operational amplifier 135 and is connected to ground in parallel with the fourth operational amplifier resistor 134. The output end of the operational amplifier 135 is the output end of the operational amplifier circuit 13.

[0066] The first operational amplifier resistor 131, the second operational amplifier resistor 132, the third operational amplifier resistor 133, and the fourth operational amplifier resistor 134 constitute an external feedback resistor network of the operational amplifier 135. The closed-loop voltage amplification factor of the operational amplifier 135 can be determined by the ratio of the external feedback resistor network. That is, the operational amplifier 135 can adjust the output voltage of the operational amplifier 135 based on the settings of the first operational amplifier resistor 131, the second operational amplifier resistor 132, the third operational amplifier resistor 133, and the fourth operational amplifier resistor 134. For example, the voltage value at the end of the resistor 11 connected to the first operational amplifier resistor 131 is recorded as V1, the voltage value at the end of the resistor 11 connected to the second operational amplifier resistor 132 is recorded as V2, and the output voltage of the operational amplifier 135 is recorded as V out1 The resistance values ​​of the first operational amplifier resistor 131, the second operational amplifier resistor 132, the third operational amplifier resistor 133, and the fourth operational amplifier resistor 134 are respectively denoted as R1, R2, R3, and R4. At this time, the voltage at the output terminal of the operational amplifier 135 is:

[0067]

[0068] When R1=R2, R3=R4, the output V out1 for:

[0069]

[0070] The ratio between R3 and R1 is called the gain of the operational amplifier 135. That is, the voltage difference across the resistor can be multiplied by the ratio between R3 and R1 to obtain the amplified voltage difference across the resistor. The resistance values ​​of R3 and R1 can be selected according to actual design requirements.

[0071] In the above scheme, the voltage difference across the resistor 11 is obtained by connecting the first operational amplifier resistor 131, the second operational amplifier resistor 132, the third operational amplifier resistor 133, the fourth operational amplifier resistor 134, and the operational amplifier 135 in the operational amplifier circuit 13, so as to effectively implement the detection control circuit 10, and then actively monitor whether there is abnormal surge current or short-circuit high current generated on the sampling line, and at the same time realize the on-off control of the sampling line, cutting off the sampling line when abnormal surge current or short-circuit high current is generated, thereby preventing device damage such as abnormal melting of the fuse 30.

[0072] In some embodiments, the first operational amplifier resistor 131 , the second operational amplifier resistor 132 , the third operational amplifier resistor 133 , and the fourth operational amplifier resistor 134 have the same resistance value.

[0073] In some examples, the voltage value at the end of the resistor 11 connected to the first op amp resistor 131 is recorded as V1, the voltage value at the end of the resistor 11 connected to the second op amp resistor 132 is recorded as V2, the voltage value at the output end of the operational amplifier 135 is recorded as Vout1, and the resistance values ​​of the first op amp resistor 131, the second op amp resistor 132, the third op amp resistor 133, and the fourth op amp resistor 134 are recorded as R1, R2, R3, and R4, respectively. At this time, the voltage at the output end of the operational amplifier 135 is:

[0074]

[0075] The resistance values ​​of the first operational amplifier resistor 131, the second operational amplifier resistor 132, the third operational amplifier resistor 133, and the fourth operational amplifier resistor 134 are the same, that is, R1=R2=R3=R4. At this time, the output V out1 for:

[0076]

[0077] It can be understood that when the resistance values ​​of the first operational amplifier resistor 131, the second operational amplifier resistor 132, the third operational amplifier resistor 133, and the fourth operational amplifier resistor 134 in the operational amplifier circuit 13 are the same, the voltage value of the output end of the operational amplifier 135 is the voltage difference across the resistor 11.

[0078] In the above scheme, by setting the resistance values ​​of the first operational amplifier resistor 131, the second operational amplifier resistor 132, the third operational amplifier resistor 133, and the fourth operational amplifier resistor 134 in the operational amplifier circuit 13 to be the same, the output of the operational amplifier 135, i.e., the voltage difference across the resistor 11, is effectively implemented to detect the control circuit 10, thereby actively monitoring whether there is an abnormal surge current or a short-circuit high current generated on the sampling line, and at the same time realizing the on-off control of the sampling line, cutting off the sampling line when an abnormal surge current or a short-circuit high current is generated, thereby preventing damage to the device such as abnormal melting of the fuse 30.

[0079] See also Figure 4-Figure 5 , Figure 4 This is a circuit diagram of the battery management circuit of some embodiments of the present application Figure 1 ,like Figure 4-Figure 5 As shown, the battery management circuit 400 is used for at least one battery cell 20 and includes at least two of the above-mentioned detection control circuits 10, wherein each detection control circuit 10 is connected between the positive electrode or negative electrode of the corresponding battery cell 20 in at least one battery cell 20 and the sampling resistor 40 on the sampling line of the corresponding battery cell 20.

[0080] Each detection control circuit 10 is connected between the positive electrode or negative electrode of the corresponding battery cell 20 in at least one battery cell 20 and the sampling resistor 40 on the sampling line of the corresponding battery cell 20. When the number of battery cells 20 is 1, as shown in FIG. Figure 4 As shown, the battery management circuit 400 is used for a battery cell 20, and the battery management circuit 400 includes two detection control circuits 10. In some examples, the battery management circuit 400 is used for the battery cell C1 (20), and the two detection control circuits 10 include a detection control circuit D1 and a detection control circuit D2, wherein the first end of the detection control circuit D1 can be connected to the positive electrode of the battery cell C1, and the second end of the detection control circuit D1 is connected to the sampling resistor 40 on the sampling line S1 corresponding to the positive electrode of the battery cell C1, and the voltage value on the sampling line S1 can be obtained to protect the functional devices on the sampling line S1 from being damaged by the current; the first end of the detection control circuit D2 can be connected to the negative electrode of the battery cell C1, and the second end of the detection control circuit D2 is connected to the sampling resistor 40 on the sampling line S2 corresponding to the negative electrode of the battery cell C1, and the voltage value on the sampling line S2 can be obtained to protect the functional devices on the sampling line S2 from being damaged by the current.

[0081] Alternatively, when the number of cells 20 is ≥ 2, if Figure 5As shown, the battery management circuit 400 is used for at least two battery cells 20 , and the battery management circuit 400 includes at least three detection control circuits 10 . For example, at least two battery cells 20 include battery cell C1 and battery cell C2, the battery management circuit 400 is used for battery cell C1 and battery cell C2, and at least three detection control circuits 10 include detection control circuit D1, detection control circuit D2 and detection control circuit D3, wherein the positive electrode of battery cell C1 can be connected to the first end of detection control circuit D1, and the second end of detection control circuit D1 is connected to the sampling resistor 40 on the sampling line S1 corresponding to the positive electrode of battery cell C1; the negative electrode of battery cell C1 can be connected to the first end of detection control circuit D2, and the second end of detection control circuit D2 is connected to the sampling resistor 40 on the sampling line S2 corresponding to the negative electrode of battery cell C1; the positive electrode of battery cell C2 can be connected to the first end of detection control circuit D2, and the second end of detection control circuit D2 is connected to the sampling resistor 40 on the sampling line S2 corresponding to the positive electrode of battery cell C2; the negative electrode of battery cell C2 can be connected to the first end of detection control circuit D3, and the second end of detection control circuit D3 is connected to the sampling resistor 40 on the sampling line S3 corresponding to the negative electrode of battery cell C2.

[0082] It can be understood that each detection control circuit 10 is connected between the positive or negative pole of the corresponding battery cell 20 in at least one battery cell 20 and the sampling resistor 40 on the sampling line of the corresponding battery cell 20, that is, one detection control circuit 10 can be connected between the positive or negative pole of the corresponding battery cell 20 in one battery cell 20 and the sampling resistor 40 on the sampling line of the corresponding battery cell 20, or one detection control circuit 10 can be connected between the positive or negative pole of the corresponding battery cell 20 in two battery cells 20 and the sampling resistor 40 on the sampling line of the corresponding battery cell 20.

[0083] In the above scheme, the battery management circuit 400 includes at least two detection control circuits 10. By connecting each detection control circuit 10 between the positive or negative pole of the corresponding battery cell 20 in at least one battery cell 20 and the sampling resistor 40 on the sampling line of the corresponding battery cell 20, active monitoring of whether abnormal surge current or short-circuit high current is generated on the sampling line is achieved, and at the same time, on-off control of the sampling line is achieved. When abnormal surge current or short-circuit high current is generated, the sampling line is cut off to prevent abnormal fuse blowing and other device damage problems.

[0084] Please continue reading Figure 4-Figure 5 The battery management circuit 400 further includes at least two fuses 30 , each fuse 30 being connected between the positive electrode or negative electrode of a corresponding battery cell 20 in at least one battery cell 20 and the corresponding detection control circuit 10 .

[0085] Among them, the fuse 30 is used to protect the battery cell 20 and the components on the sampling line. When the current exceeds the rated value, the built-in alloy components are melted by Joule heat to protect the circuit and prevent component damage. In the battery management circuit 400, at least two fuses 30 are included, and each fuse 30 is connected to the positive electrode or negative electrode of the corresponding battery cell 20 in at least one battery cell 20.

[0086] When the number of battery cells 20 is 1, Figure 4 As shown, the battery management circuit 400 is used for one battery cell 20 and includes two fuses 30. For example, the battery management circuit 400 is used for the battery cell C1 (20), the two detection control circuits 10 include the detection control circuit D1 and the detection control circuit D2, and the two fuses 30 include the fuse F1 and the fuse F2, wherein the fuse F1 can connect the positive electrode of the battery cell C1 with the detection control circuit D1, and the fuse F2 can connect the negative electrode of the battery cell C1 with the detection control circuit D2. When the number of battery cells 20 is ≥2, as Figure 5 As shown, the battery management circuit 400 is used for at least two battery cells 20 and includes at least three fuses 30. For example, the at least two battery cells 20 include a battery cell C1 and a battery cell C2, the battery management circuit 400 is used for the battery cells C1 and C2, the at least two detection control circuits 10 include a detection control circuit D1, a detection control circuit D2, and a detection control circuit D3, and the at least two fuses 30 include a fuse F1, a fuse F2, and a fuse F3. Fuse F1 can connect the positive electrode of battery cell C1 to the detection control circuit D1; fuse F2 can connect the negative electrode of battery cell C1 to the detection control circuit D2, and to the positive electrode of battery cell C2; fuse F3 can connect the negative electrode of battery cell C2 to the detection control circuit D3.

[0087] In the above scheme, by connecting each of the at least two fuses 30 between the positive pole or negative pole of the corresponding battery cell 20 in at least one battery cell 20 and the corresponding detection control circuit 10, the battery management circuit 400 is effectively realized, thereby actively monitoring whether there is abnormal surge current or short-circuit high current generated on the sampling line, and at the same time realizing the on-off control of the sampling line, cutting off the sampling line when abnormal surge current or short-circuit high current is generated, and preventing device damage such as abnormal melting of the fuse 30.

[0088] In some embodiments, see Figure 6-Figure 9 At least two fuses 30 are arranged on the first circuit board 600, and the sampling resistor 40 is arranged on the second circuit board 700; at least two detection control circuits 10 are arranged on the first circuit board 600, or at least two detection control circuits 10 are arranged on the second circuit board 700, or at least two detection control circuits 10 are arranged on a third circuit board 800 different from the first circuit board 600 and the second circuit board 700.

[0089] like Figure 6 As shown, at least two fuses 30 are provided on the first circuit board 600, and the sampling resistor 40 is provided on the second circuit board 700. The first circuit board 600 and the second circuit board 700 can be connected through a sampling line, that is, each fuse 30 is connected to the sampling resistor 40 on the sampling line, and a detection control circuit 10 is further connected between each fuse 30 and the corresponding connected sampling resistor 40. Among them, at least two detection control circuits 10 can be provided on the first circuit board 600, as shown in FIG. Figure 7 As shown, at least two detection control circuits 10 are connected to at least two fuses 30 and can be set together on the first circuit board 600; or, at least two detection control circuits 10 can be set on the second circuit board 700, as shown. Figure 8 As shown, at least two detection control circuits 10 are connected to at least two sampling resistors 40 and can be set together on the second circuit board 700; or, at least two detection control circuits 10 are set on a third circuit board 800 different from the first circuit board and the second circuit board 700, as shown in FIG. Figure 9 As shown, at least two detection control circuits 10 arranged on the third circuit board 800 are respectively connected to corresponding battery cells 20 of at least one battery cell 20 on the first circuit board 600 and at least two sampling resistors 40 on the second circuit board 700 .

[0090] In the above scheme, the detection control circuit 10 is set on the first circuit board 600 where the fuse 30 is located, or the detection control circuit 10 is set on the second circuit board 700 where the sampling resistor 40 is located, or the detection control circuit 10 is set on a third circuit board 800 that is different from the first circuit board 600 and the second circuit board 700. The detection control circuit 10 is used to actively monitor whether there is abnormal surge current or short-circuit high current generated on the sampling line, and at the same time realize the on-off control of the sampling line. When abnormal surge current or short-circuit high current is generated, the sampling line is cut off to prevent damage to the components on the first circuit board 600 and the second circuit board 700.

[0091] See also Figure 10-11 , Figure 10 This is a circuit diagram of the battery pack of some embodiments of the present application Figure 1 , Figure 11 This is a circuit diagram of the battery pack of some embodiments of the present application Figure 2 In some embodiments, a battery pack 1000 includes N battery cells 20, a sampling circuit 100, and a battery management circuit 400; the N battery cells 20 are connected in series, and the battery management circuit 400 includes M detection control circuits 10 of the above-mentioned embodiments; wherein N and M are both positive integers, and N is greater than or equal to 1, M=N+1, and each detection control circuit 10 is connected between the positive electrode or the negative electrode of a battery cell 20 and the sampling resistor 40 of the sampling circuit 100.

[0092] When N=1, Figure 10 As shown, the battery pack 1000 includes a battery cell 20, a sampling circuit 100 and a battery management circuit 400, wherein the battery management circuit 400 includes two detection control circuits 10, wherein one of the two detection control circuits 10 is connected between the positive electrode of the battery cell 20 and the sampling resistor 40 on the sampling line corresponding to the positive electrode of the battery cell 20, and the other of the two detection control circuits 10 is connected between the negative electrode of the battery cell 20 and the sampling resistor 40 on the sampling line corresponding to the negative electrode of the battery cell 20.

[0093] When N≥2, such as Figure 11 As shown, the battery pack 1000 includes N battery cells 20, which are connected in series in sequence. The battery management circuit 400 includes M detection control circuits 10, that is, N+1 detection control circuits 10, and each detection control circuit 10 is connected to the positive or negative pole of a battery cell 20. For example, N battery cells 20 include battery cells C1, battery cells C2...battery cells Cn connected in series in sequence, and M detection control circuits 10 include detection control circuit D1, detection control circuit D2...detection control circuit Dm, wherein the detection control circuit D1 can be connected between the negative pole of battery cell C1 and its corresponding sampling resistor 40, the detection control circuit Dm can be connected between the positive pole of battery cell Cn and its corresponding sampling resistor 40, and the detection control circuits 10D2 to the detection control circuit Dm-1 can be connected to the positive pole or negative pole of the two battery cells 20, and connected to the sampling resistor 40 corresponding to the positive pole or negative pole of the battery cell 20. For example, the detection control circuit D2 can be connected to the positive pole of battery cell C1 and the negative pole of C2, and the detection control circuit Dm-1 can be connected to the negative pole of battery cell Cn and the negative pole of Cn-2.

[0094] In the above scheme, the battery pack 1000 includes N battery cells 20, a sampling circuit 100 and a battery management circuit 400; the N battery cells 20 are connected in series in sequence, and the battery management circuit 400 includes M detection control circuits 10, each detection control circuit 10 is connected between the positive or negative pole of a battery cell 20 and the sampling resistor 40 of the sampling circuit 100. The detection control circuit 10 is used to actively monitor whether there is abnormal surge current or short-circuit high current generated on the sampling line, and at the same time realize the on-off control of the sampling line, cutting off the sampling line when abnormal surge current or short-circuit high current is generated, to prevent abnormal melting of the fuse 30 and other device damage problems.

[0095] In some embodiments, see Figure 12 , Figure 12 This is a circuit diagram of the detection control circuit of some embodiments of the present application Figure 4 , the number of control circuits 14 in the M detection control circuits 10 is 1, and the number of resistors 11, switch tubes 12 and operational amplifier circuits 13 are all M.

[0096] The M detection control circuits 10 include M resistors 11, M switches 12, M operational amplifier circuits 13, and a control circuit 14. For example, the control circuit 14 can be connected to the output terminals of the M operational amplifier circuits 13 and the control terminals of the M switches 12. The control circuit 14 can control the M switches 12 to be turned on, so as to detect and obtain first voltage values ​​on the M sampling lines through the corresponding resistors 11 and operational amplifier circuits 13. When the first voltage value on the M sampling lines is greater than a preset value, the control circuit 14 can control one or more corresponding switches 12 among the M switches 12 to be turned off. Furthermore, after the corresponding switch 12 is turned off for a preset time, the control circuit 14 controls the corresponding switch 12 to be turned on again, so as to re-detect and obtain a second voltage value on the sampling line through the corresponding resistor 11 and operational amplifier circuit 13. When the second voltage value is greater than the preset value, the control circuit 14 controls the corresponding switch 12 to be turned off again. When the second voltage value is less than or equal to the preset value, the control circuit 14 controls the corresponding switch 12 to remain turned on. For example, M can be equal to 2, 4, 16, 17, 32, 64, ... and so on.

[0097] In some examples, N=16, M=17, e.g. Figure 13 As shown, BAT represents a battery cell 20, and the 16 battery cells 20 include BAT1, BAT2...BAT16. The 16 battery cells 20 are connected in series in sequence. The battery management circuit 400 includes 17 detection control circuits 10, and each detection control circuit 10 is connected to the positive or negative pole of a battery cell 20. Among them, the 17 detection control circuits 10 may include a control circuit 14, 17 resistors 11, 17 switching tubes 12 and 17 operational amplifier circuits 13.

[0098] In the above scheme, the M detection control circuits 10 include M resistors 11, M switching tubes 12, M operational amplifier circuits 13 and 1 control circuit 14. The control circuit 14 can control the conduction and shutdown of the M switching tubes based on the voltage values ​​across the M resistors 11, thereby actively monitoring whether there is abnormal surge current or short-circuit high current generated on the sampling line, and at the same time realize the on-off control of the sampling line, cutting off the sampling line when abnormal surge current or short-circuit high current is generated, thereby preventing device damage such as abnormal melting of the fuse 30.

[0099] In some embodiments, as Figure 14 As shown, the M detection control circuits 10 also include a multiplexing circuit 1300; the number of control circuits 14 and operational amplifier circuits 13 in the M detection control circuits 10 is 1, and the number of resistors 11 and switch tubes 12 are both M, where the two ends of the M resistors 11 are connected to the operational amplifier circuit 13 through the multiplexing circuit 1300; the multiplexing circuit 1300 is also connected to the control circuit 14.

[0100] The battery pack 1000 includes N battery cells 20, a sampling circuit 100, and a battery management circuit 400. The battery management circuit 400 includes M detection control circuits 10. In other examples, such as Figure 13 As shown, the M detection control circuits 10 may include M resistors 11 and M switches 12, as well as one operational amplifier circuit 13 and one multiplexing circuit 1300. In this case, there is no need to set up multiple operational amplifier circuits 13 for acquisition and output.

[0101] The two ends of the M resistors 11 are connected to the operational amplifier circuit 13 via the multiplexing circuit 1300, that is, the electrical signals at the two ends of the M resistors 11 are obtained by the multiplexing circuit 1300 and transmitted to the operational amplifier circuit 13. The multiplexing circuit 1300 may include at least two multiplexers, and the size and number of the multiplexers can be selected according to actual conditions. In addition, the multiplexing circuit 1300 is also connected to the control circuit 14. For example, the electrical signals at the two ends of the M resistors 11 transmitted by the multiplexing circuit 1300 are transmitted to the operational amplifier circuit 13, and the operational amplifier circuit 13 outputs an analog voltage value, which is converted into a digital value after processing by the analog-to-digital converter 15 and finally transmitted to the control circuit 14, so that the microcontroller 141 in the control circuit can control the conduction and disconnection of the switch tube 12 on the sampling line according to the received digital value.

[0102] In the above scheme, the multiplexing circuit 1300 in the detection control circuit 10 is used to reduce the use of operational amplifiers and achieve a simplified design. Furthermore, the detection control circuit 10 is used to actively monitor whether there is abnormal surge current or short-circuit high current generated on the sampling line, and at the same time, the on-off control of the sampling line is realized. When an abnormal surge current or short-circuit high current is generated, the sampling line is cut off to prevent abnormal fuse blowing and other device damage problems.

[0103] See also Figure 15 , Figure 15 This is a circuit diagram of the battery pack of some embodiments of the present application Figure 5 The multiplexing circuit 1300 includes a first multiplexer 1301 and a second multiplexer 1302, wherein one end of the M resistors 11 is connected to the first input end of the operational amplifier circuit 13 through the first multiplexer 1301, and the other end is connected to the second input end of the operational amplifier circuit 13 through the second multiplexer 1302; the first multiplexer 1301 is also connected to the control circuit 14, and the second multiplexer 1302 is also connected to the control circuit 14.

[0104] One end of the M resistors 11 is connected to a first input end of the operational amplifier circuit 13 via a first multiplexer 1301. For example, the ends of the M resistors 11 connected to the fuse 30 are connected to a non-inverting input end of an operational amplifier 135 in the operational amplifier circuit 13 via the first multiplexer 1301. The other ends of the M resistors 11 are connected to a second input end of the operational amplifier circuit 13 via a second multiplexer 1302. For example, the ends of the M resistors 11 connected to the switch tube 12 are connected to an inverting input end of the operational amplifier 135 in the operational amplifier circuit 13 via the second multiplexer 1302.

[0105] The first multiplexer 1301 is also connected to the control circuit 14, and the second multiplexer 1302 is also connected to the control circuit 14. Figure 16 As shown, the first multiplexer 1301 can be connected to the control circuit 14 through the operational amplifier circuit 13, and the second multiplexer 1302 can also be connected to the control circuit 14 through the operational amplifier circuit 13, so that the control circuit 14 can obtain the voltage difference between the two ends of the M resistors 11, and then control the switching tube 12 on the sampling line corresponding to the M resistors 11 to be turned on and off.

[0106] The first multiplexer 1301 and the second multiplexer 1302 can be single-chip CMOS analog multiplexers, such as the ADI ADG5206. For example, the first multiplexer 1301 and the second multiplexer 1302 can each have 16 built-in single channels. Specifically, the 16 input channels of the first multiplexer 1301 can be connected to the ends of the 16 resistors 11 connected to the fuses 30, and the output channels of the first multiplexer 1301 can be connected to the non-inverting inputs of the operational amplifier 135. The 16 input channels of the second multiplexer 1302 can be connected to the ends of the 16 resistors 11 connected to the switches 12, and the output channels of the second multiplexer 1302 can be connected to the inverting inputs of the operational amplifier 135.

[0107] In some examples, N=16, M=17, e.g. Figure 16 As shown, BAT represents a battery cell 20, and the 16 battery cells 20 include BAT1, BAT2...BAT16. The 16 battery cells 20 are connected in series in sequence. The battery management circuit 400 includes 17 detection control circuits 10, and each detection control circuit 10 is connected to the positive electrode or the negative electrode of a battery cell 20. The 17 detection control circuits 10 include 1 control circuit 14, 2 multiplexers, 17 resistors 11 and 17 switching tubes 12, wherein one end of the 17 resistors 11 is connected to a multiplexer, and the other end of the 17 resistors 11 is connected to another multiplexer.

[0108] In the above scheme, the multiplexing circuit 1300 includes two multiplexers, which reduces the use of operational amplifiers and simplifies the design. Then, the detection control circuit 10 is used to actively monitor whether there is abnormal surge current or short-circuit high current generated on the sampling line, and at the same time, the on-off control of the sampling line is realized. When abnormal surge current or short-circuit high current is generated, the sampling line is cut off to prevent abnormal melting of the fuse 30 and other device damage problems.

[0109] See also Figure 17-18 , Figure 17 This is a circuit diagram of the battery pack of some embodiments of the present application Figure 7 , Figure 18 This is a circuit diagram of the battery pack of some embodiments of the present application Figure 8 ,like Figure 18 As shown, the battery management circuit 400 includes the M+1th detection control circuit 10 in the above embodiment, and the M+1th detection control circuit 10 is connected between the positive electrodes of the N battery cells 20 connected in series and the power supply end of the sampling circuit 100.

[0110] The battery pack 1000 includes N battery cells 20 , a sampling circuit 100 and a battery management circuit 400 . The N battery cells 20 are connected in series. The battery management circuit 400 includes M detection control circuits 10 . The battery management circuit 400 may further include an M+1th detection control circuit 10 .

[0111] When N=1, that is, the battery management circuit 400 is used for one battery cell 20, as shown in FIG. Figure 17 As shown, the battery management circuit 400 includes three detection control circuits 10. For example, the battery management circuit 400 is used for the battery cell C1, and the three detection control circuits 10 include a detection control circuit D1, a detection control circuit D2, and a detection control circuit D3. Among them, the detection control circuit D1 is connected between the negative electrode of the battery cell C1 and the sampling resistor 40 on the sampling line corresponding to the negative electrode of the battery cell 20, the detection control circuit D2 is connected between the positive electrode of the battery cell 20 and the sampling resistor 40 on the sampling line corresponding to the positive electrode of the battery cell 20, and the detection control circuit D3 is connected between the positive electrode of the battery cell C1 and the power supply terminal of the sampling circuit 100.

[0112] When N≥2, that is, the battery management circuit 400 is used for at least two battery cells 20, such as Figure 18As shown, the battery management circuit 400 includes M+1 detection control circuits 10. For example, N battery cells 20 include battery cells C1, C2, ..., and Cn connected in series. The M+1 detection control circuits 10 include detection control circuit D1, detection control circuit D2, ..., detection control circuit Dm, and detection control circuit Dm+1. Detection control circuit D1 can be connected between the negative electrode of battery cell C1 and its corresponding sampling resistor 40, detection control circuit Dm can be connected between the positive electrode of battery cell Cn and its corresponding sampling resistor 40, and detection control circuit Dm+1 can be connected between the positive electrode of battery cell Cn and its corresponding sampling resistor 40. In this case, detection control circuit Dm+1 can be connected between the positive electrode of battery cell Cn and the power supply terminal 110 of the sampling circuit 100.

[0113] It can be understood that the battery cell 20 supplies power to the power supply terminal 110 in the sampling circuit 100 to keep the sampling function normal. At the same time, the M+1th detection control circuit 10 is connected between the positive electrode of the battery cell 20 and the power supply terminal of the sampling circuit 100. The M+1th detection control circuit 10 detects and protects the voltage on the power supply line.

[0114] In the above scheme, the M+1th detection control circuit 10 in the battery management circuit 400 is connected between the positive electrodes of the N battery cells 20 connected in series and the power supply terminal of the sampling circuit 100 to achieve circuit protection. Specifically, the detection control circuit 10 is used to actively monitor whether there is abnormal surge current or short-circuit high current generated on the sampling line, and at the same time, the on-off control of the sampling line is achieved. When abnormal surge current or short-circuit high current is generated, the sampling line is cut off to prevent device damage such as abnormal fuse blowing.

[0115] See also Figure 18-19 , Figure 19 This is a circuit diagram of the battery pack of some embodiments of the present application Figure 9 The battery management circuit 400 further includes M fuses 30 or M+1 fuses 30 , each fuse 30 being connected between the positive electrode or negative electrode of the corresponding battery cell 20 and the corresponding detection control circuit 10 .

[0116] The battery pack 1000 includes N battery cells 20 , a sampling circuit 100 and a battery management circuit 400 . The N battery cells 20 are connected in series. The battery management circuit 400 includes M+1 detection control circuits 10 .

[0117] The battery management circuit 400 may include M fuses 30, such as Figure 18As shown, M fuses 30 are connected between the positive or negative pole of the corresponding battery cell 20 and the corresponding detection control circuit 10. For example, N battery cells 20 include battery cell C1, battery cell C2...battery cell Cn connected in series in sequence, M+1 detection control circuits 10 include detection control circuit D1, detection control circuit D2...detection control circuit Dm and detection control circuit Dm+1, and M fuses 30 include fuse F1, fuse F1...fuse Fm, wherein fuse F1 is connected between the negative pole of the corresponding battery cell C1 and the corresponding detection control circuit D1, fuse F2 is connected between the negative pole of the corresponding battery cell C2 and the corresponding detection control circuit D2, and fuse Fm is connected between the positive pole of the corresponding battery cell Cn and the corresponding detection control circuit Dm, that is, no fuse may be set between the positive pole of the battery cell Cn and the detection control circuit Dm+1.

[0118] Alternatively, the battery management circuit 400 may include M+1 fuses 30, such as Figure 19 As shown, M+1 fuses 30 are connected between the positive or negative pole of the corresponding battery cell 20 and the corresponding detection control circuit 10. For example, the N battery cells 20 include battery cell C1, battery cell C2...battery cell Cn connected in series in sequence, the M+1 detection control circuits 10 include detection control circuit D1, detection control circuit D2...detection control circuit Dm and detection control circuit Dm+1, and the M fuses 30 include fuse F1, fuse F1...fuse Fm and fuse Fm+1, wherein fuse F1 is connected between the negative pole of the corresponding battery cell C1 and the corresponding detection control circuit D1, fuse F2 is connected between the negative pole of the corresponding battery cell C2 and the corresponding detection control circuit D2, fuse Fm is connected between the positive pole of the corresponding battery cell Cn and the corresponding detection control circuit Dm, and fuse Fm+1 is connected between the positive pole of the battery cell Cn and the detection control circuit Dm+1.

[0119] In the above scheme, the battery management circuit 400 includes M fuses 30 or M+1 fuses 30, each fuse 30 is connected between the positive pole or negative pole of the corresponding battery cell 20 and the corresponding detection control circuit 10 to achieve battery cell protection, wherein the detection control circuit 10 is used to actively monitor whether there is abnormal surge current or short-circuit high current generated on the sampling line, and at the same time realize the on-off control of the sampling line, cutting off the sampling line when abnormal surge current or short-circuit high current is generated, to prevent abnormal fuse melting and other device damage problems.

[0120] In some embodiments, as Figure 13As shown, the battery pack 1000 includes 16 battery cells 20 connected in series, wherein the 16 battery cells 20 are respectively represented by BAT1, BAT2...BAT16, and the numbers represent the order of the battery cells 20, such as BAT1 represents the first battery cell 20, BAT16 represents the second battery cell 20, the negative electrode of BAT1 is connected to the first sampling line, and the positive electrode of BAT16 is connected to the seventeenth sampling line. There is a connection point between each battery cell between BAT1 and BAT16 for connecting a sampling line.

[0121] When the battery pack 1000 includes 16 battery cells 20 connected in series, 17 fuses 30 (FUSEs) are connected to the positive or negative electrodes of the 16 battery cells 20. The 17 fuses 30 are named FUSE1, FUSE2, ..., FUSE17 in sequence. FUSE1 is connected to the negative electrode of BAT1, and FUSE17 is connected to the positive electrode of BAT16. All fuses 30 between FUSE1 and FUSE17 are connected between the positive and negative electrodes of two adjacent battery cells 20. For example, FUSE2 is connected between the positive electrode of BAT1 and the negative electrode of BAT2.

[0122] Furthermore, the left side of each FUSE is connected to the positive or negative electrode of the corresponding battery cell 20, and the right side of each FUSE is connected to a small resistance precision resistor (i.e., resistor 11). Its resistance is small, so the voltage divided on the sampling line is small, which is suitable for voltage detection. Its resistance precision can reach within ±1%, or even 0.01%. Figure 13 As shown, the 17 small-resistance precision resistors are RD1, RD2...RD17. For example, the resistance of each small-resistance precision resistor may be 500mΩ, that is, RD1=RD2=...=RD17=500mΩ.

[0123] Furthermore, the two ends of the small-resistance precision resistor are connected to the input ends of the operational amplifier circuit 13, the left side of the small-resistance precision resistor is connected to the first input end of the operational amplifier circuit 13, and the right side of the small-resistance precision resistor is connected to the second input end of the operational amplifier circuit 13. The operational amplifier circuit 13 is composed of an operational amplifier 135 and four operational amplifier resistors. The second operational amplifier resistor 132 is connected to the left side of the small-resistance precision resistor and the same-direction input end of the operational amplifier 135. The fourth operational amplifier resistor 134 is connected to the second operational amplifier resistor 132 and the same-direction input end in parallel and grounded. The first operational amplifier resistor 131 is connected to the right side of the small-resistance precision resistor and the inverting input end of the operational amplifier 135. The third operational amplifier resistor 133 is connected in parallel with the first operational amplifier resistor 131 and the inverting input end of the operational amplifier 135 to the output end of the operational amplifier 135.

[0124] Among them, on the first sampling line, the first operational amplifier resistor 131, the second operational amplifier resistor 132, the third operational amplifier resistor 133, and the fourth operational amplifier resistor 134 are R1, R2, R3, and R4 respectively, the operational amplifier 135 is OP1, and the output end of the operational amplifier 135 is Vout1. On the second sampling line, the first operational amplifier resistor 131, the second operational amplifier resistor 132, the third operational amplifier resistor 133, and the fourth operational amplifier resistor 134 are R5, R6, R7, and R8 respectively, the operational amplifier 135 is OP2, and the output end of the operational amplifier 135 is Vout2. Similarly, on the seventeenth sampling line, On the line, the first operational amplifier resistor 131, the second operational amplifier resistor 132, the third operational amplifier resistor 133, and the fourth operational amplifier resistor 134 are R65, R66, R67, and R68 respectively. The operational amplifier 135 is OP17. The output terminal of the operational amplifier 135 is Vout17. The operational amplifier circuit 13 differentially amplifies the voltage difference on the small resistance precision resistor on each sampling line. The voltage at the parallel point of the small resistance precision resistor close to the FUSE side is recorded as V1, and the voltage at the parallel point of the other side connected to the operational amplifier circuit 13 is recorded as V2. At this time, the output of the operational amplifier 135 (OP1) is:

[0125]

[0126] When R1=R2, R3=R4, the output of operational amplifier 135OP1 is:

[0127]

[0128] The ratio between R3 and R1 is called the gain of the operational amplifier 135. It can amplify the voltage difference across the small resistance precision resistor. In the design, the resistance values ​​of R3 and R1 can be selected independently to facilitate the analog-to-digital converter (ADC) to acquire the voltage. For example, R1 = R2 = R3 = R4, in this case:

[0129]

[0130] Furthermore, the output end of the operational amplifier circuit 13 is connected to the ADC, and the ADC has multiple input ends, and the output end of each operational amplifier 135 is connected thereto, that is, Vout1, Vout2...Vout17 are connected to the input end of the ADC, and the output end of the ADC is connected to the single-chip microcomputer 141 in the control circuit 14. The ADC converts the voltage detection values ​​of the small resistance precision resistor on the seventeen sampling lines, that is, the values ​​of Vout1, Vout2...Vout17, from analog voltage values ​​to digital voltage values, and inputs them into the single-chip microcomputer 141. The single-chip microcomputer 141 has multiple output ports, and each output port is connected to the switch tube 12. The switch tube 12 can be an NMOS. The NMOS has three ports: source, drain, and gate. The drain of the NMOS is connected to the right side of the small resistance precision resistor, and the source is connected to the sampling resistor 40 in the sampling circuit 100. The sampling circuit 100 can be a CSC (Cell Supervision Circuit, battery monitoring unit), when the gate voltage is greater than a certain value, NMOS will be turned on, and the single-chip microcomputer 141 can control NMOS to turn on or off the sampling line. Under normal working conditions, the single-chip microcomputer 141 always outputs a high level, and NMOS remains turned on. When abnormal surge current or short-circuit current occurs in a certain sampling line or multiple sampling lines, the operational amplifier circuit 13 transmits the voltage value of the small resistance precision resistor on each sampling line to the ADC and converts it into a digital voltage value. The single-chip microcomputer 141 compares the detected voltage value on each sampling line with the preset voltage value. When the detected voltage value is greater than the preset voltage value, the single-chip microcomputer 141 sends a signal to NMOS. The gate of the MOS transmits a low level, causing the NMOS to disconnect the sampling line. A preset time is set in the single-chip microcomputer 141. When the sampling line is disconnected for the preset time, the single-chip microcomputer 141 transmits a high level to the gate of the NMOS, causing the NMOS to re-connect the sampling line. At this time, the operational amplifier circuit 13 will re-detect the voltage value on the small-resistance precision resistor on the sampling line. If the detected voltage value is still greater than the preset voltage value, the single-chip microcomputer 141 transmits a low level to the gate of the NMOS, causing the NMOS to be disconnected again. If the detected voltage value is less than or equal to the preset voltage value, the single-chip microcomputer 141 transmits a high level to the gate of the NMOS, causing the NMOS to remain turned on.

[0131] Furthermore, the CSC includes a sampling chip 60, which may be a BQ79616. The other end of each sampling resistor 40 is sequentially connected to ports VC0, VC1, ..., VC16 on the BQ79616. The CSC also includes a sampling balancing resistor 50, which is connected in parallel to the left side of each sampling resistor 40 and connected to ports VB0, VB1, ..., VB16 of the BQ79616. The BQ79616 can enable or disable the balancing function of the sampling line through the balancing resistor 50. The BQ79616 can control the balancing resistor 50 to adjust the battery cells 20 with uneven charge based on the voltage information on the sampling line, thereby extending the service life of the battery cells 20 and ensuring the consistency of the battery pack.

[0132] Furthermore, taking RD1 = 500mΩ, R1 = R2 = R3 = R4 = 10Ω as an example, when the sampling line does not enable the balancing function, the current in the loop is approximately 10mA. At this time, the voltage difference across the small resistance precision resistor, i.e., the output Vout1 of the operational amplifier 135OP1, is:

[0133]

[0134] When the sampling line is balanced, the current in the loop is about 100mA. At this time, the voltage difference across the small-resistance precision resistor, that is, the output Vout1 of the operational amplifier 135OP1, is:

[0135]

[0136] At this time, the output value of the operational amplifier 135 is an analog voltage value, which is converted into a digital voltage value after being processed by the ADC. The ADC transmits the digital voltage value of each sampling line to the single-chip microcomputer 141. In the single-chip microcomputer 141, it can be set that when the voltage value of a certain sampling line is greater than a preset value, it is determined that the sampling line has an abnormal surge or short-circuit current. The preset value can be 0.05V, and the specific value can be set by yourself. That is, when the voltage value Vout of a certain sampling line is greater than 0.05V, the single-chip microcomputer 141 outputs a low level to the NMOS on the sampling line, so that the NMOS cuts off the sampling line. A preset value is set in the single-chip microcomputer 141. Set a time, the preset time can be 10s, and the specific value can be set by yourself. After the sampling line is disconnected for 10s, the microcontroller 141 transmits a high level to the gate of the NMOS, so that the NMOS turns the sampling line back on. At this time, the operational amplifier circuit 13 will re-detect the voltage value on the small resistance precision resistor on the sampling line. If the detected voltage value Vout is greater than 0.05V, the microcontroller 141 transmits a low level to the gate of the NMOS, so that the NMOS is disconnected again. If the detected voltage value Vout is less than or equal to 0.05V, the microcontroller 141 transmits a high level to the gate of the NMOS, so that the NMOS remains turned on.

[0137] In other embodiments, since there are many sampling lines and each sampling line needs to be provided with an operational amplifier 135, a multiplexer can be used to replace the redundant operational amplifiers 135, and only one operational amplifier 135 is retained to perform voltage detection and control on multiple sampling lines. Figure 16 As shown in the figure, taking the ADI ADG5206 as an example, the ADI ADG5206 is a single-chip CMOS analog multiplexer with 16 built-in channels. The ADI ADG5206 switches one of the 16 inputs to the common output according to the address determined by the 4-bit binary address lines A0, A1, A2 and A3. When turned on, the conductivity of each switch in both directions is the same.

[0138] Using two multiplexers ADI ADG5206 transmits the voltage across the small-resistance precision resistor to the operational amplifier circuit 13, wherein the end of the small-resistance precision resistor near the fuse is connected to the first multiplexer 1301 (U1), and the end of the small-resistance precision resistor near the NMOS is connected to the second multiplexer 1302 (U2). RD1, RD2...RD16 are connected to S1, S2...S16 of U1 and S1, S2...S16 of U2, respectively. The output ends of U1 and U2 are connected to the first input end and the second input end of the operational amplifier circuit 13, respectively, that is, the D port of U1 and the D port of U2 are connected to the non-inverting input end and the inverting input end of the operational amplifier 135, respectively. The 4-bit binary address lines A0, A1, A2, and A3 of U1 and U2 are interconnected and connected to the input end of the single-chip microcomputer 141. The single-chip microcomputer 141 switches the output of different sampling lines by controlling the address level. The truth table of A0, A1, A2, and A3 is shown in Table 1:

[0139] Table 1

[0140]

[0141] Among them, EN is the enable terminal. When EN is None, U1 and U2 do not work. When EN is 1, U1 and U2 start to work. The 4-bit binary address lines A0, A1, A2 and A3 represent 1, 2 and 16 sampling lines respectively when they are 0001, 0011...1111, that is, the inputs of the 1st, 2nd and 16th sampling lines are switched to the common output, and input from the D ports of U1 and U2 to the operational amplifier circuit 13. The operational amplifier circuit 13 performs voltage detection on the small resistance precision resistor on the sampling line. Therefore, the output value of the operational amplifier circuit 13 can be VoutX (X: 1-16), which can output the detection voltage value on each sampling line.

[0142] For further information, please refer to Figure 13 and Figure 16The sampling cell BQ79616 further includes a power supply terminal BAT, an 18th FUSE, an 18th small-resistance precision resistor, an 18th or second and third operational amplifier circuits 13, an 18th NMOS, and an 18th sampling resistor 40. The connections are made accordingly according to the relevant descriptions of the above embodiments, and the other end of the 18th sampling resistor 40 is connected to BAT.

[0143] In the above scheme, the detection control circuit 10 includes a resistor 11, a switch tube 12, an operational amplifier circuit 13 and a control circuit 14. When the first voltage value is greater than a preset value, the control circuit 14 controls the switch tube 12 to be disconnected; after the switch tube 12 is disconnected for a preset time, the control circuit 14 controls the switch tube 12 to be turned on again, so as to re-detect and obtain a second voltage value on the sampling line through the resistor 11 and the operational amplifier circuit 13; when the second voltage value is greater than the preset value, the control circuit 14 controls the switch tube 12 to be turned off again, and when the second voltage value is less than or equal to the preset value, the control circuit 14 controls the switch tube 12 to remain turned on, thereby actively monitoring whether there is an abnormal surge current or a short-circuit high current generated on the sampling line, and at the same time realizing the on-off control of the sampling line, cutting off the sampling line when an abnormal surge current or a short-circuit high current is generated, thereby preventing device damage such as abnormal melting of the fuse 30.

[0144] In some embodiments, the functions or modules included in the device provided by the embodiments of the present disclosure can be used to execute the method described in the above method embodiments. The specific implementation can refer to the description of the above method embodiments. For the sake of brevity, it will not be repeated here.

[0145] The above description of the various embodiments tends to emphasize the differences between the various embodiments. The same or similar aspects can be referenced with each other and will not be repeated herein for the sake of brevity.

[0146] In the several embodiments provided in this application, it should be understood that the disclosed methods and devices can be implemented in other ways. For example, the device implementation methods described above are only schematic. For example, the division of modules or units is only a logical function division. There may be other division methods in actual implementation. For example, units or components can be combined or integrated into another system, or some features can be ignored or not executed. In another image position, the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, and the indirect coupling or communication connection of devices or units can be electrical, mechanical or other forms.

[0147] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in either hardware or software functional units. If the integrated units are implemented as software functional units and sold or used as standalone products, they may be stored on a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the portion that contributes to the prior art, or all or part of the technical solution, may be embodied in the form of a software product. This computer software product, stored on a storage medium, includes instructions for causing a computer device (such as a personal computer, server, or network device) or processor to execute all or part of the steps of the various embodiments of the present application. The aforementioned storage media include various media capable of storing program code, such as USB flash drives, removable hard drives, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical disks.

Claims

1. A detection control circuit, characterized in that: Used on the sampling line of the battery cell, connected between the positive electrode or negative electrode of the battery cell and the sampling resistor on the sampling line, including: a resistor, one end of which is connected to the positive electrode or the negative electrode of the battery cell; a switch tube, a first end of which is connected to the other end of the resistor, and a second end of which is connected to the sampling resistor; an operational amplifier circuit, wherein a first input terminal is connected to one end of the resistor, and a second input terminal is connected to the other end of the resistor; A control circuit connected to the output end of the operational amplifier circuit and the control end of the switch tube; In which, the control circuit controls the switch tube to be turned on, so as to obtain a first voltage value on the sampling line through the resistor and the operational amplifier circuit; when the first voltage value is greater than a preset value, the control circuit controls the switch tube to be turned off; after the switch tube is turned off for a preset time, the control circuit controls the switch tube to be turned on again, so as to obtain a second voltage value on the sampling line through the resistor and the operational amplifier circuit; when the second voltage value is greater than the preset value, the control circuit controls the switch tube to be turned off again, and when the second voltage value is less than or equal to the preset value, the control circuit controls the switch tube to remain turned on.

2. The detection control circuit according to claim 1, characterized in that: The control circuit includes a single chip microcomputer; The detection control circuit further includes an analog-to-digital converter, which is connected between the output end of the operational amplifier circuit and the single chip microcomputer.

3. The detection control circuit according to claim 1 or 2, characterized in that: The operational amplifier circuit includes a first operational amplifier resistor, a second operational amplifier resistor, a third operational amplifier resistor, a fourth operational amplifier resistor and an operational amplifier; One end of the first operational amplifier resistor is connected to the other end of the resistor as the second input end, and the other end is connected to the inverting input end of the operational amplifier and connected to the output end of the operational amplifier through the third operational amplifier resistor; One end of the second operational amplifier resistor is connected to one end of the resistor as the first input end, and the other end is connected to the non-inverting input end of the operational amplifier and grounded through the fourth operational amplifier resistor; The output end of the operational amplifier serves as the output end of the operational amplifier circuit.

4. The detection control circuit according to claim 3, characterized in that: The resistance values ​​of the first operational amplifier resistor, the second operational amplifier resistor, the third operational amplifier resistor, and the fourth operational amplifier resistor are the same.

5. A battery management circuit, characterized in that: For at least one battery cell, comprising at least two detection control circuits according to any one of claims 1 to 4, wherein each of the detection control circuits is connected between the positive electrode or the negative electrode of a corresponding battery cell in the at least one battery cell and a sampling resistor on a sampling line of the corresponding battery cell.

6. The battery management circuit according to claim 5, characterized in that: It also includes at least two fuses, each of which is connected between the positive electrode or negative electrode of a corresponding battery cell in the at least one battery cell and the corresponding detection control circuit.

7. The battery management circuit according to claim 6, characterized in that: The at least two fuses are arranged on the first circuit board, and the sampling resistor is arranged on the second circuit board; At least two of the detection control circuits are arranged on the first circuit board, or the at least two of the detection control circuits are arranged on the second circuit board, or the at least two of the detection control circuits are arranged on a third circuit board different from the first circuit board and the second circuit board.

8. A battery pack, characterized in that: Includes N battery cells, sampling circuit and battery management circuit; The N battery cells are connected in series in sequence, and the battery management circuit includes M detection and control circuits according to any one of claims 1 to 4; Wherein, N and M are both positive integers, and N is greater than or equal to 1, M=N+1, and each of the detection control circuits is connected between the positive electrode or the negative electrode of one of the battery cells and the sampling resistor of the sampling circuit.

9. The battery pack according to claim 8, characterized in that: The number of the control circuits in the M detection control circuits is 1, and the number of the resistors, the switching tubes, and the operational amplifier circuits are all M.

10. The battery pack according to claim 8, wherein: The M detection control circuits further include a multiplexing circuit; The number of the control circuits and the operational amplifier circuits in the M detection control circuits is 1, and the number of the resistors and the switching tubes is M, wherein the two ends of the M resistors are connected to the operational amplifier circuit through the multiplexing circuit; the multiplexing circuit is also connected to the control circuit.

11. The battery pack according to claim 10, characterized in that: The multiplexing circuit includes a first multiplexer and a second multiplexer, wherein one end of the M resistors is connected to the first input end of the operational amplifier circuit through the first multiplexer, and the other end is connected to the second input end of the operational amplifier circuit through the second multiplexer; The first multiplexer is further connected to the control circuit, and the second multiplexer is further connected to the control circuit.

12. The battery pack according to claim 8, wherein: The battery management circuit further includes an M+1th detection control circuit according to any one of claims 1 to 4, wherein the M+1th detection control circuit is connected between the positive electrodes of the N battery cells connected in series and the power supply end of the sampling circuit.

13. The battery pack according to any one of claims 8 to 12, characterized in that: The battery management circuit further includes M fuses or M+1 fuses, each of which is connected between the positive electrode or negative electrode of the corresponding battery cell and the corresponding detection control circuit.

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