Back contact battery and photovoltaic module

Abstract

The utility model provides a back contact cell and a photovoltaic assembly, the back contact cell comprises a semiconductor substrate, and a first surface of the semiconductor substrate comprises a minority sub-region and a multi-sub-region which are alternately distributed at intervals along a first direction; the first doped semiconductor part is arranged in the minority carrier region; the second doped semiconductor part is arranged in the multiple sub-regions, and the conduction type of the second doped semiconductor part is opposite to that of the first doped semiconductor part; the first transparent conductive layer is arranged on the first doped semiconductor part; the second transparent conductive layer is arranged on the second doped semiconductor part; wherein the ratio of the width of the first transparent conductive layer to the width of the minority sub-region in the first direction is 0.8-1, and the ratio of the width of the second transparent conductive layer to the width of the multi-sub-region in the first direction is 0.6-1.

Description

Technical Field

[0001] At least one embodiment of the present utility model relates to the field of photovoltaic technology, and in particular to a back-contact cell and a photovoltaic module. Background Art

[0002] In back-contact cells, electron-hole pairs undergo both lateral and longitudinal transport within the cell before being collected by the corresponding electrodes. That is, majority carriers are generated in the minority-carrier region and transported laterally to the majority-carrier region for collection; conversely, minority carriers are generated in the majority-carrier region and transported laterally to the least-carrier region for collection. Compared to bifacial cells, where carriers are primarily transported and collected longitudinally along the cell, carriers undergo a more complex drift and diffusion motion within the cell.

[0003] Therefore, the geometric structure design of the back-contact cell plays a vital role in achieving high photoelectric conversion efficiency. The geometric design includes but is not limited to parameters such as pitch width, minority carrier region width, majority carrier region width, and spacer region width.

[0004] In view of this, how to design the geometric structure of the back-contact cell to maintain a high photoelectric conversion efficiency has become a technical problem that needs to be solved urgently. Utility Model Content

[0005] To address at least one of the aforementioned and other technical issues in the prior art, the present invention provides a back-contact cell and photovoltaic module. A first doped semiconductor portion is disposed in the minority carrier region to form the emitter region of the back-contact cell, and a second doped semiconductor portion is disposed in the majority carrier region to form the back field region of the back-contact cell. By designing the widths of the first and second doped semiconductor portions, carrier collection efficiency can be effectively improved. Furthermore, by configuring a transparent conductive layer to cover the first and second doped semiconductor portions in a ratio that satisfies insulation requirements, the minority and majority carrier regions can collect both minority and majority carriers.

[0006] An embodiment of the present invention provides a back-contact cell, comprising: a semiconductor substrate, wherein a first surface of the semiconductor substrate includes minority carrier regions and majority carrier regions alternately spaced along a first direction; a first doped semiconductor portion disposed in the minority carrier region; a second doped semiconductor portion disposed in the majority carrier region, the second doped semiconductor portion having a conductivity type opposite to that of the first doped semiconductor portion; a first transparent conductive layer disposed on the first doped semiconductor portion; and a second transparent conductive layer disposed on the second doped semiconductor portion. The ratio of the width of the first transparent conductive layer to the width of the minority carrier region along the first direction is 0.8-1, and the ratio of the width of the second transparent conductive layer to the width of the majority carrier region along the first direction is 0.6-1. The minority carrier region has relatively poor lateral transport capability, requiring a higher coverage rate of the first transparent conductive layer over the minority carrier region. The majority carrier region has a stronger lateral transport capability, requiring a higher coverage rate of the second transparent conductive layer over the majority carrier region.

[0007] According to an embodiment of the present invention, the width of each minority carrier region along the first direction is 50 μm to 2500 μm, and the width of each majority carrier region along the first direction is 50 μm to 1500 μm. The width of the minority carrier region is wider than the majority carrier region, which can increase the minority carrier collection range and reduce the recombination of minority carriers in the majority carrier collection region.

[0008] According to an embodiment of the present invention, the width of the minority carrier region along the first direction is configured to be greater than the width of the majority carrier region along the first direction; and the ratio of the widths of the first transparent conductive layer to the second transparent conductive layer along the first direction is greater than 1 and less than 5. The minority carrier region has relatively poor lateral transport capability for minority carriers, while the majority carrier region has stronger lateral transport capability for majority carriers, requiring the first transparent conductive layer to be wider than the second transparent conductive layer. Setting a width ratio greater than 1 and less than 5 facilitates the design of the insulation structure and reduces process complexity.

[0009] According to an embodiment of the present invention, the ratio of the thickness of the second transparent conductive layer to the thickness of the first transparent conductive layer is 1.4 to 1.8. The first transparent conductive layer is set to be thinner than the second transparent conductive layer to better adapt to the textured structure of the minority carrier region and increase the light absorption effect.

[0010] According to an embodiment of the present invention, the photovoltaic module further includes a first electrode disposed on the first transparent conductive layer and extending along a second direction, the second direction intersecting the first direction; the ratio of the width of the first electrode to the width of the first transparent conductive layer along the first direction is 0.05 to 1. This wider range of configurations allows for the use of a variety of metallization options, such as precious metals and base metals, increasing process compatibility.

[0011] According to an embodiment of the present invention, the photovoltaic module further includes a second electrode disposed on the second transparent conductive layer and extending along a second direction intersecting the first direction. The ratio of the width of the second electrode to the width of the second transparent conductive layer along the first direction is 0.05 to 1. This wider range of configurations allows for the use of a variety of metallization options, including precious metals and base metals, increasing process compatibility.

[0012] According to an embodiment of the present invention, a first opening is provided on the minority carrier region, and a second opening is provided on the majority carrier region. A spacing region is formed between facing ends of the first opening and the second opening.

[0013] According to an embodiment of the present invention, the first transparent conductive layer covers the first opening, the second transparent conductive layer covers the second opening, and an insulating region is formed between the facing ends of the first transparent conductive layer and the second transparent conductive layer. The provision of this insulating region can enhance carrier collection capability.

[0014] According to an embodiment of the present invention, the second transparent conductive layer further extends to the first doped semiconductor portion.

[0015] According to an embodiment of the present invention, in the orthographic projection of the first surface, the projection of the insulating region coincides with the projection of the spacing region.

[0016] According to an embodiment of the present invention, the first transparent conductive layer covers a portion of the first opening, and the second transparent conductive layer covers the second opening and extends to the first doped semiconductor portion. In an orthographic projection of the first surface, the portion between the projections of the first transparent conductive layer and the second transparent conductive layer forms an insulating region. The provision of this insulating region provides better insulation, reduces short circuits, and improves yield.

[0017] According to an embodiment of the present invention, in the orthographic projection of the first surface, the projection of the insulating region partially overlaps with the projection of the spacing region.

[0018] According to an embodiment of the present invention, a width of the spacer along the first direction is 20 μm to 400 μm.

[0019] According to an embodiment of the present invention, a width of the insulating region along the first direction is 20 μm to 200 μm.

[0020] According to an embodiment of the present invention, a ratio of the widths of the insulating region and the spacing region along the first direction is 0.2-1.

[0021] According to an embodiment of the present invention, the sum of the widths of adjacent minority and majority carrier regions along the first direction is 300μm to 3000μm. The sum of the widths of the minority and majority carrier regions is positively correlated with the pitch width. This width range allows for flexible design of the number of fine gates to accommodate silicon wafers with varying doping concentrations, thereby improving overall cell efficiency and reducing manufacturing costs.

[0022] An embodiment of the present invention further provides a photovoltaic module including a back-contact cell.

[0023] According to the back contact cell and photovoltaic module provided by the present invention, the first doped semiconductor part is arranged in the minority carrier region to form the emitter region of the back contact cell, and the second doped semiconductor part is arranged in the majority carrier region to form the back field region of the back contact cell. By configuring a transparent conductive layer to cover the ratio of the minority carrier region and the majority carrier region, the insulation and carrier collection effects can be balanced, and physical isolation of the first doped semiconductor part and the second doped semiconductor part with opposite conductivity types can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a longitudinal cross-sectional schematic diagram of a back-contact battery according to an exemplary embodiment of the present invention;

[0025] Figure 2 It is a schematic longitudinal cross-sectional view of a back-contact battery according to another exemplary embodiment of the present invention.

[0026] In the drawings, the meanings of the reference numerals are as follows:

[0027] 11. Semiconductor substrate;

[0028] 12. Insulation layer;

[0029] 13. a first doped semiconductor portion;

[0030] 14. a first transparent conductive layer;

[0031] 15. a first electrode;

[0032] 16. a second electrode;

[0033] 17. a second transparent conductive layer;

[0034] 18. a second doped semiconductor portion;

[0035] 19. Interface passivation layer;

[0036] 20. Small population area;

[0037] 21. Multiple sub-areas. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0039] The terms used herein are only for describing specific embodiments and are not intended to limit the present invention. The terms "comprise", "include", etc. used herein indicate the presence of the features, steps, operations and / or components, but do not exclude the presence or addition of one or more other features, steps, operations or components.

[0040] All terms used herein, including technical and scientific terms, have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0041] When expressions such as “at least one of A, B, and C, etc.” are used, they should generally be interpreted in accordance with the meaning commonly understood by those skilled in the art. For example, “a system having at least one of A, B, and C” should include but is not limited to systems having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, and C, etc. When expressions such as “at least one of A, B, or C, etc.” are used, they should generally be interpreted in accordance with the meaning commonly understood by those skilled in the art. For example, “a system having at least one of A, B, or C” should include but is not limited to systems having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, and C, etc.

[0042] The positive and negative electrodes of a back-contact cell are located on the backside of the cell, minimizing the footprint of the metal electrodes on the front of the cell and resulting in higher energy conversion efficiency. The minority and majority carrier regions of a back-contact cell are interdigitated on the backside of the cell. Sunlight striking the light-receiving side of the cell forms hole-electron pairs at the cell's PN junction. For example, in a cell with an N-type silicon wafer as the semiconductor substrate, the P region serves as the minority carrier region, collecting minority carriers (i.e., holes); correspondingly, the N region serves as the majority carrier region, collecting majority carriers (i.e., electrons) to generate current when the circuit is connected.

[0043] Based on these characteristics, compared to bifacial cells, back-contact cells have electron-hole pairs that not only travel longitudinally but also transversely, resulting in more complex drift and diffusion motions. When minority and majority carriers pass through regions of opposite conductivity, surface recombination may occur.

[0044] Therefore, how to design the geometric structure of the back contact battery to maintain a high photoelectric conversion efficiency has become a technical problem that needs to be solved urgently.

[0045] Figure 1 It is a schematic longitudinal cross-sectional view of a back-contact battery according to an illustrative embodiment of the present invention.

[0046] According to the back contact battery provided by the present invention, Figure 1 As shown, the device comprises a semiconductor substrate 11, a first doped semiconductor portion 13, a second doped semiconductor portion 18, a first transparent conductive layer 14, and a second transparent conductive layer 17. The first surface of the semiconductor substrate 11 includes minority carrier regions 20 and majority carrier regions 21, alternately spaced along a first direction. The first doped semiconductor portion 13 is disposed in the minority carrier region 20; the second doped semiconductor portion 18 is disposed in the majority carrier region 21. The conductivity type of the second doped semiconductor portion 18 is opposite to that of the first doped semiconductor portion 13. The first transparent conductive layer 14 is disposed on the first doped semiconductor portion 13. The second transparent conductive layer 17 is disposed on the second doped semiconductor portion 18. The ratio of the width of the first transparent conductive layer 14 to that of the minority carrier region 20 along the first direction is 0.8-1, and the ratio of the width of the second transparent conductive layer 17 to that of the majority carrier region 21 along the first direction is 0.6-1. The thickness ratio of the second transparent conductive layer to the first transparent conductive layer is 1.4-1.8. As a result, the minority carrier lateral transport capability of the minority carrier region is relatively poor, requiring a higher coverage of the minority carrier region by the first transparent conductive layer. For the multi-sub region, the multi-sub lateral transmission capability is relatively strong, and the coverage rate of the second transparent conductive layer on the multi-sub region does not need to be higher.

[0047] To clearly illustrate the embodiments of the present invention, the widths of the regions, layers, and portions mentioned below are all represented as the widths of the corresponding portions along the first direction unless otherwise specified.

[0048] In an illustrative embodiment, Figure 1 As shown, the first surface of the semiconductor substrate 11 includes but is not limited to the backlight surface used as the back contact battery (such as Figure 1 The left side surface shown in FIG), accordingly, the second surface of the semiconductor substrate 11 opposite to the first surface (such as Figure 1 The right side surface shown in FIG. 1 is used as the light-receiving surface of the back contact battery. Figure 1 A minority carrier region 20 and a majority carrier region 21 are provided in a spaced relationship (in the vertical direction shown). The first doped semiconductor portion 13 is formed in the minority carrier region 20 and serves as the emitter region (i.e., the emitter) of the back-contact cell. The second doped semiconductor portion 18 is formed in the majority carrier region 21 and serves as the back surface field (BSF) of the back-contact cell.

[0049] In an exemplary embodiment, the semiconductor substrate 11 may be a silicon substrate. Alternatively, the semiconductor substrate 11 may be a substrate made of any semiconductor material, such as a silicon germanium substrate, a germanium substrate, or a gallium arsenide substrate. Furthermore, the semiconductor substrate 11 may be an N-type semiconductor substrate or a P-type semiconductor substrate.

[0050] Correspondingly, the conductivity type of the first doped semiconductor portion may also be P-type, in which case the conductivity type of the second doped semiconductor portion is N-type; or, the conductivity type of the first doped semiconductor portion may be N-type, in which case the conductivity type of the second doped semiconductor portion is P-type.

[0051] In an exemplary embodiment, the semiconductor substrate 11 is an N-type semiconductor substrate. Accordingly, the first doped semiconductor portion 13 is configured as a P-type doped semiconductor, and the second doped semiconductor portion 18 is configured as an N-type doped semiconductor.

[0052] According to the embodiment of the present utility model, Figure 1 As shown, the width of each minority carrier region 20 along the first direction is 50 μm to 2500 μm, and the width of each majority carrier region 21 along the first direction is 50 μm to 1500 μm. Thus, the minority carrier region is wider than the majority carrier region, which can increase the minority carrier collection range and reduce the recombination of minority carriers in the majority carrier collection region.

[0053] According to the embodiment of the present utility model, Figure 1 As shown, the sum of the widths of the adjacent minority carrier regions 20 and majority carrier regions 21 along the first direction is 300 μm to 3000 μm.

[0054] In an illustrative embodiment, Figure 1 As shown, the minority carrier region 20 is arranged along the first direction (eg Figure 1 The width of the minority carrier region 20 (in the vertical direction shown) is configured as W1, and the width of the multi-carrier region 21 is configured as W2. In a preferred embodiment, the width of the minority carrier region 20 includes, but is not limited to, any value between 500μm and 560μm (i.e., 500μm ≤ W1 ≤ 560μm), and the corresponding width of the multi-carrier region 21 is configured as 440μm to 500μm (i.e., 440μm ≤ W2 ≤ 500μm). It should be understood that the embodiments of the present invention are not limited to this.

[0055] With improved process precision, the pitch width (i.e., W1 + W2) can be narrowed accordingly. To this end, various layout designs are possible, including but not limited to 780μm, 1000μm, 1300μm, or other sizes. Furthermore, the combined width of the minority carrier region 20 and the majority carrier region 21 can be configured to range from 300μm to 3000μm (i.e., 300μm ≤ W1 + W2 ≤ 3000μm).

[0056] In this embodiment, the first doped semiconductor portion 13 is disposed in the minority carrier region 20 to form the emitter region of the back-contact cell, and the second doped semiconductor portion 18 is disposed in the majority carrier region 21 to form the back field region of the back-contact cell. The wide emitter of the back-contact cell effectively collects minority carriers and transmits them to the external circuit, while also reducing contact resistance and energy loss. Correspondingly, the narrow back field region effectively collects majority carriers while reducing surface recombination of minority carriers through the majority carrier region, resulting in a high carrier collection efficiency for the back-contact cell.

[0057] In an illustrative embodiment, Figure 1 As shown, the ratio of the widths of the first transparent conductive layer 14 and the minority carrier region 20 along the first direction includes, but is not limited to, being configured to be 0.8 to 1 (i.e., 80% ≤ W3 / W1 ≤ 100%). Furthermore, the ratio of the widths of the second transparent conductive layer 17 and the majority carrier region 21 is (i.e., 60% ≤ W4 / W2 ≤ 100%).

[0058] In a preferred embodiment, the width of the first transparent conductive layer 14 (i.e., W3) is configured to be substantially the same as the width of the minority carrier region 20 (i.e., W1). For example, the width of the first transparent conductive layer 14 (i.e., W3) and the width of the minority carrier region 20 (i.e., W1) are both configured to be 530 μm (i.e., W1 = W3 = 530 μm). This helps improve the collection efficiency of minority carriers.

[0059] In an exemplary embodiment, the ratio of the thickness of the second transparent conductive layer 17 to the thickness of the first transparent conductive layer 14 is 1.4-1.8. Thus, the first transparent conductive layer is set to be thinner than the second transparent conductive layer to better adapt to the textured structure of the minority carrier region and enhance the light absorption effect.

[0060] In a preferred embodiment, the thickness of the first transparent conductive layer 14 is 15-55 μm, and the thickness of the second transparent conductive layer 14 is 25-80 μm.

[0061] Reference Figure 1 As shown, the first transparent conductive layer 14 is located in the first doped semiconductor portion 13 with a step-like structure on both sides. Therefore, the width of the first transparent conductive layer 14 should be smaller than the width of the minority carrier region 20. Figure 1 This is a macroscopically magnified schematic diagram for illustrating the layer structure. The purpose is to clearly illustrate the layer structure of the first side of the back-contact cell. In an actual layered structure, the thickness of the first doped semiconductor portion 13 should be on the nanometer scale (including but not limited to 10 nm). Therefore, this thickness can be neglected in the 530 μm-level widths of W1 and W3. In other words, W3 is assumed to be approximately the same width as W1, or slightly smaller than W1.

[0062] In an illustrative embodiment, Figure 1 As shown, the second transparent conductive layer 17 is arranged along the first direction (eg Figure 1 The width (i.e., W4) of the second transparent conductive layer 17 (in the vertical direction shown) includes, but is not limited to, being configured within a range of 50 μm to 1500 μm (i.e., 50 ≤ W4 ≤ 1500 μm). Furthermore, the width (i.e., W2) of the multi-sub-region 21 includes, but is not limited to, being configured within a range of 50 μm to 2500 μm (i.e., 50 ≤ W2 ≤ 2500 μm). In other words, the ratio of the width of the second transparent conductive layer 17 to the width of the multi-sub-region 21 is 60% ≤ W4 / W2 ≤ 100%.

[0063] In a preferred embodiment, the width of the second transparent conductive layer 17 is configured to be smaller than the width of the majority-sub-region 21 (i.e., W4 < W2). Specifically, the second transparent conductive layer 17 is disposed at the location of the light spot opening (i.e., the second opening described below) formed by etching (or laser) between two adjacent minority-sub-regions 20, so as to completely cover the second doped semiconductor portion 18 exposed at the opening. The width of the second transparent conductive layer 17 (i.e., W4) includes, but is not limited to, being configured to be 150μm to 210μm (i.e., 150 ≤ W4 ≤ 210μm), and preferably, can be configured to be 180μm. Correspondingly, the width of the majority-sub-region 21 (i.e., W2) includes, but is not limited to, being configured to be 440μm to 500μm (i.e., 440 ≤ W2 ≤ 500μm).

[0064] In this embodiment, the spacer has carrier collection regions of different conductivity types (i.e., P-type and N-type) on both sides. Majority carriers and minority carriers are prone to severe edge loading near the spacer. Therefore, the smaller the width of the spacer, the more conducive it is to preventing the above-mentioned situation. At the same time, the smaller the width of the spacer, the more conducive it is to reducing the series resistance and correspondingly increasing the short-circuit current (i.e., J SC ), filling factor (ie FF, such as pFF).

[0065] However, due to external factors such as process precision (currently controlled at approximately 50 µm), if the width of this spacer is set too small, leakage (such as tunneling) can easily occur. Therefore, by configuring the transparent conductive layer (i.e., the first transparent conductive layer 14 and the second transparent conductive layer 17) to cover the ratio of the minority carrier region 20 to the majority carrier region 21, the insulation between the first doped semiconductor portion 13 and the second doped semiconductor portion 18 is maintained, thereby facilitating the configuration of a spacer that is as narrow as possible. Furthermore, while maintaining insulation, it also provides better carrier collection.

[0066] In an illustrative embodiment, Figure 1As shown, an interface passivation layer 19 is further disposed between the second doped semiconductor portion 18 and the semiconductor substrate 11. Specifically, the passivation contact structure formed by the interface passivation layer 19 and the second doped semiconductor portion 18 has excellent interface passivation and enables selective carrier collection, further improving the photoelectric conversion efficiency of the back-contact cell. It should be understood that the embodiments of the present invention are not limited to this.

[0067] For example, when the material of the second doped semiconductor portion 18 is doped polysilicon, the interface passivation layer 19 may be a tunneling passivation layer.

[0068] For example, when the material of the second doped semiconductor portion 18 includes at least one of doped amorphous silicon, doped microcrystalline silicon and doped nanocrystalline silicon, the interface passivation layer 19 may be an intrinsic amorphous silicon layer, an intrinsic microcrystalline silicon layer, an intrinsic nanocrystalline silicon layer or a mixture thereof.

[0069] According to the embodiment of the present utility model, Figure 1 As shown, the width of the minority carrier region 20 is configured to be greater than the width of the majority carrier region 21 (i.e., W1>W2). The ratio of the widths of the first transparent conductive layer 14 to the second transparent conductive layer 17 is greater than 1 and less than 5 (i.e., 1<W3 / W4<5). This results in relatively poor lateral transport of minority carriers in the minority carrier region. In contrast, the majority carrier region has stronger lateral transport, requiring the first transparent conductive layer to be wider than the second transparent conductive layer. A width ratio greater than 1 but less than 5 facilitates the design of the insulation structure and reduces manufacturing complexity.

[0070] In a preferred embodiment, Figure 1 As shown, the first transparent conductive layer 14 and the minority carrier region 20 are arranged along a first direction (eg Figure 1 The widths of the first transparent conductive layer 14 (i.e., W3) and the second transparent conductive layer 17 (i.e., W4) are configured to be substantially the same (i.e., W1>W3). Furthermore, the second transparent conductive layer 17 is configured to cover the second semiconductor doped portion 17 disposed at the location of the light spot opening formed by etching (or laser) between two adjacent minority carrier regions 20. The ratio (i.e., W3 / W4) of the width of the first transparent conductive layer 14 (i.e., W3) to the width of the second transparent conductive layer 17 (i.e., W4) includes, but is not limited to, being configured to be 1.4 to 3.0 (i.e., 1.4≤W3 / W4≤3.0).

[0071] In this embodiment, the width of the minority carrier region 20 is configured to be greater than the width of the majority carrier region 21, which can increase the effective collection of minority carriers. On this basis, through the above-mentioned design of the width of the first transparent conductive layer 14 and the second transparent conductive layer 17, better battery performance can be achieved.

[0072] According to the embodiment of the present utility model, Figure 1As shown, the back-contact cell further includes a first electrode 15 disposed on the first transparent conductive layer 14 and extending along a second direction that intersects (e.g., is orthogonal to) the first direction. The ratio of the width of the first electrode 15 to the width of the first transparent conductive layer 14 is 0.05-1.

[0073] According to the embodiment of the present utility model, Figure 1 As shown, the back-contact cell also includes a second electrode 16, disposed on the second transparent conductive layer 17 and extending along a second direction that intersects (e.g., is orthogonal to) the first direction. The ratio of the width of the second electrode 16 to the width of the second transparent conductive layer 17 is 0.05-1. This allows for a wider range of metallization options, including precious metals and base metals, and increases process compatibility.

[0074] In an illustrative embodiment, Figure 1 As shown, the first transparent conductive layer 14 is provided with a plurality of Figure 1 A first electrode 15 extends in a direction (as shown facing or away from the page, with the second direction being orthogonal to the first direction) on the second transparent conductive layer 17. Similarly, a second electrode 16 is provided on the second transparent conductive layer 17. The first and second electrodes 15, 16 (i.e., auxiliary grids), which can also be called fine grids or collector grid lines, are used to extract majority carriers from the doped regions of the solar cell. Specifically, the first and second electrodes 15, 16 have different polarities.

[0075] In an exemplary embodiment, the widths of the first and second electrodes 15 and 16 (i.e., W7 and W8) can be configured based on actual usage requirements. Wider widths facilitate carrier collection and reduce line resistance, but also increase the material required to manufacture the electrodes, thereby increasing manufacturing costs. Narrower widths have the opposite effect, which is not discussed further. Furthermore, the electrode widths can be comprehensively considered based on the materials used to manufacture the electrodes.

[0076] In an exemplary embodiment, the total number of first electrodes 15 and second electrodes 16 provided on a back-contact cell is the electrode number, which is calculated as follows: the electrode number = the short side length of the back-contact cell's silicon wafer / (W1 + W2, i.e., one pitch). Based on common silicon wafer sizes, the short side length of the silicon wafer includes, but is not limited to, 182 / 2, 191 / 2, and 210 / 2 mm, where the denominator "2" represents the number of silicon wafers cut. Furthermore, the electrode number includes, but is not limited to, X ± 2 electrodes, where X represents the number of pitches.

[0077] In an exemplary embodiment, the first electrode 15 and / or the second electrode 16 are made of, but not limited to, noble metals, base metals, and alloy materials.

[0078] For example, the width of an electrode made of a precious metal (including but not limited to silver, platinum or other precious metals) can be set to 20μm~500μm (i.e., 20μm≤W7≤500μm, and / or 20μm≤W8≤500μm); accordingly, the ratio of the width of the first electrode 15 to the first transparent conductive layer 14 is configured to be, but not limited to, 0.05~0.5 (i.e., 5%≤W7 / W3≤50%), and the second electrode 16 is similarly configured to be 5%≤W8 / W4≤50%.

[0079] For another example, the width of an electrode made of a base metal (including but not limited to copper, aluminum, titanium or other base metals) can be set to 20μm~2500μm (i.e., 20μm≤W7≤2500μm, and / or 20μm≤W8≤2500μm); accordingly, the ratio of the width of the first electrode 15 to the first transparent conductive layer 14 is configured to be, but not limited to, 0.05~1 (i.e., 5%≤W7 / W3≤100%), and the second electrode 16 is similarly configured to be 5%≤W8 / W4≤100%.

[0080] In a preferred embodiment, the width of the first electrode 15 includes, but is not limited to, being configured to be 40 μm to 120 μm (i.e., 40 μm ≤ W7 ≤ 120 μm), and the corresponding width of the second electrode 16 includes, but is not limited to, being configured to be 30 μm to 110 μm (i.e., 30 μm ≤ W7 ≤ 110 μm). Preferably, the width of the first electrode 15 is 40 μm, and the width of the second electrode 16 is 30 μm.

[0081] In another exemplary embodiment, not shown in the figure, the back-contact cell may further include a third electrode and a fourth electrode (not shown). The third and fourth electrodes, also known as busbars, are used to collect current collected by the first electrode 15 or the second electrode 16 (i.e., the secondary grid). Specifically, the third and fourth electrodes are spaced apart along the second direction and extend along the first direction, wherein the third electrode (and fourth electrode) are only connected to the secondary grid (i.e., the first electrode 15 or the second electrode 16) of the same polarity. Furthermore, the spacing between the third or fourth electrode located at the edge of the cell along the second direction and the edge of the cell is configured as m, and the spacing between adjacent busbars of the same polarity is configured as N, where m should satisfy 0.3N≤m≤0.7N and be symmetrical. It should be understood that the aforementioned third and fourth electrodes are optional.

[0082] For example, the back contact battery can adopt a main grid-free battery (ie, 0BB battery).

[0083] According to the embodiment of the present utility model, Figure 1As shown, a first opening is provided on the minority carrier region 20 , and a second opening is provided on the majority carrier region 21 , and an isolation region is formed between facing ends of the first opening and the second opening.

[0084] According to an embodiment of the present invention, not shown in the figures, the first transparent conductive layer 14 covers the first opening, the second transparent conductive layer 17 covers the second opening, and an insulating region is formed between the facing ends of the first transparent conductive layer 14 and the second transparent conductive layer 17. Thus, the provision of this insulating region can increase the carrier collection capability.

[0085] According to the embodiment of the present utility model, Figure 1 As shown, the second transparent conductive layer 17 also extends to the first doped semiconductor portion 13 .

[0086] In an illustrative embodiment, Figure 1 As shown, the first transparent conductive layer 14 covers at least a portion of the surface of the first doped semiconductor portion 13. In detail, an insulating layer 12 is further provided between the first transparent conductive layer 14 and the semiconductor substrate 11, and the insulating layer 12 includes but is not limited to a layer formed along the thickness direction and / or the first direction of the semiconductor substrate 11 (e.g., Figure 1 The first doped semiconductor portion 13 and the second doped semiconductor portion 18 are provided between the first doped semiconductor portion 13 and the second doped semiconductor portion 18. For example, an intrinsic amorphous silicon layer can be used to insulate the first doped semiconductor portion 13 and the second doped semiconductor portion 18.

[0087] In an illustrative embodiment, Figure 1 As shown, the first transparent conductive layer 14 and the second transparent conductive layer 17 are spaced apart (i.e., the first transparent conductive layer 14 and the second transparent conductive layer 17 are disconnected) to form an insulating region. Specifically, the width of the insulating region (i.e., W5) includes, but is not limited to, 20 μm to 200 μm (i.e., 20 ≤ W5 ≤ 200 μm) to ensure that leakage between the first doped semiconductor portion 13 and the second doped semiconductor portion 18 is prevented.

[0088] According to the embodiment of the present utility model, Figure 1 As shown, in the orthographic projection of the first surface, the projection of the insulating region coincides with the projection of the isolation region.

[0089] In an illustrative embodiment, Figure 1As shown, the first doped semiconductor portion 13 also extends over the portion of the second doped semiconductor portion 18 facing away from the semiconductor substrate 11. The stacked first doped semiconductor portion 13 and the second doped semiconductor portion 18 are spaced apart, which helps suppress leakage. Furthermore, the spacer region (i.e., W6) formed between the facing ends of the first opening and the second opening (e.g., the upper end of the first opening located below and the lower end of the second opening located above) defines the maximum width that can be set for the insulating region (i.e., W5 ≤ W6).

[0090] According to the embodiment of the present utility model, Figure 1 As shown, the width of the isolation region along the first direction is 20 μm to 400 μm.

[0091] According to the embodiment of the present utility model, Figure 1 As shown, the width of the insulating region along the first direction is 20 μm to 200 μm.

[0092] According to the embodiment of the present utility model, Figure 1 As shown, the ratio of the width of the insulating region to the width of the isolation region along the first direction is 0.2-1.

[0093] In an illustrative embodiment, Figure 1 As shown, the width of the spacer region (i.e., W6) includes, but is not limited to, being configured to be 20 μm to 400 μm (i.e., 80 ≤ W6 ≤ 200 μm). Furthermore, the ratio of the width of the insulating region to the width of the portion overlapping the spacer region includes, but is not limited to, being configured to be 0.2 to 1 (i.e., 20% ≤ W5 / W6 ≤ 100%).

[0094] In another exemplary embodiment, not shown in the figure, the insulating region may be provided in the minority carrier region 20. Specifically, the overlap ratio (W5 / W1) between the insulating region and the minority carrier region 20 includes, but is not limited to, being configured to be 0-20%.

[0095] In another exemplary embodiment, not shown in the figure, the insulating region may be provided in the multiple sub-regions 21. Specifically, the overlap ratio (W5 / W2) between the insulating region and the multiple sub-regions 21 includes, but is not limited to, being configured to be 0-20%.

[0096] Figure 2 It is a schematic longitudinal cross-sectional view of a back-contact battery according to another exemplary embodiment of the present invention.

[0097] According to the embodiment of the present utility model, Figure 2As shown, the first transparent conductive layer 14 covers a portion of the first opening, and the second transparent conductive layer 17 covers the second opening and extends to the first doped semiconductor portion 13. In the orthographic projection of the first surface, the portion between the projections of the first transparent conductive layer 14 and the second transparent conductive layer 17 forms an insulating region. This insulating region provides better insulation, reduces short circuits, and improves yield.

[0098] According to the embodiment of the present utility model, Figure 2 As shown, in the orthographic projection of the first surface (ie, the projection from left to right), the projection of the insulating region partially overlaps with the projection of the isolation region.

[0099] In an illustrative embodiment, Figure 2 As shown, the thickness of the second doped semiconductor portion 18 is greater than that of the first doped semiconductor portion 13, so that the second doped semiconductor portion 18 protrudes from the first doped semiconductor portion 13. Furthermore, the first transparent conductive layer 14 only covers a portion of the first opening. Based on this, the insulating region formed between the first transparent conductive layer 14 and the second transparent conductive layer 17 is located at the step formed by the edge of the second doped semiconductor portion 18. This insulating region provides good insulation, but because the first transparent conductive layer 14 only covers a portion of the first doped semiconductor portion 13, it may affect the collection of minority carriers.

[0100] Based on the inventive concept similar to the above-mentioned back-contact cell, the present invention also provides a photovoltaic module, not shown in the figures, which includes the above-mentioned back-contact cell.

[0101] It should also be noted that directional terms such as "upper," "lower," "front," "back," "left," and "right" mentioned in the embodiments are merely references to the drawings and are not intended to limit the scope of protection of the present invention. Throughout the drawings, identical elements are represented by identical or similar reference numerals. Conventional structures or configurations will be omitted where they may cause confusion in understanding the present invention.

[0102] The above describes embodiments of the present invention. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present invention. Although each embodiment has been described separately above, this does not mean that the measures in each embodiment cannot be used in combination to advantage. The scope of the present invention is defined by the appended claims and their equivalents. Without departing from the scope of the present invention, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present invention.

Claims

1. A back contact battery, characterized in that: include: A semiconductor substrate (11), wherein a first surface of the semiconductor substrate (11) comprises minority carrier regions (20) and majority carrier regions (21) alternately spaced along a first direction; A first doped semiconductor portion (13) is provided in the minority carrier region (20); a second doped semiconductor portion (18) disposed in the multi-sub-region (21), the second doped semiconductor portion (18) having a conductivity type opposite to that of the first doped semiconductor portion (13); a first transparent conductive layer (14) disposed on the first doped semiconductor portion (13); a second transparent conductive layer (17) disposed on the second doped semiconductor portion (18); The ratio of the widths of the first transparent conductive layer (14) and the minority carrier region (20) along the first direction is 0.8 to 1, and the ratio of the widths of the second transparent conductive layer (17) and the majority carrier region (21) along the first direction is 0.6 to 1.

2. The back contact battery according to claim 1, characterized in that The width of each of the minority carrier regions (20) along the first direction is 50 μm to 2500 μm, and the width of each of the majority carrier regions (21) along the first direction is 50 μm to 1500 μm.

3. The back contact battery according to claim 1, characterized in that The width of the minority sub-region (20) along the first direction is configured to be greater than the width of the majority sub-region (21) along the first direction; The ratio of the widths of the first transparent conductive layer (14) and the second transparent conductive layer (17) along the first direction is greater than 1 and less than 5.

4. The back contact battery according to claim 1, characterized in that The ratio of the thickness of the second transparent conductive layer (17) to the thickness of the first transparent conductive layer (14) is 1.4-1.

8.

5. The back contact battery according to claim 1, characterized in that It also includes a first electrode (15), which is arranged on the first transparent conductive layer (14) and extends along a second direction, wherein the second direction intersects with the first direction; The ratio of the width of the first electrode (15) to the width of the first transparent conductive layer (14) along the first direction is 0.05-1.

6. The back contact battery according to claim 1, characterized in that It also includes a second electrode (16), which is arranged on the second transparent conductive layer (17) and extends along a second direction, wherein the second direction intersects with the first direction; The ratio of the widths of the second electrode (16) and the second transparent conductive layer (17) along the first direction is 0.05-1.

7. The back contact cell according to any one of claims 1 to 6, characterized in that A first opening is provided on the minority carrier region (20), and a second opening is provided on the majority carrier region (21), wherein a spacing region is formed between facing ends of the first opening and the second opening.

8. The back contact battery according to claim 7, characterized in that The first transparent conductive layer (14) covers the first opening, the second transparent conductive layer (17) covers the second opening, and an insulating region is formed between the facing ends of the first transparent conductive layer (14) and the second transparent conductive layer (17).

9. The back contact battery according to claim 8, characterized in that The second transparent conductive layer (17) also extends to the first doped semiconductor portion (13).

10. The back contact battery according to claim 8, characterized in that In an orthographic projection of the first surface, a projection of the insulating region coincides with a projection of the spacer region.

11. The back contact battery according to claim 7, characterized in that The first transparent conductive layer (14) covers a portion of the first opening, and the second transparent conductive layer (17) covers the second opening and extends to the first doped semiconductor portion (13); In the orthographic projection of the first surface, a portion between the projections of the first transparent conductive layer (14) and the second transparent conductive layer (17) forms an insulating region.

12. The back contact battery according to claim 11, characterized in that In an orthographic projection of the first surface, a projection of the insulating region partially overlaps with a projection of the spacer region.

13. The back contact battery according to claim 7, characterized in that A width of the spacer along the first direction is 20 μm to 400 μm.

14. The back contact cell according to any one of claims 8 to 12, characterized in that A width of the insulating region along the first direction is 20 μm to 200 μm.

15. The back contact cell according to any one of claims 8 to 12, characterized in that A ratio of the widths of the insulating region and the spacing region along the first direction is 0.2-1.

16. The back contact cell according to any one of claims 1 to 6, characterized in that The sum of the widths of the adjacent minority carrier regions (20) and majority carrier regions (21) along the first direction is 300 μm to 3000 μm.

17. A photovoltaic module, characterized in that: Comprising a back contact cell as claimed in any one of claims 1 to 16.

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