6U VPX data processing 10-gigabit interface card based on Hisilicon processor

Abstract

The utility model relates to a 6U VPX data processing 10-gigabit interface card based on Hisilicon processors. The 6U VPX data processing 10-gigabit interface card comprises a first Hisilicon processor, a second Hisilicon processor, an FPGA, a network switch chip, a storage module, a 10-gigabit interface transceiver module and other interface modules. The FPGA is connected with the first Hisilicon processor and the second Hisilicon processor, the first Hisilicon processor and the second Hisilicon processor are both connected with the storage module, and the FPGA is connected with the 10-gigabit interface transceiver module and the network switch chip; and the first Hisilicon processor, the second Hisilicon processor and the FPGA are also connected with other interface modules. Compared with an implementation mode of interconnection of board cards with different functions, the system has the advantages that the design layout size is small, the bandwidth, the response speed, the signal quality and the like are superior to those of an interconnection building system among the board cards, the system has great advantages in the aspects of life cycle, cost performance and the like, and the defect that signal transmission among different board cards is unstable is overcome.

Description

Technical Field

[0001] The utility model relates to the field of electronic devices, and in particular to a 6U VPX data processing 10G interface card based on a HiSilicon processor. Background Art

[0002] Since the country has gradually attached importance to information security, it has begun to gradually upgrade the localization of equipment in the fields of information security, industrial control, etc.; the processor, as a core component of a system, has a large number of applications in key fields such as military, communications, and industrial control; in order to ensure the core's independent control, a product with high flexibility, short development cycle, good interchangeability, and stable and reliable advantages is needed.

[0003] Currently, image processing cards and data transmission cards on the market are usually designed separately and then connected together through a local area network. In some scenarios, the overall size of the product needs to be taken into consideration, and they need to be designed together to process related data. Existing HiSilicon processors and high-speed 10G network interfaces are generally designed on different boards, and then data is exchanged through switch boards. This design has a low degree of integration and is costly. Utility Model Content

[0004] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a 6U VPX data processing 10G interface card based on HiSilicon processor, which solves the shortcomings of the prior art.

[0005] The purpose of the utility model is achieved by the following technical solutions: a 6U VPX data processing 10G interface card based on HiSilicon processor, which includes a first HiSilicon processor, a second HiSilicon processor, an FPGA, a network switch chip, a storage module, a 10G interface transceiver module and other interface modules;

[0006] The FPGA is connected to the first HiSilicon processor and the second HiSilicon processor, both of which are connected to the storage module, and the FPGA is connected to the 10G interface transceiver module and the network switch chip; the first HiSilicon processor, the second HiSilicon processor and the FPGA are also connected to other interface modules.

[0007] The storage module includes a first DDR4, a second DDR4, a first eMMC, and a second eMMC; the first DDR4 and the first eMMC are connected to the first HiSilicon processor, and the second DDR4 and the second eMMC are connected to the second HiSilicon processor.

[0008] The other interface modules include a first network PHY, a second network PHY, an SPI Flash and a debug serial port; the network switch chip is connected to the first network PHY and the second network PHY respectively, the first network PHY is connected to the first HiSilicon processor, and the second network PHY is connected to the second HiSilicon processor; the first HiSilicon processor and the second HiSilicon processor are both connected to the debug serial port, and the FPGA is connected to the SPI Flash.

[0009] The 10G interface transceiver module includes a 10G optical transceiver integrated module and a multi-channel 10G optical transceiver module; the FPGA is connected to the 10G optical transceiver integrated module and the multi-channel 10G optical transceiver module.

[0010] The present invention has the following advantages: a 6U VPX data processing 10G interface card based on HiSilicon processor has a small design layout size compared to the implementation method of interconnecting boards with different functions, and is superior to the board-to-board interconnection system in terms of bandwidth, response speed, signal quality, etc. It has great advantages in terms of life cycle and cost performance, and overcomes the disadvantage of unstable signal transmission between different boards; in addition, it is implemented in a dual-processor manner, which can meet different needs according to the requirements of application scenario reliability, business computing volume, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a structural diagram of the present utility model. DETAILED DESCRIPTION

[0012] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the detailed description of the embodiments of the present application provided below in conjunction with the drawings is not intended to limit the scope of protection of the present application for which protection is sought, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application. The present utility model is further described below in conjunction with the drawings.

[0013] The utility model specifically relates to a 6U VPX data processing 10G interface card based on a HiSilicon processor. Utilizing the flexible scalability and high reusability of highly integrated modules, the card adopts a design scheme of a HiSilicon Hi3559 processor + XC7V690T + network switch chip. It has multiple interfaces such as PCIe, GTH, 10G, 1G, and UART. The required interfaces can be realized through network interconnection, making it more convenient to upgrade, replace, and maintain the entire product. Its flexibility, maintainability, and life cycle are all higher than those of other types of products.

[0014] like Figure 1 As shown, it specifically includes a first HiSilicon processor, a second HiSilicon processor, an FPGA, a network switch chip, a storage module, a 10G interface transceiver module and other interface modules;

[0015] The FPGA is connected to HiSilicon processor A and HiSilicon processor B. HiSilicon processor A and the second HiSilicon processor B are both connected to the storage module. The FPGA is connected to the 10G interface transceiver module and the network switch chip. HiSilicon processor A, HiSilicon processor B and FPGA are also connected to other interface modules.

[0016] Among them, HiSilicon processor A and HiSilicon processor B are both Hi3559 processors, and the FPGA model is XC7V690T; System A consists of HiSilicon Hi3559 processor A, supporting 8GB DDR4 memory particles, and supporting eMMC storage chips.

[0017] Furthermore, other interface modules include a first network PHY, a second network PHY, an SPI Flash, and a debug serial port; the network switch chip is connected to the first network PHY and the second network PHY respectively, the first network PHY is connected to HiSilicon processor A, and the second network PHY is connected to HiSilicon processor B; HiSilicon processor A and the second HiSilicon processor B are both connected to the debug serial port, and the FPGA is connected to the SPI Flash.

[0018] Furthermore, the 10G interface transceiver module includes a 10G optical transceiver integrated module and a multi-channel 10G optical transceiver module; the FPGA is connected to the 10G optical transceiver integrated module and the multi-channel 10G optical transceiver module.

[0019] Furthermore, the serial port on the FPGA is expanded through the PCIEx2 bus; the debug serial ports of system A and system B are both brought out from the front panel connector for easy debugging; system A and system B are simultaneously connected to the FPGA, PCIEx2, and LVDS; upgrades to system A, system B, and FPGA can be remotely updated through the network switch chip.

[0020] Systems A and B are configured in redundant mode to process data: a high-performance FPGA sends and receives relevant image data through 10G optical transceiver module A, and sends the same set of image data to HiSilicon processor A and HiSilicon processor B simultaneously through the LVDS interface for processing. The processed image data is sent to the FPGA through the PCIEx2 bus, and the FPGA then sends it to the next-level processing unit through the GTH interface for processing.

[0021] Systems A and B are configured to process data in independent mode: a high-performance FPGA sends and receives relevant image data through 10G optical transceiver module A, and sends the data to HiSilicon processor A and HiSilicon processor B for processing via the LVDS interface according to the image data type. The processed image data is then transmitted back to the FPGA via the PCIEx2 bus, and the FPGA then sends the data to the next-level processing unit for recognition and processing via the GTH interface.

[0022] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the form disclosed herein and should not be construed as excluding other embodiments. Instead, the present invention may be used in various other combinations, modifications, and improvements, and may be modified within the scope of the concept described herein through the above teachings or techniques or knowledge in the relevant fields. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention shall be within the scope of protection of the appended claims.

Claims

1. A 6U VPX data processing 10G interface card based on a HiSilicon processor, characterized by: It includes the first HiSilicon processor, the second HiSilicon processor, FPGA, network switch chip, storage module, 10G interface transceiver module and other interface modules; The FPGA is connected to the first HiSilicon processor and the second HiSilicon processor, both of which are connected to the storage module, and the FPGA is connected to the 10G interface transceiver module and the network switch chip; the first HiSilicon processor, the second HiSilicon processor and the FPGA are also connected to other interface modules.

2. The HiSilicon processor-based 6U VPX data processing 10G interface card according to claim 1, characterized in that: The storage module includes a first DDR4, a second DDR4, a first eMMC, and a second eMMC; the first DDR4 and the first eMMC are connected to the first HiSilicon processor, and the second DDR4 and the second eMMC are connected to the second HiSilicon processor.

3. The HiSilicon processor-based 6U VPX data processing 10G interface card according to claim 1, characterized in that: The other interface modules include a first network PHY, a second network PHY, an SPI Flash and a debug serial port; the network switch chip is connected to the first network PHY and the second network PHY respectively, the first network PHY is connected to the first HiSilicon processor, and the second network PHY is connected to the second HiSilicon processor; the first HiSilicon processor and the second HiSilicon processor are both connected to the debug serial port, and the FPGA is connected to the SPI Flash.

4. The HiSilicon processor-based 6U VPX data processing 10G interface card according to claim 1, characterized in that: The 10G interface transceiver module includes a 10G optical transceiver integrated module and a multi-channel 10G optical transceiver module; the FPGA is connected to the 10G optical transceiver integrated module and the multi-channel 10G optical transceiver module.

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