Solar cell
By adopting P-type and N-type tunnel passivation contact structures on the back of the silicon substrate of the BC cell and adjusting the thickness and doping concentration of the doped crystalline silicon layer, the problems of low BC cell yield and low back-side light absorption were solved, and the cell efficiency was improved and the optical absorption was enhanced.
Patent Information
- Application Number
- CN202422638963.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-30
- Publication Date
- 2025-09-16
- Estimated Expiration
- 2034-10-30
AI Technical Summary
The low yield and back-side light absorption rate of existing BC batteries restrict the development of batteries.
P-type tunneling passivation contact structure and N-type tunneling passivation contact structure are used to form a good passivation effect on the back side of the silicon substrate, and the metal electrodes are all set on the back side. By adjusting the thickness and doping concentration of the doped crystalline silicon layer, electrode burn-through is avoided and the parasitic absorption of light by the film layer is reduced.
It improves the efficiency of BC batteries, enhances the optical absorption of batteries, and increases the short-circuit current, thereby improving the overall performance of the batteries.
Smart Images
Figure CN223349017U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the field of photovoltaic cells, in particular to a solar cell. Background Art
[0002] Driven by the theme of "reducing costs and increasing efficiency", photovoltaic cells have undergone technological iterations. The efficiency of the current mainstream product PERC cell is approaching the theoretical limit and the cost reduction is slowing down. The N-type cell with advantages such as high conversion efficiency, low temperature coefficient and low photo-induced degradation will become the direction of the next iterative development.
[0003] The back contact cell (BC cell) is a new type of N-type cell. P-type and N-type doped structures are fabricated on the back of the cell, with a first electrode and a second electrode formed on the P-type and N-type doped structures, respectively. The positive and negative electrodes of a BC cell are both on the back of the cell, leaving no metal electrode shading the front. This avoids light loss from metal electrode shading, greatly improving the cell's optical absorption and achieving good short-circuit current. BC cells also eliminate the front-surface emitter, reducing front-surface recombination losses.
[0004] However, the low yield and backside light absorption rate of BC batteries restrict the development of batteries.
[0005] In view of this, it is necessary to provide a new solar cell to solve the above technical problems. Utility Model Content
[0006] The purpose of the utility model is to provide a solar cell to solve the deficiencies in the prior art, thereby improving the cell yield and bifaciality, and improving the cell efficiency.
[0007] In order to achieve one of the above purposes, the present invention adopts the following technical solutions:
[0008] A solar cell comprising:
[0009] A silicon substrate having a first region and a second region spaced apart from each other on its back side;
[0010] The tunneling layer includes a first tunneling layer located in the first region and a second tunneling layer located in the second region;
[0011] The P-type doped crystalline silicon layer comprises a first P-type doped crystalline silicon layer and a second P-type doped crystalline silicon layer located on the back side of the first tunneling layer, wherein the thickness of the first P-type doped crystalline silicon layer is greater than that of the second P-type doped crystalline silicon layer;
[0012] The N-type doped crystalline silicon layer comprises a first N-type doped crystalline silicon layer and a second N-type doped crystalline silicon layer located on the back side of the second tunneling layer, wherein the thickness of the first N-type doped crystalline silicon layer is greater than that of the second N-type doped crystalline silicon layer;
[0013] a first electrode, contacting the first P-type doped crystalline silicon layer;
[0014] The second electrode contacts the first N-type doped crystalline silicon layer.
[0015] In one embodiment, the thickness of the first P-type doped crystalline silicon layer is 1.1 to 3.1 times the thickness of the second P-type doped crystalline silicon layer.
[0016] In one embodiment, the thickness of the first N-type doped crystalline silicon layer is 1.1 to 3.1 times the thickness of the second N-type doped crystalline silicon layer.
[0017] In one embodiment, the first P-type doped crystalline silicon layer and the first N-type doped crystalline silicon layer have the same thickness.
[0018] In one embodiment, the second P-type doped crystalline silicon layer and the second N-type doped crystalline silicon layer have the same thickness.
[0019] In one embodiment, the first P-type doped crystalline silicon layer is located in the middle of the first region; or the second P-type doped crystalline silicon layer is disposed around the first P-type doped crystalline silicon layer.
[0020] In one embodiment, the first N-type doped crystalline silicon layer is located in the middle of the second region; or the second N-type doped crystalline silicon layer is disposed around the first N-type doped crystalline silicon layer.
[0021] In one embodiment, the doping concentration of the first P-type doped crystalline silicon layer is greater than the doping concentration of the second P-type doped crystalline silicon layer.
[0022] In one embodiment, the doping concentration of the first N-type doped crystalline silicon layer is greater than the doping concentration of the second N-type doped crystalline silicon layer.
[0023] In one embodiment, the tunneling layer covers the entire back side of the silicon substrate.
[0024] In one embodiment, the tunneling layer has a thickness of 0.5 nm to 2 nm.
[0025] In one embodiment, the tunneling layer is a silicon oxide layer or a silicon carbide layer, and the thickness of the tunneling layer is 0.5 nm to 2 nm.
[0026] In one embodiment, the width of the spacer between the first region and the second region is 10 μm to 500 μm.
[0027] In one embodiment, the solar cell further includes a back anti-reflection layer located on the back side of the P-type doped crystalline silicon layer and the N-type doped crystalline silicon layer, the first electrode passes through the back anti-reflection layer and contacts the P-type doped crystalline silicon layer, and the second electrode passes through the back anti-reflection layer and contacts the P-type doped crystalline silicon layer.
[0028] In one embodiment, the thickness of the back anti-reflection layer is 70 nm to 90 nm, and the reflectivity of the back anti-reflection layer is 30% to 40%.
[0029] In one embodiment, the front surface of the silicon substrate has a suede structure, and the suede reflectivity is 7% to 10%.
[0030] In one embodiment, the solar cell further comprises a front passivation layer located on the front side of the silicon substrate and a front anti-reflection layer located on the front side of the front passivation layer. The thickness of the front anti-reflection layer is 70 nm to 90 nm.
[0031] Compared with the prior art, the solar cell of the present invention uses a P-type tunneling passivation contact structure and an N-type tunneling passivation contact structure to form a good passivation effect on the back of the silicon substrate, and the metal electrodes are all arranged on the back, which can improve the efficiency of the back-contact cell. In addition, the thickness of the doped crystalline silicon layer in contact with the electrode is greater than the thickness of the doped crystalline silicon layer in the non-metallic area. On the one hand, it prevents the electrode from burning through the doped crystalline silicon layer and contacting the silicon substrate during the sintering process. On the other hand, thinning the thickness of the doped crystalline silicon layer in the non-metallic area can reduce the parasitic absorption of long-wave light by the film layer, improve the effective absorption of incident light, and help increase the short-circuit current, thereby improving the battery efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] Figure 1 It is a schematic structural diagram of a solar cell in one embodiment of the present invention;
[0033] Figure 2 yes Figure 1 A partial enlarged view of
[0034] Figure 3 It is a schematic structural diagram of a solar cell in one embodiment of the present invention;
[0035] Figure 4 yes Figure 3 A partial enlarged view of .
[0036] Reference numerals:
[0037] 100. Solar cell, 10. Silicon substrate; 20. Tunneling layer; 21. First tunneling layer; 22. Second tunneling layer; 30. P-type doped crystalline silicon layer; 31. First P-type doped crystalline silicon layer; 32. Second P-type doped crystalline silicon layer; 40. N-type doped crystalline silicon layer; 41. First N-type doped crystalline silicon layer; 42. Second N-type doped crystalline silicon layer; 50. Back anti-reflection layer; 60. Front passivation layer; 70. Front anti-reflection layer; 81. First electrode; 82. Second electrode. DETAILED DESCRIPTION
[0038] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.
[0039] Please refer to Figures 1 to 4 FIG. 1 shows a solar cell 100 according to a preferred embodiment of the present invention.
[0040] The solar cell 100 includes a silicon substrate 10, a P-type tunneling passivation contact structure, an N-type tunneling passivation contact structure, a first electrode 81, and a second electrode 82 located on the back side of the silicon substrate 10. The front side of the silicon substrate 10 is free of metal electrodes, providing a large light-receiving area, thereby improving the efficiency of the solar cell 100.
[0041] The silicon substrate 10 is an N-type single crystal silicon wafer, or may be an N-type single crystal silicon wafer. Its back side has a first region for preparing a P-type tunnel passivation contact structure, a second region for preparing an N-type tunnel passivation contact structure, and a spacer region between the first region and the second region.
[0042] The first and second regions are alternately arranged in an interdigitated manner and separated by a spacer region having a width of 10 μm to 500 μm to prevent short circuit leakage between the P-type tunnel passivation contact structure and the N-type tunnel passivation contact structure.
[0043] In one embodiment, the front surface of the silicon substrate 10 has a suede structure, and the reflectivity of the suede structure is 7% to 10%. The suede structure can reduce light reflection, increase the front light absorption rate, and thus improve the battery efficiency.
[0044] The back side of the silicon substrate 10 is a planar structure, the tower base size is 15 μm, the reflectivity is about 40%, the surface has few composite points, and is conducive to forming a tunnel passivation contact structure.
[0045] The silicon substrate 10 having a textured surface on the front side and a flat surface on the back side can be formed by using a double-sided texturing and back side polishing process.
[0046] In one embodiment, a mixed solution of potassium hydroxide (KOH) and hydrogen peroxide (H2O2) is first used to remove the damaged layer on the surface of the silicon substrate 10. Then, a sodium hydroxide (NaOH) solution or a KOH solution is used to texturize the silicon wafer, forming a pyramidal texture on the surface. The pyramidal base size is controlled to be approximately 2 μm, and the reflectivity is controlled to be approximately 8%. Finally, the back side of the silicon substrate is single-sided polished using a chain alkali polishing machine. The alkali polishing solution is a commonly used polishing alkali solution in the art, such as a NaOH solution or a KOH solution mixed with a polishing additive.
[0047] The P-type tunneling passivation contact structure is located in the first region and includes a first tunneling layer 21 and a P-type doped crystalline silicon layer 30 located on the back of the first tunneling layer 21 .
[0048] The first tunneling layer 21 is a silicon oxide layer (SiOx) or a silicon carbide layer (SiC). The thickness of the first tunneling layer 21 is 0.5 nm to 2 nm, preferably 1 nm to 1.5 nm.
[0049] The P-type doped crystalline silicon layer 30 includes a first P-type doped crystalline silicon layer 31 located in the metal region and a second P-type doped crystalline silicon layer 32 located in the non-metal region. The first electrode 81 is located on the back side of the first P-type doped crystalline silicon layer 31 and contacts the first P-type doped crystalline silicon layer 31 .
[0050] In one embodiment, the first P-type doped crystalline silicon layer 31 is located in the middle of the first region; or the second P-type doped crystalline silicon layer 32 is disposed around the first P-type doped crystalline silicon layer 31 .
[0051] In one embodiment, the thickness of the first P-type doped crystalline silicon layer 31 is greater than the thickness of the second P-type doped crystalline silicon layer 32. On the one hand, increasing the thickness of the first P-type doped crystalline silicon layer 31 prevents the first electrode 81 from burning through the first P-type doped crystalline silicon layer 31 and contacting the silicon substrate 10 during the sintering process. On the other hand, reducing the thickness of the second P-type doped crystalline silicon layer 32 can reduce the parasitic absorption of long-wavelength light by the film layer, thereby improving the effective absorption of incident light, thereby increasing short-circuit current and thereby improving battery efficiency.
[0052] In one embodiment, the thickness of the first P-type doped crystalline silicon layer 31 is 1.1 to 3.1 times the thickness of the second P-type doped crystalline silicon layer 32 .
[0053] In one embodiment, the first P-type doped crystalline silicon layer 31 has a thickness of 90 nm to 130 nm, for example, 120 nm, and a width of 1 μm to 100 μm, for example, about 50 μm. The second P-type doped crystalline silicon layer 32 has a thickness of 60 nm to 80 nm, and a width of 1 μm to 1000 μm, for example, 500 μm.
[0054] In one embodiment, the doping concentration of the first P-type doped crystalline silicon layer 31 is greater than the doping concentration of the second P-type doped crystalline silicon layer 32. This concentration is set in the first region to form a selective emitter. The high doping concentration of the first P-type doped crystalline silicon layer 31 in the metal region improves metal contact, thereby increasing open-circuit voltage and fill factor. The low doping concentration of the second P-type doped crystalline silicon layer 32 in the non-metal region can reduce dead layer and Auger recombination, thereby increasing open-circuit voltage.
[0055] In one embodiment, the doping concentration of the first P-type doped crystalline silicon layer 31 is 1E19 atoms / cm 3 ~5E19 atoms / cm 3 , for example 4E19atoms / cm 3 The doping concentration of the second P-type doped crystalline silicon layer 32 is 3E18atoms / cm 3 ~8E18atoms / cm 3 , for example 6E18atoms / cm 3 .
[0056] The N-type tunneling passivation contact structure is located in the second region and includes a second tunneling layer 22 and an N-type doped crystalline silicon layer 40 located on the back of the second tunneling layer 22 .
[0057] The second tunneling layer 22 is a silicon oxide layer or a silicon carbide layer, and the thickness of the second tunneling layer 22 is 0.5 nm to 2 nm.
[0058] The N-type doped crystalline silicon layer 40 includes a first N-type doped crystalline silicon layer 41 in the metal region and a second N-type doped crystalline silicon layer 42 in the non-metal region. The second electrode 82 is located on the back side of the first N-type doped crystalline silicon layer 41 and contacts the first N-type doped crystalline silicon layer 41 .
[0059] In one embodiment, the first N-type doped crystalline silicon layer 41 is located in the middle of the second region; or the second N-type doped crystalline silicon layer 42 is disposed around the first N-type doped crystalline silicon layer 41 .
[0060] In one embodiment, the thickness of the first N-type doped crystalline silicon layer 41 is greater than the thickness of the second N-type doped crystalline silicon layer 42. On the one hand, increasing the thickness of the first N-type doped crystalline silicon layer 41 prevents the second electrode 82 from burning through the first N-type doped crystalline silicon layer 41 and contacting the silicon substrate 10 during the sintering process. On the other hand, reducing the thickness of the second N-type doped crystalline silicon layer 42 can reduce the parasitic absorption of long-wavelength light by the film layer, thereby improving the effective absorption of incident light, thereby increasing short-circuit current and thereby improving battery efficiency.
[0061] In one embodiment, the thickness of the first N-type doped crystalline silicon layer 41 is 1.1 to 3.1 times the thickness of the second N-type doped crystalline silicon layer 42 .
[0062] In one embodiment, the first N-type doped crystalline silicon layer 41 has a thickness of 90 nm to 130 nm, for example, 120 nm, and a width of 0 to 100 μm, for example, approximately 50 μm. The second N-type doped crystalline silicon layer 42 has a thickness of 40 nm to 80 nm, for example, 60 nm, and a width of 0 to 1000 μm, for example, 500 μm.
[0063] In one embodiment, the thickness of the first P-type doped crystalline silicon layer 31 is consistent with that of the first N-type doped crystalline silicon layer 41; and / or the thickness of the second P-type doped crystalline silicon layer 32 is consistent with that of the second N-type doped crystalline silicon layer 42. This facilitates the preparation of the first electrode 81 and the second electrode 82.
[0064] In one embodiment, the doping concentration of the first N-type doped crystalline silicon layer 41 is greater than the doping concentration of the second N-type doped crystalline silicon layer 42. This concentration is set in the second region to form a selective emitter. The high doping concentration of the first N-type doped crystalline silicon layer 41 in the metal region improves metal contact, thereby increasing open-circuit voltage and fill factor. The low doping concentration of the second N-type doped crystalline silicon layer 42 in the non-metal region can reduce dead layer and Auger recombination, thereby increasing open-circuit voltage.
[0065] In one embodiment, the doping concentration of the first N-type doped crystalline silicon layer 41 is 1E21 atoms / cm 3 ~5E21atoms / cm 3 , for example 5E21 atoms / cm 3 The doping concentration of the second N-type doped crystalline silicon layer 42 is 3E20atoms / cm 3 ~8E20atoms / cm 3 , for example 5E20atoms / cm 3 .
[0066] In addition, the first tunneling layer 21 and the second tunneling layer 22 may be arranged in the following manner.
[0067] In one embodiment, if Figure 1 and Figure 2 As shown, the first tunneling layer 21 and the second tunneling layer 22 are respectively part of the tunneling layer 20 formed on the entire back side of the silicon substrate 10, that is, the first tunneling layer 21 and the second tunneling layer 22 and the tunneling layer 20 located in the spacer area constitute a complete film layer, which passivates the entire back side of the silicon substrate 10.
[0068] Based on this structural design, the solar cell 100 can be formed using the following method:
[0069] A tunneling layer 20 is formed on the back side of the silicon substrate 10 .
[0070] A first boron-doped silicon slurry and a second boron-doped silicon slurry are formed in the first region to form the first P-type doped crystalline silicon layer 31 and the second P-type doped crystalline silicon layer 32 respectively; the corresponding first P-type doped crystalline silicon layer 31 and the second P-type doped crystalline silicon layer 32 are obtained by adjusting the doping concentration and thickness of the first boron-doped silicon slurry and the second boron-doped silicon slurry.
[0071] A first phosphorus-doped silicon slurry and a second phosphorus-doped silicon slurry are formed in the second region to form the first N-type doped crystalline silicon layer 41 and the second N-type doped crystalline silicon layer 42, respectively. The first N-type doped crystalline silicon layer 41 and the second N-type doped crystalline silicon layer 42 are obtained by controlling the doping concentration and thickness of the first phosphorus-doped silicon slurry and the second phosphorus-doped silicon slurry.
[0072] High-temperature annealing, with an annealing time of 1800s to 10800s at a temperature of 800°C to 1050°C, forms alternately spaced P-type tunneling passivation contact structures and N-type tunneling passivation contact structures, with a natural spacer region between them. This eliminates the need for multiple masking and laser film opening, significantly simplifying process steps and costs.
[0073] Of course, conventional processes may also be used to prepare the P-type doped crystalline silicon layer 30 and the N-type doped crystalline silicon layer 40 .
[0074] In another embodiment, if Figure 3 and Figure 4 As shown, the second tunneling layer 22 and the first tunneling layer 21 are two independent film layers, which are disconnected and can be formed separately under the action of a mask. One film layer can be formed first and then the film layer in the spacer area can be removed.
[0075] The solar cell 100 further includes a backside anti-reflection layer 50 located on the backside of the P-type doped crystalline silicon layer 30 and the N-type doped crystalline silicon layer 40 to reduce backside reflectivity and increase backside light absorption, thereby improving the cell efficiency of the double-glass module.
[0076] In one embodiment, the back anti-reflection layer 50 is selected from one or more laminated films of silicon nitride, silicon oxynitride, and silicon oxide. The thickness of the back anti-reflection layer 50 is 70nm to 90nm, for example, 80nm; the reflectivity of the back anti-reflection layer 50 is 30% to 40%.
[0077] The first electrode 81 passes through the back anti-reflection layer 50 and contacts the first P-type doped crystalline silicon layer 31 , and the second electrode 82 passes through the back anti-reflection layer 50 and contacts the first N-type doped crystalline silicon layer 41 .
[0078] In addition, the solar cell 100 further includes a front passivation layer 60 located on the front surface of the silicon substrate 10 to passivate the front surface of the silicon substrate 10 and reduce interface recombination.
[0079] In one embodiment, the front passivation layer 60 is an aluminum oxide layer with a thickness of 1 nm to 20 nm.
[0080] The solar cell 100 further includes a front anti-reflection layer 70 located on the front of the front passivation layer 60. The front anti-reflection layer 70 is a laminated film selected from one or more of silicon nitride, silicon oxide, and silicon oxynitride. The thickness of the front anti-reflection layer 70 is 70 nm to 90 nm.
[0081] The front anti-reflection layer 70 is selected from one or more laminated films of silicon nitride, silicon oxynitride, and silicon oxide, with a thickness of 60nm to 130nm, which reduces reflectivity and improves light utilization.
[0082] In one embodiment, the front anti-reflection layer 70 and the back anti-reflection layer 50 are made of the same material and have the same thickness, and both can also be deposited in the same process.
[0083] In summary, the solar cell 100 of the present invention utilizes a P-type tunneling passivation contact structure and an N-type tunneling passivation contact structure to achieve a good passivation effect on the back side of the silicon substrate 10, and both metal electrodes are disposed on the back side, thereby improving the efficiency of the back-contact cell. Furthermore, the thickness of the doped crystalline silicon layer in contact with the electrode is greater than the thickness of the doped crystalline silicon layer in the non-metallic region. This prevents the electrode from burning through the doped crystalline silicon layer and contacting the silicon substrate 10 during the sintering process. Furthermore, reducing the thickness of the doped crystalline silicon layer in the non-metallic region can reduce the parasitic absorption of long-wavelength light by the film layer, thereby improving the effective absorption of incident light, thereby increasing the short-circuit current and, consequently, the cell efficiency.
[0084] The above describes in detail the structure, features and effects of the present invention based on the embodiments shown in the drawings. The above is only a preferred embodiment of the present invention, but the scope of implementation of the present invention is not limited to what is shown in the drawings. Any changes made in accordance with the concept of the present invention, or modifications to equivalent embodiments with equivalent changes, which do not exceed the spirit covered by the description and drawings, should be within the scope of protection of the present invention.
Claims
1. A solar cell, characterized in that: include: A silicon substrate having a first region and a second region spaced apart from each other on its back side; The tunneling layer includes a first tunneling layer located in the first region and a second tunneling layer located in the second region; The P-type doped crystalline silicon layer comprises a first P-type doped crystalline silicon layer and a second P-type doped crystalline silicon layer located on the back side of the first tunneling layer, wherein the thickness of the first P-type doped crystalline silicon layer is greater than that of the second P-type doped crystalline silicon layer; The N-type doped crystalline silicon layer comprises a first N-type doped crystalline silicon layer and a second N-type doped crystalline silicon layer located on the back side of the second tunneling layer, wherein the thickness of the first N-type doped crystalline silicon layer is greater than that of the second N-type doped crystalline silicon layer; a first electrode, contacting the first P-type doped crystalline silicon layer; The second electrode contacts the first N-type doped crystalline silicon layer.
2. The solar cell according to claim 1, wherein: The thickness of the first P-type doped crystalline silicon layer is 1.1 to 3.1 times the thickness of the second P-type doped crystalline silicon layer; or the thickness of the first P-type doped crystalline silicon layer is 90 nm to 130 nm, and the thickness of the second P-type doped crystalline silicon layer is 60 nm to 80 nm; And / or, the thickness of the first N-type doped crystalline silicon layer is 1.1 to 3.1 times the thickness of the second N-type doped crystalline silicon layer; or the thickness of the first N-type doped crystalline silicon layer is 90 nm to 130 nm, and the thickness of the second N-type doped crystalline silicon layer is 40 nm to 80 nm.
3. The solar cell according to claim 1, wherein: The thickness of the first P-type doped crystalline silicon layer is consistent with that of the first N-type doped crystalline silicon layer; and / or The second P-type doped crystalline silicon layer and the second N-type doped crystalline silicon layer have the same thickness.
4. The solar cell according to claim 1, wherein: The first P-type doped crystalline silicon layer is located in the middle of the first region; or the second P-type doped crystalline silicon layer is arranged around the first P-type doped crystalline silicon layer; And / or, the first N-type doped crystalline silicon layer is located in the middle of the second region; or the second N-type doped crystalline silicon layer is arranged around the first N-type doped crystalline silicon layer.
5. The solar cell according to claim 1, wherein: The doping concentration of the first P-type doped crystalline silicon layer is greater than the doping concentration of the second P-type doped crystalline silicon layer; and / or The doping concentration of the first N-type doped crystalline silicon layer is greater than the doping concentration of the second N-type doped crystalline silicon layer.
6. The solar cell according to claim 1, wherein The tunneling layer covers the entire back side of the silicon substrate.
7. The solar cell according to claim 1, wherein: The thickness of the tunneling layer is 0.5 nm to 2 nm; Alternatively, the tunneling layer is a silicon oxide layer or a silicon carbide layer, and the thickness of the tunneling layer is 0.5 nm to 2 nm.
8. The solar cell according to claim 1, wherein: The width of the spacer between the first region and the second region is 10 μm to 500 μm.
9. The solar cell according to claim 1, wherein: The solar cell further includes a back anti-reflection layer located on the back sides of the P-type doped crystalline silicon layer and the N-type doped crystalline silicon layer, the first electrode passes through the back anti-reflection layer and contacts the P-type doped crystalline silicon layer, and the second electrode passes through the back anti-reflection layer and contacts the P-type doped crystalline silicon layer; in The thickness of the back anti-reflection layer is 70 nm to 90 nm, and the reflectivity of the back anti-reflection layer is 30% to 40%.
10. The solar cell according to claim 1, wherein: The front surface of the silicon substrate has a suede structure, and the suede reflectivity is 7% to 10%; and / or, The solar cell further comprises a front passivation layer located on the front side of the silicon substrate and a front anti-reflection layer located on the front side of the front passivation layer. The thickness of the front anti-reflection layer is 70 nm to 90 nm.