Chip and semiconductor power module

Abstract

The utility model relates to the field of semiconductors, and discloses a chip and a semiconductor power module, and the chip comprises a chip body which comprises a plurality of electrode regions; a first solder layer stacked in the electrode region in a first direction; the bonding connection layer is arranged on the face, back to the chip body, of the first solder layer in a stacked mode in the first direction, the bonding connection layer is used for being connected with a bonding wire, and the orthographic projection, in the electrode area, of the bonding connection layer is arranged in the orthographic projection, in the electrode area, of the first solder layer. In order to solve the problems that a bonding connection layer is high in connection cost, low in production efficiency and prone to causing stress concentration, a first solder layer is arranged between a chip body and the bonding connection layer, and the orthographic projection of the bonding connection layer in an electrode area is arranged in the orthographic projection of the first solder layer in the electrode area; therefore, the bonding connection layer is connected to the chip body through reflow soldering, the cost of the connection process is reduced, the processing efficiency of the chip is improved, and the stress concentration of the bonding connection layer is prevented from being intensified.

Description

Technical Field

[0001] The present application relates to the field of semiconductors, and in particular to a chip and a semiconductor power module. Background Art

[0002] Wire bonding is an important semiconductor packaging technology that uses thin metal wires as bonding wires and uses energy such as heat, pressure, and ultrasound to tightly weld the bonding wires to the substrate pads of semiconductor power modules, thereby achieving electrical interconnection between the chip and the substrate and information exchange between chips.

[0003] To improve the stability of the connection between the chip and the bonding wire, a bonding layer is currently placed on the top surface of the chip. This bonding layer is connected to the chip surface using silver sintering technology. However, silver sintering technology is expensive and has low production efficiency. Furthermore, the high pressure during the silver sintering process exacerbates stress concentration in the bonding layer. Utility Model Content

[0004] The embodiments of the present application provide a chip and a semiconductor power module, which can reduce production costs, improve production efficiency, and enhance the connection stability of the bonding connection layer.

[0005] In the first aspect, an embodiment of the present application provides a chip, comprising: a chip body, comprising multiple electrode regions; a first solder layer, stacked along a first direction on the electrode region; a bonding connection layer, stacked along the first direction on the side of the first solder layer facing away from the chip body, the bonding connection layer being used to connect to a bonding wire, the orthographic projection of the bonding connection layer on the electrode region being placed within the orthographic projection of the first solder layer on the electrode region.

[0006] According to the chip provided in the embodiment of the present application, the electrode region includes a plurality of source regions spaced apart along a second direction, the first solder layer is continuously arranged on the plurality of source regions, and the first direction is perpendicular to the second direction.

[0007] According to the chip provided in an embodiment of the present application, the side of the bonding connection layer facing away from the first solder layer includes a first stress release area arranged along the circumferential edge and a first bonding area arranged in the middle, the first stress release area extends along the first direction toward the first solder layer and is provided with a stress reducing structure, and the first bonding area is used to connect to the bonding wire.

[0008] According to the chip provided by the embodiment of the present application, the stress relief structure includes a first groove structure or a through hole penetrating the bonding connection layer.

[0009] According to the chip provided in an embodiment of the present application, the side of the bonding connection layer facing away from the first solder layer includes a second stress release area located in the middle and a second bonding area avoiding the second stress release area, the second stress release area is provided with a second groove structure along the first direction, and the second bonding area is used to connect to the bonding wire.

[0010] According to the chip provided by the embodiment of the present application, the second groove structure penetrates the bonding connection layer along the span direction of the bonding connection layer.

[0011] According to the chip provided in an embodiment of the present application, the second stress release area is provided with a plurality of intersecting second groove structures.

[0012] In the second aspect, an embodiment of the present application also provides a semiconductor power module, comprising: a substrate; a second solder layer, stacked on the substrate along a first direction; a chip, stacked on the side of the second solder layer facing away from the substrate along the first direction; and bonding wires, bonded and connected between multiple chips and / or between the chip and the substrate.

[0013] According to the semiconductor power module provided by the embodiment of the present application, the difference in thermal expansion coefficient between the bonding connection layer and the bonding wire is smaller than the difference in thermal expansion coefficient between the electrode region and the bonding wire.

[0014] According to the semiconductor power module provided by the embodiment of the present application, the thermal expansion coefficient of the material of the bonding wire and the bonding connection layer is the same.

[0015] The chip and semiconductor power module of the embodiments of the present application are configured such that a first solder layer is arranged between the chip body and the bonding connection layer, and the orthographic projection of the bonding connection layer in the electrode area is placed within the orthographic projection of the first solder layer in the electrode area, thereby enabling the bonding connection layer to be connected to the chip body through reflow soldering, thereby reducing the cost of the connection process, improving the processing efficiency of the chip, and avoiding aggravated stress concentration in the bonding connection layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0017] Figure 1 shows a top view of a semiconductor power module provided by some embodiments of the present application;

[0018] Figure 2 Show Figure 1 Left view of;

[0019] Figure 3 Show Figure 1 The main view;

[0020] Figure 4 Show Figure 1 A top view of an exemplary chip;

[0021] Figure 5 Show Figure 4 Cross-section along AA direction;

[0022] Figure 6 Show Figure 1 A top view of another exemplary chip;

[0023] Figure 7 Show Figure 6 Cross-section along BB direction;

[0024] Figure 8 A stress distribution diagram showing a bonding connection layer and a first solder layer in an electrode region of an embodiment of the present application in which the bonding connection layer is a continuous structure;

[0025] Figure 9 Show Figure 1 A top view of another exemplary chip;

[0026] Figure 10 Show Figure 9 Rear view;

[0027] Figure 11 A rear view of a chip showing another example;

[0028] Figure 12 Show Figure 4 Stress distribution diagram of the bonding connection layer and the first solder layer of the chip;

[0029] Figure 13 Show Figure 9 Stress distribution diagram of the chip's bonding layer and first solder layer.

[0030] Reference numerals:

[0031] 100: substrate; 200: chip; 210: chip body; 220: electrode area; 221: source area; 230: bonding connection layer; 231: stress reduction structure; 232: first stress release area; 233: first bonding area; 234: second groove structure; 235: second stress release area; 236: second bonding area; 240: first solder layer; 300: second solder layer; 310: bonding wire. DETAILED DESCRIPTION

[0032] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is merely to provide a better understanding of the present application by illustrating the examples of the present application.

[0033] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, the elements defined by the phrase "comprising..." do not exclude the presence of other identical elements in the process, method, article, or device comprising the elements.

[0034] Semiconductor power modules are widely used in the power electronics industry and are a fundamental component of electronic products. They are gaining increasing attention and application as the industry transitions to electronicization. In recent years, the call for the Internet of Everything has intensified. Transportation vehicles, such as automobiles and high-speed rail; new energy sectors, such as photovoltaics and wind power; communications equipment, such as mobile phones; and consumer products, such as televisions, washing machines, air conditioners, and refrigerators, are all experiencing increasing levels of electronicization. The high degree of electronicization in new energy vehicles is particularly striking. Meanwhile, traditional sectors, such as industry and power grids, are also accelerating their electronicization process. Amidst this wave of electronicization, the industry's demands for semiconductor device performance are rapidly increasing. The power conversion capabilities of a single chip are no longer sufficient to meet this growing demand. Integrating multiple chips within a package to form semiconductor power modules is crucial for addressing high-current and high-power applications. However, the large size and high power consumption of these power modules also place increasing demands on the wire bonding process.

[0035] Existing semiconductor power modules usually include a heat sink, a substrate solder layer, a DBC substrate, a chip solder layer, a chip and bonding wires from bottom to top. Among them, the heat sink is used to dissipate heat as a whole power module. The substrate solder layer can be a thermally conductive adhesive, which is used to connect the DBC substrate and the heat sink. The DBC substrate is composed of three layers of copper-ceramic-copper. The lower copper is usually a whole piece, and the upper copper is usually multiple separate pieces of copper to form a circuit pattern. The ceramic layer acts as an insulator, so that the current does not flow to the lower copper and the area below. Since the upper copper is composed of multiple independent pieces of copper and the gap in the middle is ceramic, current cannot be transmitted between them. Therefore, bonding wires are required to connect the chips to each other and the chip to the DBC substrate to form the required circuit. This enables information exchange between different chips and electrical transmission between the entire power module and the outside world.

[0036] Common materials for bonding wires include aluminum, gold, silver, and copper. Aluminum wire is the most widely used in power modules due to its low price. The bonding wires are connected to the chip and DBC substrate through a bonding process involving ultrasonic welding. Ultrasonic bonding uses a wedge to guide the bond wire and press it against the metal pad. The wedge then inputs ultrasonic pulses at a frequency parallel to the pad plane, causing the wedge to vibrate horizontally while simultaneously applying downward pressure. These two forces cause the wedge to rapidly rub the bond wire against the metal surface of the bond pad. The energy causes the bond wire to plastically deform, resulting in close contact with the bond pad, completing the bond.

[0037] However, power modules are frequently turned on and off during use, generating heat that causes the module temperature to rise. The mismatch in the thermal expansion coefficients of the various material layers creates thermal stress, ultimately causing the bond wires to break. Bond wire failure is the most common cause of power module failure. For example, the thermal expansion coefficient of aluminum bond wires is 23.21ppm / °C, while the chip's source region is made of silicon carbide, which has a thermal expansion coefficient of 2.62ppm / °C. This significant difference in thermal expansion coefficients causes the power module to expand and contract to varying degrees with temperature fluctuations, resulting in significant shear stress. This can cause cracks in the bond wire solder joints, increasing the risk of breakage and further increasing the risk of failure when subjected to mechanical shock or temperature fluctuations.

[0038] Compared to aluminum wire, copper wire has higher electrical and thermal conductivity, better mechanical properties, and a lower thermal expansion coefficient. Therefore, replacing copper wire with aluminum wire as bonding wire can significantly improve the reliability and service life of power modules. However, due to the high hardness of copper wire, ultrasonic bonding can cause damage to the chip surface. To reduce chip damage, copper wire bonding is typically achieved by sintering a bonding layer in the electrode area of ​​the chip surface using silver sintering. The bonding layer is typically made of copper or a copper-molybdenum alloy, which has excellent heat dissipation properties and a good thermal expansion coefficient match with the copper bonding wire.

[0039] However, the nanosilver used in silver sintering technology is relatively expensive, and the cost of silver paste increases as the size of silver particles decreases. Furthermore, silver sintering requires a certain amount of auxiliary pressure, and high auxiliary pressure can easily damage the chip. The silver sintering process requires preheating and sintering, and the entire process can take over 60 minutes, resulting in low production efficiency.

[0040] In order to solve the problems in the prior art, the embodiment of the present application provides a chip 200 and a semiconductor power module. The chip 200 provided by the embodiment of the present application is first introduced below.

[0041] Figure 1 shows a top view of a semiconductor power module provided by some embodiments of the present application, Figure 2 Show Figure 1 Left view of Figure 3 Show Figure 1 main view.

[0042] like Figures 1 to 3 As shown, an embodiment of the present application provides a semiconductor power module, including: a substrate 100; a second solder layer 300, stacked on the substrate 100 along a first direction; a chip 200, stacked on the side of the second solder layer 300 facing away from the substrate 100 along the first direction; and a bonding wire 310, bonded and connected between multiple chips 200 and / or between the chip 200 and the substrate 100.

[0043] Specifically, the substrate 100 includes an insulating layer and a copper clad layer stacked along a first direction. The copper clad layer forms a circuit. A second solder layer 300 connects the chip 200 to the copper clad layer through a reflow process. The second solder layer 300 can include tin-based alloy solder, solder paste, etc. The coverage area of ​​the second solder layer 300 is greater than or equal to the bottom area of ​​the chip 200. The bottom of the chip 200 is the drain region, which is electrically connected to the copper clad layer. The upper portion of the chip 200 includes electrode regions 220, such as the source region 221, the gate region, and the Kelvin source region 221. These regions are electrically connected to other chips 200 and / or the substrate 100 via bonding wires 310. The bonding wires 310 can be copper wires. The Kelvin source region is connected via a separate bonding wire 310, so that the induced voltage on the L_SL cannot affect the drive circuit, thereby increasing switching speed and reducing switching losses. The gate region, source region, and Kelvin source region are different functional areas of the chip. The current flows into the drain region (bottom) of the chip and flows out of the source region. The power signal flows into the gate and flows out of the Kelvin source.

[0044] Figure 4 Show Figure 1 A top view of an exemplary chip 200; Figure 5 Show Figure 4 Cross-section along the AA direction.

[0045] The present embodiment provides a chip 200, which is used in a semiconductor power module according to the above embodiment. The chip 200 includes: a chip body 210 including a plurality of electrode regions 220; a first solder layer 240 stacked along a first direction on the electrode regions 220; and a bonding layer 230 stacked along the first direction on a surface of the first solder layer 240 facing away from the chip body 210. The bonding layer 230 is used to connect to a bonding wire 310, and the orthographic projection of the bonding layer 230 on the electrode regions 220 is located within the orthographic projection of the first solder layer 240 on the electrode regions 220. In other words, the coverage area of ​​the first solder layer 240 is greater than or equal to the coverage area of ​​the bonding layer 230.

[0046] Specifically, the first solder layer 240 includes tin-based alloy solder, solder paste, etc., and a reflow soldering process can be used to connect the chip body 210 to the bonding connection layer 230. The solder production of the first solder layer 240 is mature and diverse, and the material cost and production cost are far lower than silver. The reflow soldering process conditions are simple and do not require pressurization, eliminating the impact of high pressure on the chip 200. Moreover, this process is more mature than silver sintering, and it is easier to obtain process parameters suitable for the scenario. The reflow soldering process has a fast heating speed, and the process time is usually no more than 15 minutes, which greatly improves production efficiency compared to silver sintering.

[0047] The bonding layer 230 is connected to the electrode region 220 of the chip body 210 via the first solder layer 240, thereby connecting the chip body 210 to the bonding wire 310. The bonding layer 230 can be made of materials such as pure copper, copper-molybdenum-copper, copper-Invar-copper, etc., and has excellent heat dissipation performance and good thermal expansion coefficient matching with the copper bonding wire 310. The bonding layer 230 not only matches the thermal expansion coefficient of the interface material at the bonding point, but also ensures that the coating of the chip 200 is not damaged.

[0048] The orthographic projection of the bonding layer 230 on the electrode region 220 is positioned within the orthographic projection of the first solder layer 240 on the electrode region 220. The bonding layer 230 can be completely covered by the first solder layer 240, thereby providing better protection and support. In other words, the orthographic projection of the bonding layer 230 on the substrate 100 overlaps with the orthographic projection of the first solder layer 240 on the substrate 100, and the orthographic projection of the bonding layer 230 on the substrate 100 is positioned within the orthographic projection of the source region 221 on the substrate 100. The size of the bonding layer 230 is slightly smaller than that of the source region 221, leaving sufficient space for the bonding layer 230 to drift, preventing the bonding layer 230 from drifting out of the source region 221 and contaminating other areas, thereby affecting the function of the entire chip 200. At the same time, the first solder layer 240 also provides a stable electrical connection foundation for the bonding layer 230. The first solder layer 240 provides a larger contact area for the bonding layer 230, thereby increasing the reliability of the connection. The larger contact area helps to disperse stress and reduce the risk of failure caused by poor connection or stress concentration.

[0049] Continue to refer Figure 4 and Figure 5 In an optional embodiment of the present application, the electrode region 220 includes a plurality of source regions 221 spaced apart along the second direction, and the source regions 221 are used to provide a current or signal source. The source region 221 is connected to an external circuit, introduces current or signal into the chip 200, and outputs it to the outside after being processed by the chip 200. Multiple source regions 221 can share current, reduce resistance and heat generation. At the same time, the spacing arrangement also facilitates coordination with other electrodes (such as drain regions, gate regions, etc.) to achieve complex circuit control. Each source region 221 is provided with a first solder layer 240 and a bonding connection layer 230. The coverage area of ​​the first solder layer 240 of each source region 221 is equal to the coverage area of ​​the bonding connection layer 230 of the region, so that the bonding connection layer 230 completely covers the first solder layer 240. The coverage area of ​​the first solder layer 240 may be smaller than the area of ​​the source region 221. The first solder layers 240 of adjacent source regions 221 are spaced apart from each other. Therefore, the bonding connection layers 230 of adjacent source regions 221 are spaced apart from each other.

[0050] Figure 6 Show Figure 1 A top view of another exemplary chip 200; Figure 7 Show Figure 6 Cross-section along direction BB.

[0051] like Figure 6 and Figure 7As shown, in another optional embodiment of the present application, the electrode region 220 includes a plurality of source regions 221 spaced apart along the second direction, the first solder layer 240 is continuously arranged on the plurality of source regions 221 , and the first direction is perpendicular to the second direction.

[0052] When multiple source regions 221 can be connected, the first solder layer 240 can be connected to multiple source regions 221 simultaneously. The first solder layer 240 forms a continuous connection across the multiple source regions 221, thereby establishing an electrical connection between the multiple source regions 221. The continuous arrangement of the first solder layer 240 can improve the efficiency and stability of current transmission, reducing resistance and signal loss. Furthermore, the application of a single layer of first solder layer 240 across multiple source regions 221 increases the coverage area of ​​the first solder layer 240 and reduces the difficulty of processing the first solder layer 240.

[0053] Furthermore, in the embodiment of the present application, the bonding layer 230 on the side of the first solder layer 240 facing away from the chip body 210 may also be laid continuously, thereby increasing the coverage area of ​​the bonding layer 230 and reducing the difficulty of bonding.

[0054] In addition, during the operation of the chip 200, stress will be generated inside the chip 200 due to factors such as temperature changes, mechanical vibrations, and current flow, especially the heating of the source region 221. As for the first solder layer 240, it connects the chip body 210 and the bonding layer 230, and is subjected to forces from different parts. When these forces are unevenly distributed, concentrated stress will be generated in the first solder layer 240. When the bonding layer 230 in an electrode area 220 is a continuous layer, stress concentration is more likely to occur, thereby increasing the failure risk of the first solder layer 240. In order to reduce the failure risk of the first solder layer 240 and improve the stability of the bonding layer 230 connected through the first solder layer 240, the bonding layer 230 is subjected to stress reduction treatment.

[0055] Figure 8 The stress distribution diagram of the bonding connection layer 230 and the first solder layer 240 in an electrode region 220 in an embodiment of the present application is shown. The bonding connection layer 230 is a continuous structure.

[0056] Specifically, if Figure 8 As shown, the left side of the figure is the stress distribution diagram of the bonding connection layer 230, and the right side is the stress distribution diagram of the first solder layer 240. Figure 8Because the image is black and white, the stress distribution cannot be determined by the depth of the color. Since the stress distribution trends of the bonding layer 230 and the first solder layer 240 are similar, the stress distribution diagram of the bonding layer 230, for example, shows that the concentrated stress is high at the boundary between the bonding layer 230 and the first solder layer 240, with the highest concentrated stress at the four corners and the lowest concentrated stress in the center of the bonding layer 230. Based on the stress distribution diagram, stress reduction treatment is performed on the bonding layer 230.

[0057] like Figure 4 and Figure 6 As shown, in some embodiments of the present application, the side of the bonding connection layer 230 facing away from the first solder layer 240 includes a first stress release area 232 arranged along the circumferential edge and a first bonding area 233 arranged in the middle, the first stress release area 232 extends along the first direction toward the first solder layer 240 and is provided with a stress reducing structure 231, and the first bonding area 233 is used to connect to the bonding wire 310.

[0058] based on Figure 8 The stress distribution diagram in FIG. 2 shows that concentrated stress is greater at the circumferential edge of the bonding layer 230, namely the first stress relief region 232. Therefore, a stress relief structure 231 of a certain depth is provided in the first stress relief region 232 to reduce stress in this region. The stress relief structure 231 is provided along a first direction toward the first solder layer 240, extending from the side of the bonding layer 230 facing away from the first solder layer 240.

[0059] The stress-reducing structure 231 locally thins the bonding layer 230 in the thickness direction. When the first solder layer 240 is subjected to stress, the stress-reducing structure 231 provides space for stress release, preventing excessive stress concentration in local areas of the solder layer, thereby reducing the risk of rupture or failure of the first solder layer 240. The stress-reducing structure 231 changes the geometry of the bonding layer 230, thereby changing the distribution of stress in the bonding layer 230 and the first solder layer 240. The stress will be dispersed to a certain extent at the thinned area of ​​the stress-reducing structure 231, making the stress distribution more uniform. The provision of the stress-reducing structure 231 increases the flexibility of the bonding layer 230 and the first solder layer 240, allowing them to deform more easily at the stress concentration location, thereby absorbing and dispersing the stress. This flexibility can reduce material rupture or damage caused by stress concentration.

[0060] Furthermore, the stress-reducing structures 231 can be provided in the first stress-relieving region 232 and positioned at the corners of the bonding layer 230. For example, if the orthographic projection of the bonding layer 230 is rectangular, a stress-reducing structure 231 can be provided at each of the four corners of the rectangle. Furthermore, the multiple stress-reducing structures 231 of the bonding layer 230 can be separated and independent from each other, or can be interconnected while maintaining continuity between the first stress-relieving region 232 and the first bonding region 233. In other words, the bonding layer 230 with the stress-reducing structures 231 is a unitary structure.

[0061] In a specific embodiment of the present application, the stress-reducing structure 231 includes a first groove structure or a through-hole extending through the bonding layer 230. When the stress-reducing structure 231 is a through-hole, the multiple stress-reducing structures 231 are spaced apart and independent from each other to ensure the integrity of the bonding layer 230. The first groove structure may be a countersunk hole, a strip groove, or a wing-shaped groove, and the through-hole may be a circular hole, a square hole, or a wing-shaped hole.

[0062] Figure 9 Show Figure 1 A top view of another exemplary chip 200; Figure 10 Show Figure 9 Rear view; Figure 11 A rear view of another example chip 200 is shown.

[0063] like Figures 9 to 11 As shown, in other embodiments of the present application, the side of the bonding connection layer 230 facing away from the first solder layer 240 includes a second stress release area 235 located in the middle and a second bonding area 236 avoiding the second stress release area 235, the second stress release area 235 is provided with a second groove structure 234 along the first direction, and the second bonding area 236 is used to connect with the bonding wire 310.

[0064] The second groove structure 234 may be a strip groove, a circular groove, or a wing-shaped groove. There may be one or more second groove structures 234, and multiple second groove structures 234 may be connected or spaced apart. The second bonding area 236 needs to have sufficient area for connecting the bonding wire 310.

[0065] Specifically, to enhance the stress-reducing effect of the second groove structure 234, in some embodiments of the present application, the second groove structure 234 penetrates the bonding layer 230 along the span direction of the bonding layer 230. For example, the second groove structure 234 penetrates the bonding layer 230 along the length direction or the width direction of the bonding layer 230, so that the second groove structure 234 is a through groove, which reduces the processing difficulty and enhances the stress-reducing effect, thereby ensuring the connection stability of the first solder layer 240.

[0066] Continue to refer Figure 9In the embodiment of the present application, the second stress release area 235 is provided with a plurality of intersecting second groove structures 234 .

[0067] For example, the second stress relief region 235 includes two second groove structures 234, wherein one second groove structure 234 is provided along the length direction of the bonding layer 230, and the other second groove structure 234 is provided along the width direction of the bonding layer 230. The two second grooves intersect at the middle and may be provided perpendicularly to each other.

[0068] In addition, in the embodiment of the present application, the difference in thermal expansion coefficients between the bonding layer 230 and the bonding wire 310 is smaller than the difference in thermal expansion coefficients between the electrode region 220 and the bonding wire 310. This reduces the thermal stress caused by the difference in thermal expansion coefficients and improves the connection strength and stability of the bonding wire 310.

[0069] Furthermore, in one embodiment of the present application, the bonding wire 310 and the bonding layer 230 have the same thermal expansion coefficient. The bonding wire 310 can be a copper wire, and the bonding wire 310 and the bonding layer 230 can be made of the same material. Atoms of the same material are more easily bonded together, and the copper wire, protected by the bonding layer 230, can also use a larger bonding parameter value, thereby forming a stronger connection between the bonding wire 310 and the chip 200 and greatly improving the reliability of the bonding wire 310 solder joint.

[0070] Figure 12 Show Figure 4 Stress distribution diagram of the bonding connection layer 230 and the first solder layer 240 of the chip 200; Figure 13 Show Figure 9 Stress distribution diagram of the bonding layer 230 and the first solder layer 240 of the chip 200 .

[0071] like Figure 8 、 Figure 12 and Figure 13 As shown, Figure 12 and Figure 13 The maximum stress of the bonding layer 230 and the first solder layer 240 in the chip 200 is less than Figure 8 The maximum stress of the stress distribution diagram is reduced, and the overall stress distribution is more uniform. It can be seen that the maximum stress of the first solder layer 240 of the bonding layer 230 with the stress-reducing structure 231 and the second groove structure 234 is less than the maximum stress of the first solder layer 240 of the bonding layer 230 without stress-reducing treatment, and the stress distribution of the first solder layer 240 is more uniform. This makes the connection of the first solder layer 240 more stable.

[0072] The manufacturing process of the semiconductor power module provided in the embodiment of the present application includes the following steps:

[0073] In the first step, the chip 200 is connected to the substrate 100 .

[0074] Solder paste or other solder is applied to the pad of the chip 200 on the substrate 100 by dispensing, and then the chip 200 is sucked up with a vacuum pen and slowly moved to the top of the pad. After alignment, the suction of the vacuum pen is removed to allow the chip 200 to fall onto the solder. Then, a certain pressure is applied to tightly fit the chip 200 and the second solder layer 300. In addition, the chip 200 and the substrate 100 are connected through the same or different solder adaptation processes.

[0075] In the second step, the bonding layer 230 is connected to the chip 200 .

[0076] If the solder of the first solder layer 240 is solder paste, use a syringe to hold the solder paste, and squeeze out an appropriate amount of solder paste on the electrode area 220 on the upper surface of the chip 200 according to the surface size of the chip 200. If the solder is a solder sheet, it can be placed on the electrode area 220 by sucking it up with a vacuum suction pen or mechanically grasping it; form a first solder layer 240 whose size needs to be slightly smaller than the electrode area 220, form a bonding connection layer 230 on the first solder layer 240, and use a reflow soldering process to achieve the connection between the chip body 210 and the bonding connection layer 230.

[0077] In the third step, the bonding layer 230 is connected to the substrate 100 using the bonding wire 310 .

[0078] The first connection end of the bonding wire 310 is connected to the bonding connection layer 230 by ultrasonic method, and then the second connection end of the bonding wire 310 is connected to the substrate 100, thereby completing the assembly of the partial structure of the semiconductor power module.

[0079] Silver sintering technology is a high-temperature, high-pressure, and time-consuming process, with costs significantly higher than reflow soldering. Therefore, replacing the sintered silver layer with the first solder layer 240 can effectively improve production efficiency and reduce costs. However, the reliability of the first solder layer is lower than that of sintered silver, and failure of the bonding layer 230 or the first solder layer 240 may occur during use of the power module. Therefore, by using a stress-reducing structure and / or a second groove structure on the bonding layer 230 to improve the reliability of the first solder layer 240, an efficient, low-cost, and highly reliable bonding of the bonding layer 230 and the first solder layer 240 can be achieved, thereby enabling bonding of the copper bonding wire 310.

[0080] The above description is only a specific embodiment of the present application. Those skilled in the art will clearly understand that for the convenience and brevity of description, the specific working processes of the systems, modules and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here. It should be understood that the scope of protection of the present application is not limited thereto. Any person skilled in the art can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be included in the scope of protection of the present application.

Claims

1. A chip, characterized in that: include: A chip body (210) includes a plurality of electrode regions (220); A first solder layer (240) is stacked on the electrode region (220) along a first direction; A bonding connection layer (230) is stacked along the first direction on a side of the first solder layer (240) facing away from the chip body (210), the bonding connection layer (230) being used to connect to a bonding wire (310), and an orthographic projection of the bonding connection layer (230) in the electrode region being placed within an orthographic projection of the first solder layer (240) in the electrode region (220).

2. The chip according to claim 1, characterized in that The electrode region (220) includes a plurality of source regions (221) spaced apart along a second direction, the first solder layer (240) is continuously arranged on the plurality of source regions (221), and the first direction is perpendicular to the second direction.

3. The chip according to claim 1, characterized in that The bonding connection layer (230) includes a first stress release region (232) arranged along a circumferential edge and a first bonding region (233) arranged in the middle on a side facing away from the first solder layer (240); the first stress release region (232) extends toward the first solder layer (240) along the first direction and is provided with a stress reduction structure (231); and the first bonding region (233) is used for connecting to the bonding wire (310).

4. The chip according to claim 3, characterized in that The stress relief structure (231) comprises a first groove structure or a through hole penetrating the bonding connection layer (230).

5. The chip according to claim 1 or 3, characterized in that: The side of the bonding connection layer (230) facing away from the first solder layer (240) includes a second stress release area (235) located in the middle and a second bonding area (236) avoiding the second stress release area (235); the second stress release area (235) is provided with a second groove structure (234) along the first direction; and the second bonding area (236) is used to connect with the bonding wire (310).

6. The chip according to claim 5, characterized in that The second groove structure (234) penetrates the bonding connection layer (230) along the extension direction of the bonding connection layer (230).

7. The chip according to claim 5, characterized in that The second stress release area (235) is provided with a plurality of second groove structures (234) intersecting with each other.

8. A semiconductor power module, characterized in that: include: substrate(100); A second solder layer (300) is stacked on the substrate (100) along a first direction; The chip (200) according to any one of claims 1 to 7, stacked along the first direction on a side of the second solder layer (300) facing away from the substrate (100); Bonding wires (310) are bonded and connected between the plurality of chips (200) and / or between the chip (200) and the substrate (100).

9. The semiconductor power module according to claim 8, characterized in that The difference in thermal expansion coefficient between the bonding connection layer (230) and the bonding wire (310) is smaller than the difference in thermal expansion coefficient between the electrode region (220) and the bonding wire (310).

10. The semiconductor power module according to claim 9, characterized in that The bonding wire (310) and the bonding connection layer (230) have the same thermal expansion coefficient.

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