Lead frame structure

Abstract

The utility model discloses a lead frame structure, which comprises a chip seat and a plurality of pins distributed around the chip seat, the chip seat is provided with a first surface for placing a chip and a second surface opposite to the first surface, and the pins comprise a first pin and a second pin. Each of the first pin and the second pin is provided with a first end which is close to the direction of the chip seat and is not in contact with the chip seat and a second end which is far away from the first end, and the first end of the first pin and the first end of the second pin are not in the same horizontal plane in height; therefore, in the subsequent high-density bonding operation, the number of lead bonding intersection can be reduced, or the distance between adjacent leads after intersection can be increased, so that the production difficulty is reduced, and the production efficiency is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductor packaging process, and in particular to a lead frame structure. Background Art

[0002] The Quad Flat No-lead Package (QFNP) is an increasingly common chip packaging trend in the semiconductor industry today. Its advantages include its compact size, comparable to the Chip Scale Package (CSP). Furthermore, it offers superior heat dissipation, excellent electrical performance, and consistent quality. Furthermore, its light, thin, short, and compact dimensions have made it a mainstream lead frame base package, widely used in a variety of applications.

[0003] like Figure 1 As shown in FIG, it is a three-dimensional diagram of the lead frame structure used in such products. This lead frame 10 includes: a chip base 11 and a plurality of pins 12 distributed around the chip base 11. As the size of semiconductors becomes smaller and smaller, the number of pins 12 has not decreased. On the contrary, the number of some pins 12 has increased. In order to solve this problem, a long pin 12 structure is used. The long pin 12 increases the distance between the end away from the chip base 11 and the adjacent pin 12. This design is conducive to subsequent electrical connection to the circuit board. But as Figure 2 Figure 1 is a schematic diagram of the partial wire bonding state of a lead frame. A chip 13 is mounted on a chip holder 11, and the ends of the leads 14 are connected to the chip 13 and the corresponding pins 12, respectively. As shown in the figure, the pins 12 are very close to each other at the end closest to the chip holder 11. During the wire bonding operation between the chip 13 and the pins 12, the leads 14 will inevitably cross. Since adjacent pins 12 are at the same height, once the lead 14 crosses, the distance between the upper and lower adjacent leads 14 is likely to be too close, especially the closer the lead 14 is to the pin 12, the more obvious the crossover is, making it easy for contact to occur and cause a short circuit. To solve this problem, the height of some leads 14 must be increased, which increases the difficulty of wire bonding, making the packaging production operation more difficult, and relatively reducing production efficiency. Utility Model Content

[0004] The main purpose of the present invention is to provide a lead frame structure in which the ends of multiple leads close to the chip seat are designed to be at different heights, thereby improving the problem of lead bonding crossover with a high number of wires, thereby reducing production difficulty and solving the problem of low production efficiency.

[0005] To achieve the above-mentioned objectives, the present invention is a lead frame structure, comprising a chip holder and a plurality of pins distributed around the chip holder, wherein the chip holder has a first surface for placing a chip and a second surface opposite to the first surface, and the pins include a first pin and a second pin, wherein the first pin and the second pin both have a first end close to and not in contact with the chip holder, and a second end located away from the first end, and the first end of the first pin and the first end of the second pin are not at the same level.

[0006] As one of the preferred embodiments, the first end of the first pin and the first end of the adjacent second pin are not in the same horizontal plane.

[0007] As one of the preferred embodiments, the first pins and the second pins are staggered and distributed around the chip seat.

[0008] As one of the preferred embodiments, the first end of the first pin is located higher than the first surface.

[0009] As one of the preferred embodiments, the first pin further has a raised section at a middle position, two ends of the raised section are respectively connected to the first end and the second end, and the first end is higher than the second end.

[0010] As one of the preferred embodiments, the bottom surfaces of the second ends of the first pin and the second pin are on the same horizontal plane.

[0011] As one of the preferred embodiments, the lead frame structure is used in a Quad Flat NoLead (QFN) package structure.

[0012] Compared with the prior art, the lead frame structure of the present invention is designed in such a way that the first end of the first pin close to the chip holder and the first end of the second pin are not designed to be at the same level. In this way, when the chip on the chip holder is wire-bonded with the surrounding first pin and second pin, the number of wire bonding crosses can be reduced, or the distance between adjacent leads above and below can be increased, thereby reducing production difficulty and increasing production efficiency and yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is a perspective view of an existing lead frame.

[0014] Figure 2 Schematic diagram of local wire bonding of an existing lead frame.

[0015] Figure 3 It is a three-dimensional diagram of the lead frame structure of the present invention.

[0016] Figure 4This is a schematic diagram of the lead frame of the present invention from another angle.

[0017] Figure 5 This is a schematic diagram of the partial lead bonding state of the lead frame of the present invention.

[0018] Figure 6 This is a partial enlarged view of the lead frame lead bonding state of the utility model.

[0019] Description of main reference numerals:

[0020] 10: Lead frame 11: Chip seat

[0021] 12: Pin 13: Chip

[0022] 14: Lead 20: Lead frame

[0023] 21: Chip seat 211: First side

[0024] 212: Second side 22: First pin

[0025] 221: first end 222: second end

[0026] 223: Rising section 23: Second pin

[0027] 231: first end 232: second end. DETAILED DESCRIPTION

[0028] The technical solution of the present invention will be clearly and completely described below in conjunction with specific embodiments and accompanying drawings. It should be noted that when a component is referred to as being "mounted on or fixed to" another component, it means that it can be directly on the other component or there may also be a central component. When a component is considered to be "connected" to another component, it means that it can be directly connected to the other component or there may be a central component at the same time. In the illustrated embodiments, the directions such as up, down, left, right, front and back are relative and are used to explain that the structure and movement of different components in this case are relative. These representations are appropriate when the components are in the positions shown in the figures. However, if the description of the component positions changes, it is considered that these representations will also change accordingly.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. The terms used herein are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0030] like Figure 3 and Figure 4The figure shows a three-dimensional diagram of the lead frame structure of the present invention. The lead frame 20 of the present invention includes a chip holder 21 and a plurality of pins distributed around the chip holder. The chip holder 21 has a first surface 211 for placing the chip and a second surface 212 opposite to the first surface 211. The plurality of pins include a first pin 22 and a second pin 23. The first pin 22 and the second pin 23 both have first ends 221, 231 that are close to the chip holder 21 and do not contact the chip holder 21, and second ends 222, 232 that are located away from the first ends 221, 231. The first end 221 of the first pin 22 and the first end 231 of the second pin 23 are not at the same level. More specifically, the first end 221 of the first pin 22 is located higher than the first surface 211, the first end 231 is lower than the first end 221, or the first end 231 is at the same level as the first surface 211. The key point of this novel design is to utilize the first end 221 and the first end 231 to be not in the same horizontal plane, thereby solving the problem of the wires being too close to each other when bonding ultra-high wire count wires.

[0031] The second pins 23 extend horizontally and radially outward from the die pad 21, with their vertical position (i.e., along the Y-axis) remaining unchanged. The first pins 22 also have a raised section 223 at their center. This section can simultaneously change both their horizontal position (i.e., along the X-axis) and their vertical position (i.e., along the Y-axis). The ends of the raised section 223 are connected to a first end 221 and a second end 222, respectively, so that the first end 221 is higher than the second end 222. In this embodiment, the first pins 22 and the second pins 23 are staggered around the die pad 21. That is, the first ends 221 of adjacent first pins 22 and the first ends 231 of adjacent second pins 23 are not on the same horizontal plane. This helps reduce the number of wire bond crossovers and increases the vertical distance between adjacent wires when they cross, thereby reducing production complexity and increasing production efficiency and yield.

[0032] In addition, the lead frame of the present invention is applied to a Quad Flat No Lead (QFN) package structure, so the second ends 222 and 232 of the first lead 22 and the second lead 23 away from the chip base 21 have relatively special shapes, and the bottom surfaces are on the same horizontal plane.

[0033] like Figure 5 FIG. 1 is a schematic diagram of a partial wire bonding state using the lead frame of the present invention. The chip 13 is disposed on the first surface 211 of the chip holder 21. The two ends of the lead 14 are respectively connected to the chip 13 and the first end 221 of the corresponding first pin 22 or the first end 231 of the second pin 23. Since the adjacent first ends 221 and first ends 231 are not at the same horizontal position, as shown in FIG. Figure 6As shown, the lead 14 connected to the first end 221 and the lead 14 connected to the first end 231 are separated from each other by a distance, regardless of whether they are close to the chip 13 or close to the first pin 22 and the second pin 23. This solves the problem of the existing leads 14 getting closer to each other as they get closer to the pins, greatly reducing the possibility of contact short circuits between adjacent leads 14. This can also reduce the difficulty of wire bonding and improve production quality and efficiency.

[0034] The above description is only a preferred embodiment of the present invention and is not intended to limit the scope of the present invention. That is, all equivalent changes and modifications made within the scope of the present invention are covered by the protection scope of the present invention.

Claims

1. A lead frame structure comprising a chip holder and a plurality of pins distributed around the chip holder, wherein the chip holder has a first surface for placing a chip and a second surface opposite to the first surface, and the pins include a first pin and a second pin, characterized in that: The first pin and the second pin both have a first end close to the chip seat and not in contact with the chip seat, and a second end located away from the first end. The first end of the first pin and the first end of the second pin are not at the same level.

2. The lead frame structure according to claim 1, wherein: The first end of the first pin and the first end of the adjacent second pin are not in the same horizontal plane.

3. The lead frame structure according to claim 2, wherein: The first pins and the second pins are staggered and distributed around the chip seat.

4. The lead frame structure according to claim 1, 2 or 3, wherein: The first end of the first pin is located higher than the first surface.

5. The lead frame structure according to claim 1, 2 or 3, wherein: The first pin further has a raised section at a middle position, two ends of the raised section are respectively connected to the first end and the second end, and the first end is higher than the second end.

6. The lead frame structure according to claim 1, wherein: The bottom surfaces of the second ends of the first pin and the second pin are in the same horizontal plane.

7. The lead frame structure according to claim 1, wherein: Used in a quad flat no-lead package structure.

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