Integrated circuit

Abstract

Various embodiments of the utility model relate to an integrated circuit, comprising a first SRAM cell and a second SRAM cell, each of which comprises a plurality of field effect transistors (FETs); a front metal line over the FET and a rear metal line under the FET; and an intermediate band region between the first SRAM cell and the second SRAM cell. The intermediate band region includes a plurality of gate stacks extending longitudinally in a direction, a gate isolation structure extending through the gate stacks of the plurality of gate stacks, a feed through via (FTV) embedded in the gate isolation structure, a first dielectric gate between the FTV and the first SRAM cell, and a second dielectric gate between the FTV and the second SRAM cell. The FTV is electrically coupled to the front metal line and the rear metal line.

Description

Technical Field

[0001] An embodiment of the utility model relates to an integrated circuit. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced successive generations of ICs, each with smaller and more complex circuits than the previous one. Over the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This process of shrinking dimensions often benefits by increasing production efficiency and reducing associated costs. However, this shrinking dimension also increases the complexity of IC processing and manufacturing.

[0003] Static random access memory (SRAM) is commonly used in integrated circuits. SRAM arrays (or macros) typically use a border / band region surrounding the array of bit cells storing data. This allows the outermost bit cells of the SRAM array to have a similar environment to the bit cells within it, resulting in more uniform bit cell operation regardless of the position of the bit cells in the SRAM array compared to an SRAM array without a border / band region. On the other hand, if the border / band region occupies a relatively large area, it may consume a significant portion of the total space available for manufacturing the memory device, thereby limiting scalability. Utility Model Content

[0004] One aspect of the present invention provides an integrated circuit. The integrated circuit includes a first SRAM cell and a second SRAM cell. The first SRAM cell includes a field-effect transistor (FET). The integrated circuit also includes a front interconnect structure above the FET, a back interconnect structure below the FET, and a mid-strip region located between the first and second SRAM cells. The mid-strip region adjoins the first SRAM cell at a first boundary and adjoins the second SRAM cell at a second boundary opposite the first boundary. The first SRAM cell includes a first contact on the first boundary, and the second SRAM cell includes a second contact on the second boundary. The mid-strip region includes a plurality of gate stacks and a plurality of dielectric gates extending longitudinally along a first direction and uniformly distributed at a gate pitch (GP), a gate isolation structure extending along a second direction perpendicular to the first direction, a third contact surrounded by the gate isolation structure, and a feedthrough via (FTV) contacting and surrounded by the gate isolation structure when viewed from above. The FTV resides on a bottom surface of the third contact and electrically couples the front and back interconnect structures through the third contact. The distance between the first and second boundaries is equal to or less than approximately 9 GP.

[0005] Another aspect of the present invention provides an integrated circuit. The integrated circuit includes a first SRAM cell and a second SRAM cell, each including a plurality of field effect transistors (FETs), a front metal line above the FETs and a back metal line below the FETs, and a middle band region located between the first SRAM cell and the second SRAM cell. The middle band region includes a plurality of gate stacks extending longitudinally along a direction, a gate isolation structure extending through the gate stacks of the plurality of gate stacks, a feedthrough via (FTV) embedded in the gate isolation structure, a first dielectric gate located between the FTV and the first SRAM cell, and a second dielectric gate located between the FTV and the second SRAM cell. The FTV electrically couples the front metal line and the back metal line.

[0006] Another aspect of the present invention provides an integrated circuit. The integrated circuit includes a first SRAM cell and a second SRAM cell, and an intermediate band region located between the first SRAM cell and the second SRAM cell. The first SRAM cell includes a device. The intermediate band region includes a plurality of gate stacks extending longitudinally along a first direction, a gate isolation structure extending through the gate stacks of the plurality of gate stacks, a feedthrough via (FTV) surrounded by the gate isolation structure when viewed from above, and a first active region and a second active region located on either side of the FTV and extending longitudinally along a second direction perpendicular to the first direction. The first active region and the second active region span from the first SRAM cell to the second SRAM cell. The FTV connects a front interconnect structure above the device and a rear interconnect structure below the device.

[0007] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a top view of a portion of an integrated circuit (IC) structure according to various aspects of the present disclosure.

[0009] Figure 2A and Figure 2B According to various aspects of the present invention Figure 1 Top view of region A of the IC structure.

[0010] Figure 3 、 Figure 5 、 Figure 6 、 Figure 7 、 Figure 8 、 Figure 9 、 Figure 10 、 Figure 11 、 Figure 12 、 Figure 13 、 Figure 14 、 Figure 15 、 Figure 16 、 Figure 17 、 Figure 18 and Figure 19 According to various aspects of the present invention Figure 1 A top view of a region 200 of an IC structure.

[0011] Figure 4 According to various aspects of the present invention, Figure 3 A cross-sectional view of the IC structure along line BB. DETAILED DESCRIPTION

[0012] It should be understood that the following utility model content provides many different embodiments or examples of different components for implementing the utility model content. Specific examples of components and arrangements are described below to simplify the utility model content. Of course, these are only examples and are not intended to be limiting. For example, the following description of forming a first component on or on a second component may include an embodiment in which the first component and the second component are formed to be in direct contact, and may also include an embodiment in which an additional component may be formed between the first component and the second component, thereby making it possible for the first component and the second component not to be in direct contact. In addition, the utility model content may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed. In addition, for the sake of brevity and clarity, the various components may be arbitrarily drawn in different proportions.

[0013] Furthermore, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," and the like may be used herein to describe the relationship of one component or part to another component or part shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures were turned upside down, a component originally described as "below" or "beneath" another component or part would have an orientation "above" the other component or part. Thus, the exemplary term "below" encompasses both orientations of "above" and "below." The device may have other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0014] In addition, when a number or a range of numbers is described using the word "about," "approximately," etc., the term is intended to encompass numbers that are within a reasonable range to account for variations that inherently occur during manufacturing, as understood by those skilled in the art. For example, based on known manufacturing tolerances associated with manufacturing components having the characteristics associated with the number, the number or range of numbers encompasses a reasonable range that includes the described number, such as within ±10% of the described number. For example, a material layer having a thickness of "about 5 nm" may cover a range of sizes from 4.25 nm to 5.75 nm, where the manufacturing tolerance associated with deposited material layers is known to those of ordinary skill in the art to be ±15%. Further, the present disclosure may reuse reference numbers and / or letters in various instances. Such repetition is for the purposes of brevity and clarity and does not itself indicate a relationship between the various embodiments and / or configurations discussed.

[0015] In a memory array, such as a static random access memory (SRAM) array, each memory cell can store one bit of data. The performance of the memory cells can depend significantly on the layout. For example, it has been observed that the interior memory cells of a memory array perform differently than the edge memory cells of the memory array. In some embodiments, the interior memory cells exhibit different threshold voltages (V t ), different on-current (I on ) and / or different off-current (I off Therefore, a middle strap area is implemented to stabilize the well potential, thereby promoting uniform charge distribution across the entire memory array, resulting in consistent performance across the memory cells of the memory array. While the middle strap area can be free of memory bits, it can require a relatively large area, increasing the total area of ​​the memory array.

[0016] The present invention generally relates to semiconductor devices, and more particularly to an integrated circuit (IC) (e.g., a memory device) having a middle band region, wherein the middle band region is sandwiched between two adjacent SRAM regions along a direction. The middle band region includes a plurality of gate structures and / or a plurality of dielectric gate structures uniformly distributed along the direction with a gate pitch (GP). The middle band region may include a gate isolation structure located above at least one of the plurality of gate structures or located above one of the plurality of gate structures. In addition, the middle band region includes a conductive structure surrounded by the gate isolation structure. The conductive structure includes a feedthrough via (FTV) and a conductive component located above the FTV. The FTV electrically couples the front side interconnect structure and the back side interconnect structure of the IC. By implementing the design layout disclosed herein, the middle band region has a reduced width along the direction that is equal to or less than about nine (9) times the GP. Details of the proposed IC with the middle band region are set forth below. Different embodiments may have different advantages, and no particular advantage is essential to any embodiment.

[0017] Figure 11 is a top view of a semiconductor device 10 (e.g., an integrated circuit (IC)) having a memory macro 100 according to various aspects of the present invention. The semiconductor device may include a substrate, a device layer (e.g., a transistor, etc.) above the substrate, a front-side interconnect structure above the device layer, and a back-side interconnect structure below the device layer and / or the substrate. The semiconductor device 10 may be, for example, a microprocessor, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or a digital signal processor (DSP). The exact function of the semiconductor device 10 does not limit the provided target. The memory macro 100 may be a single-port SRAM macro, a dual-port SRAM macro, or another type of memory macro. The memory macro 100 includes a plurality of memory bits for storage. In some embodiments, the semiconductor device 10 also includes peripheral logic circuitry (not shown) adjacent to the memory macro 100 for implementing various functions, such as write and / or read address decoders, word / bit selectors, data drivers, memory self-test, etc. Each memory bit and logic circuit can be implemented using various PMOS and NMOS transistors, such as planar transistors, fin field-effect transistors (FinFETs), gate-all-around (GAA) nanosheet transistors, GAA nanowire transistors, or other types of transistors. Furthermore, the memory macro 100 and logic circuits can include various contact features (or contacts), vias, and metal lines for connecting the source, drain, and gate electrodes (or terminals) of the transistors to form an integrated circuit.

[0018] Memory macro 100 includes one or more suitable memory devices, such as a static random-access memory (SRAM) structure, a dynamic random-access memory (DRAM) structure, a nonvolatile memory structure, other suitable memory structures, or a combination thereof. Furthermore, memory macro 100 includes one or more memory cells arranged in an array. For example, memory macro 100 includes a plurality of SRAM cells arranged in an array.

[0019] Memory macro 100 includes various doped components, such as an n-type doped well (also referred to as an N-well), a p-type doped well (also referred to as a P-well), source and drain components, other doped components, or combinations thereof, configured to form various devices or various components of a device (e.g., source and drain components of a field effect transistor). In this example, semiconductor device 10 includes a negatively doped well (also referred to as an N-well) and a positively doped well (also referred to as a P-well). The N-well includes a negative dopant, such as phosphorus. The P-well includes a positive dopant, such as boron. The N-well and the P-well are formed using suitable techniques, such as ion implantation, diffusion, or a combination thereof.

[0020] In some embodiments, semiconductor device 10 includes a substrate, and memory macro 100 may be formed on the substrate. In some embodiments, the substrate may be reduced at a later manufacturing stage. The substrate comprises silicon. Alternatively, the substrate may comprise an elemental semiconductor, such as silicon or germanium in a crystalline structure; a compound semiconductor, such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; or a combination thereof. Possible substrates also include silicon-on-insulator (SOI) substrates. SOI substrates are manufactured using separation by implantation of oxygen (SIMOX), wafer bonding, and / or other suitable methods.

[0021] The substrate also includes various isolation features, such as isolation features formed on the substrate and defining various active areas on the substrate. The isolation features utilize isolation technology, such as shallow trench isolation (STI), to define and electrically isolate the various active areas. Each active area is surrounded by a continuous isolation feature, separating each active area from other adjacent active areas. The isolation features include silicon oxide, silicon nitride, silicon oxynitride, other suitable dielectric materials, or combinations thereof. The isolation features are formed using any suitable process. As an example, forming the STI features includes a photolithography process to expose a portion of the substrate, etching a trench in the exposed portion of the substrate (e.g., using dry etching and / or wet etching), filling the trench with one or more dielectric materials (e.g., using a chemical vapor deposition process), and planarizing the substrate and removing excess dielectric material using a polishing process (e.g., a chemical mechanical polishing (CMP) process). In some examples, the filled trench may have a multilayer structure, such as a thermal oxide liner and a filler layer of silicon nitride or silicon oxide.

[0022] In some embodiments, semiconductor device 10 includes a front-side interconnect structure above memory macro 100. The front-side interconnect structure may include multiple patterned dielectric layers and conductive layers that provide interconnections (e.g., routing) between various microelectronic components (e.g., transistors such as FETs) formed within memory macro 100 and upper conductive features (e.g., conductive features above the front-side interconnect structure). As noted, the front-side interconnect structure may include multiple conductive features and multiple dielectric layers for providing isolation between the conductive features. In some embodiments, the dielectric layer of the front-side interconnect structure may include silicon oxide, a low-k dielectric layer (e.g., having a dielectric constant less than that of SiO2 (approximately 3.9)), other suitable dielectric materials, or combinations thereof. In some examples, the dielectric layer may include tetraethylorthosilicate (TEOS) oxide, undoped silicate glass (USG), doped silicon oxides such as borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG), a low-k dielectric layer, and / or other suitable dielectric materials.

[0023] In some embodiments, the conductive features of the front-side interconnect structure may include contacts, vias, or metal lines (e.g., metal lines in metal layers M0, M1, M2, ...) to provide horizontal and vertical interconnects. In some cases, the metal lines include copper (Cu), aluminum (Al), aluminum-copper (AlCu) alloys, ruthenium (Ru), cobalt (Co), tungsten (W), or other suitable metals. In some embodiments, the metal lines, contacts, and / or vias include a barrier layer and a bulk metal layer above the barrier layer.

[0024] In some embodiments, the semiconductor device 10 further includes a backside interconnect structure located below the memory macro 100. Similar to the frontside interconnect structure, the backside interconnect structure may include conductive components (e.g., metal lines and vias) distributed in one or more dielectric layers. The conductive components of the backside interconnect structure may provide interconnections (e.g., wiring) between various microelectronic components (e.g., transistors such as FETs) formed within the memory macro 100 and lower conductive components (e.g., conductive components below the backside interconnect structure). The metal lines of the backside interconnect structure may be disposed in a backside metal layer, such as BM0, BM1, etc. The frontside interconnect structure and the backside interconnect structure are coupled through various conductive components and feedthrough vias (FTVs). The structure, composition, configuration, and formation of the FTVs are described in further detail below.

[0025] Still refer to Figure 1Memory macro 100 includes two memory bit regions 115, a middle band region 105 (or band region 105) disposed between the two memory bit regions 115, two edge regions 125 disposed outside the two memory bit regions 115, two standard cell regions 135 disposed outside the two edge regions 125, two word line band regions 145 disposed at the ends of the two memory bit regions 115 and the two edge regions 125, and a dummy region 155. Middle band region 105 may be located in the middle portion of memory macro 100. In the depicted embodiment, the length of middle band region 105 is oriented along the Y direction. Standard cell region 135 includes one or more standard cells to be retrieved from a standard cell library and to be placed as part of an integrated circuit (e.g., a digital, analog, or other circuit module). Edge region 125 is a transition region inserted between memory bit regions 115 and standard cell region 135 to provide transition functions including isolation and integration.

[0026] In this embodiment, the middle band region 105, the two edge regions 125, and the dummy region 155 do not contain memory bits. The middle band region 105, the two edge regions 125, and the two word line band regions 145 can be used to implement a well pick-up (WPU) structure. Therefore, they are also referred to as well pick-up regions, for example, for providing voltage (or bias) to the N-well and P-well in the memory macro 100.

[0027] For relatively large memory macros, the voltage drop along the well may be large, which will result in insufficient bias voltage for the well in the middle portion of the memory macro. To address this problem, the memory macro 100 includes a middle band region 105. In various embodiments, depending on the size of the memory macro 100, the memory macro 100 may include more than one middle band region 105. The details of the middle band region 105 will be referred to in detail. Figures 3 to 19 Further discussion.

[0028] The two memory bit regions 115 contain all the memory bits (implemented in transistors) of the memory macro 100 . Figure 2A and Figure 2B According to various aspects of the present invention Figure 1 A top view (or layout) of region A of the two memory bit regions 115 is shown. Figure 2A and Figure 2B, the two memory bit regions 115 include P-wells 204 and N-wells 206 arranged alternately along the Y direction. In other words, each P-well 204 is adjacent to an N-well 206, and the N-well 206 is adjacent to another P-well 204, and this pattern repeats. The boundary between any two oppositely doped wells is represented by a dotted line 207. Above the wells, the two memory bit regions 115 include active regions 202a and 202b whose length directions are approximately oriented along the X direction perpendicular to the Y direction, and a gate structure 225 whose length directions are approximately oriented along the Y direction. The active regions 202a and 202b can be individually or collectively referred to as active regions 202. The active regions 202a and 202b are appropriately doped to form transistors. For example, the active region 202a is located above the P-well 204 and is doped with n-type dopants to form an NMOSFET, while the active region 202b is located above the N-well 206 and is doped with p-type dopants to form a PMOSFET. In Figure 2A In the illustrated embodiment, each active region 202a has a width W1 along the Y direction, each active region 202b has a width W2 along the Y direction, and W1 is greater than W2. Figure 2B In some alternative embodiments shown, each active region 202a has a width W3 along the Y direction, each active region 202b has a width W2 along the Y direction, and W3 is equal to W2. Figure 2A The width D1 of the P-well 204 is greater than Figure 2B 2. The active regions 202a and 202b may comprise a fin or fin active region for a FinFET, or in another embodiment, may comprise vertically stacked multiple nanowires or nanosheets for a gate-all-around (GAA) FET. The active regions 202a and 202b may take other suitable forms or shapes (e.g., planar active regions for planar MOSFETs). In one embodiment, the gate structure 225 may comprise a high-k metal gate (HK / MG) structure (i.e., one or more metal layers above a high-k gate dielectric layer), and in various embodiments, the gate structure 225 may comprise other materials and / or configurations. The gate structure 225 is bonded to the active regions 202a and 202b to form various transistors (not shown), such as an NMOS FinFET, a PMOS FinFET, an NMOS GAA FET, and a PMOS GAAFET. The gate structures 225 each include a gate dielectric layer and a gate electrode. The gate structure 225 is a component of the FET and functions in conjunction with other components, such as source / drain (S / D) components and a channel, where the channel is in the portion of the active area 202 directly below the gate structure 225; the S / D components are within the active area 202 and are located on both sides of the gate structure 225.

[0029] The transistors are properly coupled to form a memory bit. For example, the transistors in the dashed box 208 are coupled to form a memory bit, such as an SRAM cell. To facilitate this example, the SRAM cell includes two inverters and two transmission gates that are cross-coupled together. Each transmission gate also includes an N-type field effect transistor, and each inverter includes an N-type field effect transistor and a P-type field effect transistor that are properly connected. The two memory bit regions 115 also include a dielectric member 205 having a length generally oriented along the X direction. The dielectric member 205 can be positioned along a portion of a well boundary (indicated by dashed line 207) to isolate adjacent wells. Therefore, the dielectric member 205 is also referred to as an isolation member 205. In some embodiments, the dielectric member 205 is positioned along a portion of an SRAM cell boundary to isolate adjacent SRAM cells. In such embodiments, the dielectric member 205 is positioned between portions of adjacent active areas 202a to isolate adjacent active areas 202a. In an embodiment, the dielectric feature 205 is a gate cutting feature that divides an otherwise continuous gate structure into isolated segments corresponding to the depicted gate structure 225 .

[0030] In the depicted embodiment, the memory macro 100 also includes various contacts (e.g., contacts 210 and 215) and a through-hole 212 above the active areas 202a and 202b. The contacts 210 and 215 and the through-hole 212 can connect various portions (e.g., source, drain, and / or gate stack) on or above the active areas 202a and 202b to the front-side interconnect structure above the SRAM cell. For example, the contact 210 can be a source / drain contact that connects the source / drain to the front-side interconnect structure above the SRAM cell. It should be understood that the position, shape, and size of each contact 210 and 215 and the through-hole 212 are not limited to the embodiments depicted in the present invention. For the sake of brevity, the contacts 210 and the through-hole 212 are not shown in the following figures.

[0031] refer to Figure 3 , which shows some aspects of the content of the present utility model Figure 1 FIG2 is a top view (or layout) of region 200 of FIG2 . A dashed box 208 shows the locations of two SRAM cells in two memory bit regions 115 . The middle band region 105 includes P-wells 204 and N-wells 206 arranged alternately along the Y direction. The boundary between the P-wells 204 and N-wells 206 is indicated by a dashed line 207 . In some embodiments, the P-wells 204 and N-wells 206 in the middle band region 105 extend continuously into the two memory bit regions 115 . In other words, the P-wells 204 in the middle band region 105 and the two memory bit regions 115 may be part of the same P-well, and the N-wells 206 in the middle band region 105 and the two memory bit regions 115 may be part of the same N-well.

[0032] The middle band region 105 also includes an active region 202a above the P-well 204 and an active region 202b above the N-well 206. The active regions 202a and 202b may be individually or collectively referred to as active regions 202. The length directions of the active regions 202a and 202b are generally oriented along the X-direction. In the depicted embodiment, the active region 202a in the middle band region 105 extends continuously into both memory bit regions 115. In other words, the active region 202a in the middle band region 105 and the active regions 202a in both memory bit regions 115 may be portions of the same active region 202a. The continuous active region 202a may provide benefits (e.g., reduced process steps) when the middle band region 105 and the two memory bit regions 115 are manufactured together. The continuous active region 202a may reduce the distance between the boundary 211 between the middle band region 105 and the two memory bit regions 115. The boundary 211 is also the boundary of the SRAM cell adjacent to the middle band region 105. In some embodiments, the active area 202b in the middle band region 105 is aligned with the active areas 202b in the two memory bit regions 115 along the X direction, but they are separated from each other. In some other embodiments, the active area 202b in the middle band region 105 extends continuously to one of the two memory bit regions 115. In some embodiments, the active area 202b in the middle band region 105 extends continuously to one of the two memory bit regions 115. Figure 2A Similarly, the active regions 202a and 202b have widths W1 and W2 along the Y direction, respectively. The distance between adjacent active regions 202a and 202b is S1. Figure 3 shown.

[0033] The active regions 202a and 202b in the middle band region 105 can have the same shape and configuration as the active regions 202a and 202b in the two memory bit regions 115. For example, the active regions 202a and 202b have widths W1 and W2 along the Y direction, respectively. For example, the active regions 202a and 202b have a channel region directly below a gate structure 225 (described below) and doped regions (e.g., source / drain regions) on either side of the gate structure 225. In some embodiments, the active region 202a above the P-well 204 can be doped with n-type dopants to form an NMOSFET, and the active region 202b above the N-well 206 can be doped with p-type dopants to form a PMOSFET. Alternatively, the active regions 202a and 202b in the middle band region 105 can include fins or fin active regions, multiple vertically stacked nanowires or nanosheets, or planar active regions.

[0034] The middle band region 105 further includes a gate structure 225 (also referred to as a gate stack 225) whose length is generally oriented along the Y direction. The gate structure 225 in the middle band region 105 can have the same shape and configuration as the gate structures 225 in the two memory bit regions 115. For example, in one embodiment, the gate structure 225 can include a high-k metal gate (HK / MG) structure, and in various embodiments, the gate structure 225 can include other materials and / or configurations.

[0035] The middle band region 105 also includes an isolation feature 205 whose length is generally oriented along the X-direction. The isolation feature 205 is disposed along portions of the well boundaries (indicated by dashed lines 207) to isolate adjacent wells. The isolation feature 205 is also disposed between adjacent active regions 202a to isolate adjacent active regions 202a. In one embodiment, the isolation feature 205 is a gate cut feature that divides an otherwise continuous gate structure into isolation segments corresponding to the depicted gate structures 225. In some embodiments, the isolation feature 205 extends from the middle band region 105 to both memory bit regions 115. In some other embodiments, the isolation feature 205 extends within the middle band region 105. This effectively reduces leakage between oppositely doped wells 204 and 206 and reduces leakage between adjacent active regions 202a. The isolation feature 205 also separates a portion or all of the gate structures 225 in the middle band region 105. Portions of the active region 202 a located between adjacent feedthrough structures 240 (described below) and the isolation features 205 therebetween provide isolation between the adjacent feedthrough structures 240 .

[0036] Still refer to Figure 3 The intermediate zone region 105 further includes two dielectric gates 230 disposed above the active regions 202a and 202b in the intermediate zone region 105. The dielectric gates 230 are not metal gates and do not function as gate structures. Instead, the dielectric gates 230 are dielectric components that include one or more dielectric materials and, in some cases, function as isolation components.

[0037] Each dielectric gate 230 has an elongated shape oriented along the Y direction. In some embodiments, the dielectric gate 230 is formed in a continuous-poly-on-diffusion-edge (CPODE) process. In the CPODE process, at least a portion of the polysilicon gate (also called a dummy gate) and the channel region of the active region below it are replaced by a dielectric component. For the purposes of the present disclosure, a "diffusion edge" may be equivalently referred to as an active edge, where, for example, the active edge is adjacent to an adjacent active region. The dielectric gate 230 is also referred to as a CPODE component 230. The dielectric gate 230 may extend vertically into the substrate. The dielectric gate 230 may have a length along the Y direction of about 1 μm to about 400 μm. In addition, the dielectric gate 230 may be arranged and configured in different ways and therefore have different functions. In some embodiments, the dielectric gate 230 and the gate structure 225 are uniformly distributed with a gate pitch (GP). Figure 3 , an example of gate spacing is shown as the edge-to-edge distance between two adjacent gate structures 225 and / or dielectric gates 230, or in some embodiments, as a center-to-center distance rather than an edge-to-edge distance. In some embodiments, the width of the gate structures 225 or dielectric gates 230 is much smaller than the GP, so the distance between two adjacent gate structures 225 and / or dielectric gates 230 is approximately the same as the GP. In the depicted embodiment, two dielectric gates 230 extend through the active region 202a and are disposed at the edges (or ends) of the active region 202b in the middle band region 105 to serve as isolation between one SRAM cell and an adjacent SRAM cell. The presence of dielectric gates 230 can avoid or reduce mushroom defects, which are undesirable epitaxial growth on excess portions of a dummy gate (e.g., at the edges or ends of the active region 202b), which may be caused by overlay shift of the lithography mask during dummy gate formation.

[0038] Still refer to Figure 3 The intermediate strip region 105 further includes a gate isolation structure 235 disposed between the two dielectric gates 230. In the depicted embodiment, the length direction of the gate isolation structure 235 extends along the X direction and extends through the gate structure 225 to separate the gate structures 225, and the gate isolation structure 235 is disposed between the two dielectric gates 230. The gate isolation structure 235 can provide isolation between the feedthrough structure 240 and the adjacent active regions 202a and 202b and the gate structure 225.

[0039] Figure 4 Some aspects of the present invention are shown along Figure 3BB. The gate isolation structure 235 may include any suitable material, such as a dielectric material, including silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The gate isolation structure 235 is a dielectric structure implemented to cut a long gate stack into two or more shorter gate stacks. The gate isolation structure 235 is formed by patterning, which includes photolithography and etching; deposition and polishing, such as chemical mechanical polishing (CMP). The gate isolation structure 235 and other dielectric layers also provide an environment in which the FTV is placed. Therefore, in this particular case, the gate isolation structure 235 and other dielectric layers are collectively referred to as the gate isolation structure 235. In some embodiments, the gate isolation structure 235 includes multiple dielectric layers. In some instances, the gate isolation structure 235 includes an interlayer dielectric (ILD) layer 236, etch stop layers (ESL) 237 and 239, and a dielectric layer 238. ILD layer 236 may include silicon oxide, a material containing silicon oxide, or a low-k dielectric layer, such as TEOS oxide, undoped silicate glass (USG), doped silicon oxide (e.g., BPSG, FSG, PSG, BSG), and / or other suitable dielectric materials. In some embodiments, ILD layer 236 includes silicon oxide or a material containing silicon oxide. In various examples, ILD layer 236 may be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or a combination thereof. In some cases, ESLs 237 and 239 may include nitrogen-containing and / or carbon-containing materials. For example, ESLs 237 and 239 may include silicon carbonitride (SiCN), silicon oxycarbide (SiOC), silicon carbide (SiC), silicon oxycarbonitride (SiOCN), silicon nitride (SiN), or a combination thereof. In some embodiments, ESLs 237 and 239 include SiN. In various examples, ESLs 237 and 239 may be deposited by CVD, ALD, PVD, or a combination thereof. In some embodiments, dielectric layer 238 includes a similar material as ILD layer 236. In various examples, dielectric layer 238 can be deposited by CVD, ALD, PVD, or a combination thereof.

[0040] In some embodiments, see Figure 3 and Figure 4 The middle band region 105 further includes a feedthrough structure 240 surrounded by each gate isolation structure 235 when viewed from above. The feedthrough structure 240 is a conductive structure that electrically couples the front-side interconnect structure (e.g., the metal line in the M0 metal layer) to the back-side interconnect structure (e.g., the metal line in the BM0 metal layer). Figure 4In some embodiments, the feedthrough structure 240 includes a feedthrough via (FTV) 245 above the BMO layer, a lower contact member 250 above the FTV 245, and an upper contact member 255 above the lower contact member 250. The FTV 245, the lower contact member 250, and the upper contact member 255 can have the same or different shapes and / or sizes when viewed from above. In some embodiments, the FTV 245, the lower contact member 250, and the upper contact member 255 are embedded in the gate isolation structure 235. The FTV 245, the lower contact member 250, and the upper contact member 255 can be formed by performing patterning and photolithography processes to form trenches through a portion of the gate isolation structure 235 and then filling the trenches with metal members. In some embodiments, the FTV 245, the lower contact member 250, and the upper contact member 255 each include Cu, Al, an AlCu alloy, Ru, Co, W, or other suitable metal layers. In some embodiments, the FTV 245, the lower contact feature 250, and the upper contact feature 255 each include a barrier layer (e.g., barrier layers 251a and 251b) and a bulk metal layer over the barrier layer. In some embodiments, the lower contact feature 250 is formed simultaneously with and / or at the same level as the source / drain contacts in the memory bit region 115.

[0041] Return Reference Figure 3 The feedthrough structure 240, the gate isolation structure 235, the surrounding area of ​​the gate isolation structure 235, and a portion of the dielectric gate 230 together form an isolation region 260. The isolation region 260 is disposed between the two active regions 202a along the Y direction and between the two groups of active regions 202b along the X direction to provide an isolation function. Each of the two groups of active regions 202b includes two active regions 202b. In the illustrated embodiment, the isolation region 260 extends between the ends of the two groups of active regions 202b and has a rectangular shape. The length D3 of the isolation region 260 along the X direction is approximately four (4) times the length of GP. The isolation region 260 can provide isolation between adjacent active regions 202a and 202b and isolation between two memory bit regions 115.

[0042] refer to Figure 3 , the distance D4 between the boundaries 211 of the middle strip region 105 is approximately nine (9) times GP. In some embodiments, the middle strip region 105 includes a total of nine (9) gate structures 225 and dielectric gates 230. The boundaries 211 include the boundaries 211 between the middle strip region 105 and the memory bit region 115 adjacent to the left and the boundaries 211 between the middle strip region 105 and the memory bit region 115 adjacent to the right.

[0043] refer to Figure 5 , which shows an alternative aspect according to the content of the present invention Figure 1For example, in Figure 5 In, with Figure 3 Compared to the region 200 in FIG. 2 , the dielectric gate 230 does not extend through the active region 202a. Instead, the dielectric gate 230 extends through the active region 202a. Figure 3 The portion of the active region 202a in the middle band region 105 is replaced by the gate structure 225. In some embodiments, the dielectric gate 230 is still disposed on the edge (or end) of the active region 202b in the middle band region 105. The dielectric gate 230 can avoid or reduce the following problems: Figure 3 Each dielectric gate 230 may have a length L1 along the Y direction. In some embodiments, the width of each active region 202b is W2, the distance between adjacent active regions 202a and 202b is S1, and the length L1 is approximately (2*W2+2*S1). In some embodiments, the channel regions of the active region 202 each have a channel length G1 along the X direction. In some embodiments, the ratio of W2 to G1 (W2 / G1) is in a range of about 0.5 to about 10. In some embodiments, the ratio of S1 to G1 (S1 / G1) is in a range of about 1 to about 10. In some embodiments, the ratio of L1 to G1 (L1 / G1) is in a range of about 1 to about 40.

[0044] refer to Figure 6 , which shows another alternative aspect according to the content of the present invention Figure 1 For example, in Figure 6 In, with Figure 3 Compared to region 200 in FIG. 1 , the dielectric gate 230 is completely replaced with two gate structures 225. In this embodiment, the gate structures 225 can be connected to a bias power supply to provide better isolation and further enhance device performance. In some embodiments, due to differences in manufacturing methods and composition, device performance may be subject to risks or damage from CPODE components. The absence of CPODE components in the intermediate band region 105 eliminates these risks.

[0045] refer to Figure 7 , which shows another alternative aspect according to the content of the present invention Figure 1 For example, in Figure 7 In, with Figure 3Compared to the region 200 in the middle strip region 105, the active region 202a is divided into an active region 202a-1 extending in the middle strip region 105 and an active region 202a-2 extending from the middle strip region 105 to one of the memory bit regions 115. In some embodiments, the dielectric gate 230 is disposed on the edges (or ends) of the active regions 202a-2 and 202b in the middle strip region 105. The dielectric gate 230 can avoid or reduce the following problems: Figure 3 The mushroom defect in FIG. 2 is depicted as extending to the edge (or end) of active regions 202 a - 2 and 202 b . The discontinuous active region 202 a provides more isolation between the two memory bit regions 115 .

[0046] refer to Figure 8 , which shows another alternative aspect according to the content of the present invention Figure 1 For example, in Figure 8 In, with Figure 7 Compared to the region 200 in FIG. 2 , the dielectric gate 230 is completely replaced by two gate structures 225. In this embodiment, since there is no CPODE component in the middle band region 105, similar advantages or benefits may be presented.

[0047] refer to Figure 9 , which shows another alternative aspect according to the content of the present invention Figure 1 For example, in Figure 9 In, with Figure 3 Compared to the region 200 in FIG. 1 , the middle strip region 105 eliminates the dummy regions 265 on each side of the isolation region 260 and eliminates the active region 202 b that extends only in the middle strip region 105. As a result, the distance D5 between the boundaries 211 of the middle strip region 105 is reduced from D4 to approximately seven (7) times GP. In some embodiments, the middle strip region 105 includes a total of seven (7) gate structures 225 and dielectric gates 230.

[0048] Due to the elimination Figure 3 The active region 202b extends only in the middle zone region 105, so Figure 9In the illustrated embodiment, the isolation region 260 has an upright or inverted "T" shape when viewed from above. The "T" shape includes a longer strip 260-1 and a shorter strip 260-2. The longer strip 260-1 extends between two active regions 202b that extend only in two memory bit regions 115. The longer strip 260-1 can have a length along the X direction of approximately eight (8) times GP. The shorter strip extends between two active regions 202b, each of which extends from the intermediate strip region 105 to one of the memory bit regions 115. The shorter strip 260-2 can have a length along the X direction of approximately four (4) times GP. In some embodiments, the distance D6 along the X direction between the edges of the longer strip 260-1 and the shorter strip 260-2 is approximately two (2) times GP. In some embodiments, the distance D7 between the longer strip 260-1 and the adjacent active region 202a is approximately half the distance S1. In some embodiments, the distance D8 between the shorter strip 260-2 and the adjacent active region 202a is approximately half the distance S1. The isolation region 260 can provide isolation between adjacent active regions 202a and 202b, and isolation between two memory bit regions 115. Figure 3 Compared with the middle zone area 105, Figure 9 The middle zone 105 in FIG has a smaller distance between the two boundaries 211 and an increased area of ​​the isolation region 260. This can be represented by Figure 3 Compared with reference Figure 9 The embodiment reduces the area of ​​the intermediate strip region 105 , increases the isolation between the two memory bit regions 115 , and increases the isolation between the feedthrough structure 240 and the active area 202 .

[0049] refer to Figure 10 , which shows another alternative aspect according to the content of the present invention Figure 1 For example, in Figure 10 In, with Figure 9 Compared to the region 200 in FIG. 1 , a portion of the active area 202b extending from one of the memory bit regions 115 to the intermediate band region 105 is eliminated. Thus, the shorter strip 260-2 extends toward the memory bit region 115 and between the shortened active areas 202b. In the illustrated embodiment, the distance D9 along the X direction between the edges of the longer strip 260-1 and the shorter strip 260-2 is approximately 1 GP and less than Figure 9 D6 in. Figure 10 The area of ​​the isolation region 260 is larger than Figure 9 The area of ​​the isolated region 260 is shown in FIG. Figure 9 Compared with reference Figure 10The embodiment increases the isolation between the two memory bit regions 115 and increases the isolation between the feedthrough structure 240 and the active area 202 .

[0050] refer to Figure 11 , which shows another alternative aspect according to the content of the present invention Figure 1 For example, in Figure 11 In, with Figure 9 Compared to the region 200 in FIG. 2 , the dielectric gate 230 does not extend through the active region 202a. Instead, the dielectric gate 230 extends through the active region 202a. Figure 9 The active region 202a in the dielectric layer is replaced by the gate structure 225. The dielectric gate 230 is connected to the reference Figure 5 The dielectric gates described are similar except that each dielectric gate 230 is only on the edge of one active region 202b and Figure 11 L1 can be from about (W2+S1) to about (2*W2+2*S1).

[0051] refer to Figure 12 , which shows another alternative aspect according to the content of the present invention Figure 1 For example, in Figure 12 In, with Figure 9 Compared to the region 200 in FIG. 2 , the dielectric gate 230 is completely replaced by two gate structures 225. In this embodiment, since there is no CPODE component in the middle band region 105, similar advantages or benefits may be presented.

[0052] refer to Figure 13 , which shows another alternative aspect according to the content of the present invention Figure 1 For example, in Figure 13 In, with Figure 3 Compared to the region 200 in the middle zone, the active regions 202a and 202b have the same width along the Y direction, and the active region 202 further includes an active region 202c in the P well 204 disposed in the middle zone region 105. The active region 202a is not as Figure 3 Instead of extending continuously from one memory bit region 115 to another memory bit region 115, Figure 13 In FIG. 1 , the active region 202a extends continuously from one of the memory bit regions 115 to the middle band region 105. Figure 2BSimilarly, active regions 202a and 202b have widths W3 and W2, respectively, along the Y direction, with W2 being equal to W3. In each P-type well, an active region 202c is disposed along the X direction between the two sets of active regions 202a in the two memory bit regions 115. Each of the two sets of active regions 202a includes two active regions 202a. In some embodiments, each active region 202c has a length W4 along the Y direction. In some embodiments, W4 is greater than W2 or W3 and less than the width D2 of each P-type well 204 along the Y direction. In some embodiments, W4 is approximately (2*W3+S1). In some embodiments, each active region 202c has a width W5 along the X direction, which is approximately twice the width of GP.

[0053] Figure 13 and Figure 3 Another difference between the regions 200 in Figure 13 , the gate isolation structure 235 does not extend through the gate structure 225, but rather the gate isolation structure 235 extends through the dielectric gate 230. In the depicted embodiment, the intermediate strip region 105 includes three dielectric gates 230 and the gate isolation structure 235 extends through the three dielectric gates 230. In some embodiments, the dielectric gates 230 extend through the active region 202c and / or are disposed on the edges (or ends) of the active region 202c. In some embodiments, one of the dielectric gates 230 extends through the active region 202c and both of the dielectric gates 230 are disposed on the edges (or ends) of the active region 202c. In some embodiments, the gate structure 225 is disposed above and / or on the edges of the active regions 202a and 202b. In the depicted embodiment, the distance D10 between the boundaries 211 of the intermediate strip region 105 is approximately nine (9) times GP.

[0054] refer to Figure 14 , which shows another alternative aspect according to the content of the present invention Figure 1 For example, in Figure 14 In, with Figure 3 2. As compared to the region 200 in FIG. 2, the active region 202a and the active region 202b have widths W3 and W2, respectively, along the Y direction, with W2 being equal to W3. In the depicted embodiment, the distance D11 between the boundaries 211 of the intermediate strip region 105 is approximately nine (9) times GP. The portion of the active region 202a between adjacent feedthrough structures 240 and the isolation features 205 therebetween provide isolation between the adjacent feedthrough structures 240.

[0055] refer to Figure 15 , which shows another alternative aspect according to the content of the present invention Figure 1For example, in Figure 15 In, with Figure 14 Compared to the region 200 in FIG. 2 , the dielectric gate 230 does not extend through the active region 202a. Instead, the dielectric gate 230 extends through the active region 202a. Figure 14 The active region 202a in the dielectric layer is replaced by the gate structure 225. The dielectric gate 230 is connected to the reference Figure 5 Similar to what described.

[0056] refer to Figure 16 , which shows another alternative aspect according to the content of the present invention Figure 1 For example, in Figure 16 In, with Figure 14 Compared to the region 200 in FIG. 2 , the dielectric gate 230 is completely replaced by two gate structures 225. In this embodiment, since there is no CPODE component in the middle band region 105, similar advantages or benefits may be presented.

[0057] refer to Figure 17 , which shows another alternative aspect according to the content of the present invention Figure 1 For example, in Figure 17 In, with Figure 14 Compared to the region 200 in the middle strip region 105, the middle strip region 105 eliminates the dummy region 267 and one of the active regions 202b extending from each side of the isolation region 260 in the middle strip region 105. Therefore, the distance D12 between the boundaries 211 of the middle strip region 105 is reduced from D11 to approximately seven (7) times GP.

[0058] Due to the cancellation Figure 14 One of the active regions 202b extending in the intermediate band region 105 on each side of the isolation region 260, thus Figure 17 In the embodiment shown, the isolation region 260 has an upright or inverted "T" shape when viewed from above, similar to the reference Figure 9 Although not shown, the isolation area 260 is described. Figure 17 The isolation region 260 in the Figure 10 In other words, the distance between the edges of the longer strip 260-1 and the shorter strip 260-2 of the isolation region 260 along the X direction can be one or two times the GP. Figure 14 compared to, Figure 17 The middle zone region 105 in FIG has a smaller distance between the two boundaries 211 and an increased area of ​​the isolation region 260. This can be represented by Figure 14 Compared with reference Figure 17The embodiment reduces the area of ​​the intermediate strip region 105 , increases the isolation between the two memory bit regions 115 , and increases the isolation between the feedthrough structure 240 and the active area 202 .

[0059] refer to Figure 18 , which shows another alternative aspect according to the content of the present invention Figure 1 For example, in Figure 18 In, with Figure 17 Compared to the region 200 in FIG. 2 , the dielectric gate 230 does not extend through the active region 202a. Instead, the dielectric gate 230 extends through the active region 202a. Figure 17 The active region 202a in the dielectric layer is replaced by the gate structure 225. The dielectric gate 230 is connected to the reference Figure 11 Similar to what described.

[0060] refer to Figure 19 , which shows another alternative aspect according to the content of the present invention Figure 1 For example, in Figure 19 In, with Figure 17 Compared to the region 200 in FIG. 1 , the dielectric gate 230 is entirely replaced by two gate structures 225. In such an embodiment, similar advantages or benefits may be exhibited due to the absence of CPODE components in the intermediate band region 105.

[0061] Although not intended to be limiting, embodiments of the present invention provide one or more of the following advantages. For example, by implementing the various layouts disclosed herein, the semiconductor device disclosed herein has a mid-band region with a reduced width and reduced area. Compared to a conventional mid-band region and a conventional memory macro, the width of the mid-band region is equal to or less than approximately 9 times the gate pitch (GP), the area of ​​the mid-band region is reduced by approximately 30% to approximately 46%, and the area of ​​the memory macro is reduced by approximately 3% to approximately 4%. Additionally, in some embodiments, mushroom defects are avoided by implementing CPODE components at the ends of the active region. The mid-band region disclosed herein also includes pickup structures, such as feedthrough vias, to achieve consistent performance across memory cells of the memory macro.

[0062] In one exemplary embodiment, the present invention is directed to an integrated circuit (IC) comprising a first SRAM cell and a second SRAM cell. The first SRAM cell comprises a field effect transistor (FET). The IC further comprises a front interconnect structure above the FET and a rear interconnect structure below the FET, and a mid-strip region located between the first SRAM cell and the second SRAM cell. The mid-strip region adjoins the first SRAM cell on a first boundary and adjoins the second SRAM cell on a second boundary opposite the first boundary. The first SRAM cell comprises a first contact on the first boundary, and the second SRAM cell comprises a second contact on the second boundary. The mid-strip region comprises a plurality of gate stacks and a plurality of dielectric gates extending longitudinally along a first direction and uniformly distributed with a gate pitch (GP), a gate isolation structure extending along a second direction perpendicular to the first direction, a third contact surrounded by the gate isolation structure, and a feedthrough via (FTV) contacting the gate isolation structure and surrounded by the gate isolation structure when viewed from above. The FTV resides on a bottom surface of the third contact and electrically couples the front interconnect structure and the rear interconnect structure through the third contact. A distance between the first boundary and the second boundary is equal to or less than about 9 GP.

[0063] In one embodiment, the plurality of dielectric gates include a first dielectric gate and a second dielectric gate located on either side of the gate isolation structure, such that the first dielectric gate and the second dielectric gate sandwich the gate isolation structure along the second direction. In one embodiment, the integrated circuit further includes a first active region and a second active region extending from the first SRAM cell to the intermediate band region along the second direction. The first active region and the second active region have different widths along the first direction. In one embodiment, the integrated circuit further includes a first active region extending from the first SRAM cell to the second SRAM cell along the second direction and adjacent to the gate isolation structure. In one embodiment, the integrated circuit further includes a second active region extending from the first SRAM cell to the intermediate band region and extending longitudinally along the second direction. In one embodiment, the plurality of dielectric gates include a dielectric gate located on an edge of the second active region. In one embodiment, the dielectric gate further extends through the first active region. In one embodiment, the FTV extends through a dielectric gate of the plurality of dielectric gates.

[0064] In another example aspect, the present invention is directed to an integrated circuit (IC) comprising a first SRAM cell and a second SRAM cell, each comprising a plurality of field effect transistors (FETs), a front metal line above the FETs and a back metal line below the FETs, and a mid-strip region between the first SRAM cell and the second SRAM cell. The mid-strip region comprises a plurality of gate stacks extending longitudinally along a direction, a gate isolation structure extending through the gate stacks of the plurality of gate stacks, a feedthrough via (FTV) embedded in the gate isolation structure, a first dielectric gate between the FTV and the first SRAM cell, and a second dielectric gate between the FTV and the second SRAM cell. The FTV electrically couples the front metal line and the back metal line.

[0065] In one embodiment, the intermediate strip region further includes a first contact located above the top surface of the FTV and embedded in the gate isolation structure, and a second contact located above the top surface of the first contact, such that the FTV is electrically coupled to the front metal line and the rear metal line via the first contact and the second contact. In one embodiment, the direction is a first direction, and the integrated circuit further includes a continuous active region extending along a second direction perpendicular to the first direction through the first SRAM cell, the intermediate strip region, and the second SRAM cell. In one embodiment, the first dielectric gate and the second dielectric gate are directly disposed on the continuous active region. In one embodiment, the continuous active region is a first continuous active region, and the integrated circuit further includes a second continuous active region extending along the second direction through the first SRAM cell, the intermediate strip region, and the second SRAM cell. In one embodiment, the first dielectric gate and the second dielectric gate are directly disposed on the first continuous active region and the second continuous active region. In one embodiment, the direction is the first direction, and the integrated circuit further includes a continuous active region extending along the second direction perpendicular to the first direction from the first SRAM cell to the intermediate strip region. The first dielectric gate is directly disposed on an edge of the continuous active region.

[0066] In yet another example aspect, the present invention is directed to an integrated circuit (IC) comprising a first SRAM cell and a second SRAM cell, and an intermediate band region located between the first SRAM cell and the second SRAM cell. The first SRAM cell comprises a device. The intermediate band region comprises a plurality of gate stacks extending longitudinally along a first direction, a gate isolation structure extending through the gate stacks of the plurality of gate stacks, a feedthrough via (FTV) surrounded by the gate isolation structure when viewed from above, and a first active region and a second active region located on either side of the FTV and extending longitudinally along a second direction perpendicular to the first direction. The first active region and the second active region span from the first SRAM cell to the second SRAM cell. The FTV connects a front interconnect structure above the device and a rear interconnect structure below the device.

[0067] In one embodiment, the integrated circuit further includes a third active region extending from the first SRAM cell to the intermediate band region, and a fourth active region extending from the intermediate band region to the second SRAM cell. The third active region and the fourth active region are aligned and separated from each other by a gate isolation structure. In one embodiment, the integrated circuit further includes a third active region and a fourth active region located on either side of the FTV and extending longitudinally along the second direction. The FTV is disposed between the third active region and the fourth active region along the first direction. In one embodiment, the intermediate band region further includes a first dielectric gate extending along the first direction and disposed directly above the first active region and the second active region. In one embodiment, the intermediate band region further includes a first dielectric gate extending along the first direction and sandwiched between the first active region and the second active region along the first direction.

[0068] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An integrated circuit, characterized in that: include: a first static random access memory cell and a second static random access memory cell, wherein the first static random access memory cell comprises a field effect transistor; a front interconnect structure above the field effect transistor and a rear interconnect structure below the field effect transistor; and a middle zone region located between the first static random access memory cell and the second static random access memory cell, wherein the middle band region is adjacent to the first SRAM cell on a first boundary and is adjacent to the second SRAM cell on a second boundary opposite to the first boundary, wherein the first SRAM cell includes a first contact on the first boundary, and the second SRAM cell includes a second contact on the second boundary, and The intermediate zone includes: A plurality of gate stacks and a plurality of dielectric gates extend longitudinally along a first direction and are uniformly distributed with a gate pitch (GP), a gate isolation structure extending along a second direction perpendicular to the first direction, a third contact surrounded by the gate isolation structure, and a feedthrough hole, contacting the gate isolation structure and surrounded by the gate isolation structure when viewed from a top view, wherein the feedthrough via falls on a bottom surface of the third contact and electrically couples the front interconnect structure and the rear interconnect structure through the third contact, Wherein a distance between the first boundary and the second boundary is equal to or less than about 9 GP.

2. The integrated circuit according to claim 1, wherein: The plurality of dielectric gates include: The first dielectric gate and the second dielectric gate are located on both sides of the gate isolation structure, so that the first dielectric gate and the second dielectric gate sandwich the gate isolation structure along the second direction.

3. The integrated circuit according to claim 1, wherein: The device further includes a first active region and a second active region extending from the first static random access memory cell to the middle zone along the second direction. The first active region and the second active region have different widths along the first direction.

4. An integrated circuit, characterized in that: include: The first static random access memory cell and the second static random access memory cell each include a plurality of field effect transistors; a front metal line above the field effect transistor and a rear metal line below the field effect transistor; as well as a middle zone region located between the first static random access memory cell and the second static random access memory cell, The intermediate zone includes: Multiple gate stacks extend longitudinally along the direction, a gate isolation structure extending through a gate stack of the plurality of gate stacks, a feedthrough via embedded in the gate isolation structure, wherein the feedthrough via electrically couples the front metal line and the back metal line, a first dielectric gate located between the feedthrough via and the first SRAM cell, and A second dielectric gate is located between the feedthrough via and the second SRAM cell.

5. The integrated circuit according to claim 4, wherein: The intermediate zone also includes: a first contact located above a top surface of the feedthrough via and embedded in the gate isolation structure, and A second contact is located above a top surface of the first contact such that the feedthrough via electrically couples the front metal line and the back metal line through the first contact and the second contact.

6. The integrated circuit according to claim 4, wherein: The direction is a first direction, and the integrated circuit further includes a continuous active region extending along a second direction perpendicular to the first direction through the first SRAM cell, the middle band region, and the second SRAM cell.

7. The integrated circuit according to claim 4, wherein: The direction is a first direction, the integrated circuit further comprising a continuous active region extending from the first static random access memory cell to the intermediate band region along a second direction perpendicular to the first direction, The first dielectric gate is directly disposed on an edge of the continuous active area.

8. An integrated circuit, characterized in that: include: a first SRAM cell and a second SRAM cell, wherein the first SRAM cell comprises a device; and a middle zone region located between the first static random access memory cell and the second static random access memory cell, The intermediate zone includes: A plurality of gate stacks extending longitudinally along a first direction, a gate isolation structure extending through a gate stack of the plurality of gate stacks, a feedthrough hole, surrounded by the gate isolation structure when viewed from above, and A first active region and a second active region are located on both sides of the feedthrough hole and extend longitudinally along a second direction perpendicular to the first direction, wherein the first active area and the second active area span from the first static random access memory cell to the second static random access memory cell, and wherein the feedthrough via connects a front interconnect structure above the device and a rear interconnect structure below the device.

9. The integrated circuit according to claim 8, wherein: The intermediate zone region further includes a first dielectric gate extending along the first direction and directly disposed above the first active region and the second active region.

10. The integrated circuit according to claim 8, wherein: The intermediate zone region further includes a first dielectric gate extending along the first direction and sandwiched between the first active region and the second active region along the first direction.

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