Semiconductor assembly

Abstract

The utility model relates to a semiconductor assembly, which comprises a semiconductor substrate and a transistor on the semiconductor substrate. The transistor includes first and second S / D features, a channel region extending between the first and second S / D features, and a gate stack contacting the channel region. The semiconductor component includes: a first S / D contact structure landing on a top surface of a first S / D feature; a second S / D contact structure landing on a top surface of the second S / D feature; and a dielectric plug penetrating the semiconductor substrate and landing on a bottom surface of the first S / D feature. A width of the dielectric plug is equal to or less than a width of the first S / D feature. Unlimited, one advantage of the utility model is that the dielectric plug formed from the back side of the substrate is in the vertical direction and deviates from the gate structure, so that the gate dielectric layer is prevented from being damaged. Another exemplary advantage is from additionally etching the epitaxial structure of the S / D feature, which further reduces parasitic capacitance. Yet another exemplary advantage is that the substrate is only partially removed, while the substrate remains a heat dissipation effect.

Description

Technical Field

[0001] The utility model relates to a semiconductor component. Background Art

[0002] The integrated circuit (IC) industry has experienced rapid growth. Advances in semiconductor manufacturing technology have led to the development of several generations of ICs, each featuring smaller and more complex circuits than the previous generation. With the evolution of ICs, the density of functional circuits (i.e., the number of interconnected IC components per unit chip area) has generally increased, while geometry (i.e., the size and / or dimensions of IC features and / or the spacing between IC features) has decreased. Generally speaking, as IC features continue to shrink, scaling is limited only by the capabilities of the photolithography techniques used to define the IC features.

[0003] As feature sizes continue to decrease, some IC features, such as source / drain metal contacts and power grids, can be formed on the backside of the semiconductor substrate. This allows for better control of pattern spacing while optimizing power consumption. Forming backside IC features involves thinning the substrate from the backside. In some cases, the thinned substrate is replaced with a dielectric layer to reduce parasitic capacitance and unwanted coupling in the device. However, replacing the thinned substrate is not an easy step. According to current practice, the thinned substrate is completely removed by a dry etching process. This is quite difficult to control due to the etching depth loading effect and the possibility of damage to the gate dielectric layer or shift in the starting voltage.

[0004] Therefore, although the existing approach of replacing the semiconductor substrate with a dielectric layer has generally met the objectives, it is still not completely satisfactory in all aspects. Utility Model Content

[0005] One aspect of the present invention relates to a semiconductor component. The semiconductor component includes: a semiconductor substrate and a transistor formed on the semiconductor substrate. The transistor includes a first source / drain feature, a second source / drain feature, a channel region extending between the first source / drain feature and the second source / drain feature, and a gate stack contacting the channel region. The semiconductor component includes: a first source / drain contact structure landing on the top surface of the first source / drain feature; a second source / drain contact structure landing on the top surface of the second source / drain feature; and a dielectric plug penetrating the semiconductor substrate and landing on the bottom surface of the first source / drain feature. The width of the dielectric plug is equal to or less than the width of the first source / drain feature.

[0006] Another aspect of the present invention relates to a semiconductor device. The semiconductor device includes a semiconductor substrate and transistors formed above the semiconductor substrate. Each transistor includes a channel region extending between source / drain features and a gate stack contacting the channel region. The semiconductor device also includes a source / drain contact structure landing on the top surface of the source / drain features; and a dielectric plug extending through the semiconductor substrate and landing on the bottom surface of the source / drain features.

[0007] Yet another aspect of the present invention relates to a method for forming a semiconductor device. The method includes receiving a workpiece having transistors formed above a substrate, wherein each transistor includes a channel region extending between source / drain features and a gate stack contacting the channel region; thinning the substrate from a backside of the workpiece; and forming dielectric plugs extending through the thinned substrate and landing on first and second source / drain features of the transistors, wherein the dielectric plugs are spaced apart from each other by the thinned substrate.

[0008] The present invention relates to a semiconductor component with a backside dielectric plug. In order to reduce parasitic capacitance and leakage current, the semiconductor substrate can be replaced with a dielectric material in the backside process. However, the main replacement of the semiconductor substrate may cause damage to the gate dielectric layer from the backside. Specifically, there is a risk of over-etching the area directly below the bottom surface of the gate stack, thereby causing a shift in the starting voltage. In addition, the complete replacement of the semiconductor substrate also causes a decrease in the heat dissipation performance of the component. To solve these problems, the present invention proposes a backside process for forming a backside dielectric plug that passes through the semiconductor substrate and is aligned with the back side of the source / drain features in the vertical direction. The backside dielectric plug is spaced apart from the bottom surface of the gate stack to avoid damage to the gate dielectric layer. Since the backside dielectric plug is spaced apart from the gate stack, an additional epitaxial structure etching process may be applied to etch into the source / drain features. This additional epitaxial etch process allows the dielectric plug to extend deeper into the source / drain features from the backside, thereby maintaining the parasitic capacitance reduction effect while only partially removing the substrate. Furthermore, the partial removal of the substrate also allows the remaining semiconductor substrate to provide better heat dissipation. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The aspects of the present invention are best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or decreased for clarity. Furthermore, it should be noted that the drawings depict only representative embodiments of the present invention and, as such, should not be construed as limiting the scope of the present invention. The present invention is equally applicable to other embodiments. Furthermore, the drawings may implicitly depict features not explicitly described herein.

[0010] Figure 1 A schematic plan view of a semiconductor device according to an embodiment of the present invention is shown.

[0011] Figures 2 to 4 According to different embodiments of the present invention, a semiconductor device is shown along the Figure 1 Schematic cross-sectional view of line A-A'.

[0012] Figure 5 The flowchart is a partial method or a complete method for forming a semiconductor device having one or more backside dielectric plugs according to one embodiment of the present invention.

[0013] Figures 6 to 16 According to an embodiment of the present invention, a semiconductor device is shown in FIG. Figure 5 The intermediate manufacturing stage of the process Figure 1 Schematic cross-sectional view of line A-A'.

[0014] Figure 17 The flowchart is a partial method or a complete method for forming a semiconductor device having one or more backside dielectric plugs according to another embodiment of the present invention.

[0015] Figures 18 to 28 According to an embodiment of the present invention, a semiconductor device is shown in FIG. Figure 17 The intermediate manufacturing stage of the process Figure 1 Schematic cross-sectional view of line A-A'.

[0016] Figure 29 The flowchart is a partial method or a complete method for forming a semiconductor component with an extended backside dielectric plug according to another embodiment of the present invention.

[0017] Figures 30 to 38 According to an embodiment of the present invention, a semiconductor device is shown in FIG. Figure 29 The intermediate manufacturing stage of the process Figure 1 Schematic cross-sectional view of line A-A'. DETAILED DESCRIPTION

[0018] The following disclosure provides many different embodiments or examples for implementing the different features of the provided target. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature on or on a second feature may include embodiments in which the first feature and the second feature are formed to be in direct contact, and may also include embodiments in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature are not in direct contact. In addition, the present invention may reuse reference numbers and / or letters in various examples. Such repetition is for the purpose of brevity and clarity and does not itself indicate a relationship between the various embodiments and / or configurations discussed.

[0019] Furthermore, for ease of description, spatially relative terms, such as "beneath," "below," "lower," "above," and "upper," may be used herein to describe the relationship of one component or feature to another component or feature as illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0020] Furthermore, when describing a value or a range of values ​​using "about," "approximately," or similar terms, a reasonable range of values ​​that includes the value (e.g., a range of + / - 10% of the value) or other values ​​that are understood by a person of ordinary skill in the art is encompassed. For example, the term "approximately 5 nm" may encompass a size range from 4.5 nm to 5.5 nm. In addition, when comparing the size / dimensions of two features, the terms "substantially equal," "essentially the same," "similar in size," or the like mean that the difference in size / dimensions of the two features is within a range of + / - 10% (or other ranges that are understood by a person of ordinary skill in the art). Furthermore, disclosing the dimensions of different features may implicitly disclose the size ratios between such features.

[0021] The present invention relates to a semiconductor component with a backside dielectric plug. In order to reduce parasitic capacitance and leakage current, the semiconductor substrate can be replaced with a dielectric material in the backside process. However, the main replacement of the semiconductor substrate may cause damage to the gate dielectric layer from the backside. Specifically, there is a risk of over-etching the area directly below the bottom surface of the gate stack, thereby causing a shift in the starting voltage. In addition, the complete replacement of the semiconductor substrate also causes a decrease in the heat dissipation performance of the component. To solve these problems, the present invention proposes a backside process for forming a backside dielectric plug that passes through the semiconductor substrate and is aligned with the back side of the source / drain features in the vertical direction. The backside dielectric plug is spaced apart from the bottom surface of the gate stack to avoid damage to the gate dielectric layer. Since the backside dielectric plug is spaced apart from the gate stack, an additional epitaxial structure etching process may be applied to etch into the source / drain features. This additional epitaxial etch process allows the dielectric plug to extend deeper into the source / drain features from the backside, thereby maintaining the parasitic capacitance reduction effect while only partially removing the substrate. Furthermore, the partial removal of the substrate also allows the remaining semiconductor substrate to provide better heat dissipation.

[0022] To illustrate various aspects of the present invention, the following describes a method for forming a semiconductor component. The embodiments shown in the present invention are implemented as gate-all-around (GAA) field effect transistors (FETs), but the present invention is not limited thereto. A GAA FET refers to a transistor having a gate stack (including a gate electrode and a gate dielectric layer) surrounding the transistor channel, such as a gate-all-around nanowire or nanosheet MOSFET component stacked in a vertical direction. A person with ordinary knowledge in the art should understand that the present invention can be easily used as a basis to design or modify other structures to achieve the purposes of the embodiments disclosed herein and / or achieve the same advantageous effects.

[0023] Figure 1A schematic plan view of a semiconductor device 100 is shown according to one embodiment of the present invention. The semiconductor device 100 has a corresponding semiconductor structure, and the terms "device" and "structure" are used interchangeably herein. The semiconductor device 100 can be part of an integrated circuit (IC) chip, a system on chip (SoC), or a portion thereof, and can include various passive and active microelectronic components, such as resistors, capacitors, inductors, diodes, p-type FETs (PFETs), n-type FETs (NFETs), fin FETs (FinFETs), nanosheet FETs, nanowire FETs, other types of multi-gate FETs, metal-oxide-semiconductor FETs (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused metal-oxide-semiconductor (LDMOS) transistors, high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof. In some embodiments, the component is located in a non-volatile memory, such as non-volatile random access memory (NVRAM), flash memory, electrically erasable programmable read only memory (EEPROM), electrically erasable programmable read only memory (EPROM), other suitable memory types, or combinations thereof.

[0024] In the illustrated embodiment, the semiconductor component 100 includes a fin active region 104 extending along a longitudinal axis in a direction X and a gate structure 108 extending along a longitudinal axis in a direction Y above the fin active region 104. The fin active regions 104 are separated from each other by an isolation structure 106. The isolation structure 106 provides isolation between adjacent fin active regions 104 and may be a shallow trench isolation (STI) layer. The isolation structure 106 may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, a combination thereof, and / or other suitable materials. In the present embodiment, the isolation structure 106 is disposed above the semiconductor substrate 102 (not shown). Figure 1 In, for example, Figures 2 to 4 The fin-type active region 104 protrudes from the semiconductor substrate 102 and is higher than the isolation structure 106. Each fin-type active region 104 includes a source / drain region SDR located at two adjacent ends of the channel region CR. The channel region CR is defined by the portion of the fin-type active region 104 located directly below the gate structure 108. Figure 1 , line AA′ cuts through one of the fin-type active regions 104 along direction X and crosses the gate structures 108 . Line AA′ is selected to illustrate a cross-sectional view of various features formed along the fin-type active region 104 .

[0025] Figure 2 According to an embodiment of the present invention, a semiconductor device 100 is shown. Figure 1 A-A' line cross-sectional view. Figure 2As shown, a fin-shaped active region 104 protruding from a semiconductor substrate 102 is disposed above the semiconductor substrate 102. The semiconductor substrate 102 may be a silicon substrate or a substrate comprising other semiconductor materials. The other semiconductor materials may be, for example, germanium, silicon carbide, silicon germanium, or diamond. The source / drain region SDR of the fin-shaped active region 104 includes epitaxial source / drain (S / D) features 104b, and the channel region CR of the fin-shaped active region 104 includes one or more transistor channels 104a. The epitaxial S / D features 104b may be doped with n-type dopants or p-type dopants. In some embodiments, for n-type transistors, the epitaxial S / D features 104b include silicon and may be doped with carbon, phosphorus, arsenic, other n-type dopants, or a combination thereof. For example, the epitaxial S / D features 104b of an n-type transistor may be formed as Si:C epitaxial S / D features, Si:P epitaxial S / D features, or Si:C:P epitaxial S / D features. In some embodiments, for a p-type transistor, the epitaxial S / D feature 104b comprises silicon germanium or germanium and may be doped with boron, other p-type dopants, or a combination thereof. For example, the epitaxial S / D feature 104b for a p-type transistor may be formed as a Si:Ge:B epitaxial S / D feature. The epitaxial S / D feature 104b may include different portions L0, L1, and L2 having different doping concentrations. In one embodiment, the doping concentration of portion L2 is higher than the doping concentration of portion L1, and the doping concentration of portion L1 is higher than the doping concentration of portion L0. In other words, the portion of the epitaxial S / D feature 104b closer to the transistor channel 104a has a lower doping concentration than the portion of the epitaxial S / D feature 104b farther away from the transistor channel 104a.

[0026] A gate structure 108 (also known as a gate stack) is disposed above one or more transistor channels 104a within the channel region CR. Each gate structure 108 may include an interface layer 108a (e.g., a silicon oxide layer), a gate dielectric layer 108b above the interface layer 108a, and a gate electrode 108c above the gate dielectric layer 108b. The gate dielectric layer 108b may include a high-k dielectric material, such as a material having a greater k than that of silicon oxide (which has a k of approximately 3.9). The gate dielectric layer 108b may include HfO, LaO, ZrO, AlO, TiO, or TaO. The gate electrode 108c may include a suitable conductive material, such as Al, W, Co, TiAl, TiN, or other metal gate materials. As shown, the interface layer 108a, the gate dielectric layer 108b, and the gate electrode 108c may each surround the multiple transistor channels 104a within the channel region CR. The channel region CR may further include spacer features, such as a gate spacer 109 and an inner spacer 111. The gate spacer 109 may line the sidewalls of the gate structure 108 above the uppermost transistor channel 104a, while the inner spacer 111 may be vertically disposed between the transistor channel 104a and laterally disposed between the gate structure 108 and the epitaxial S / D feature 104b. The gate spacer 109 and the inner spacer 111 may include silicon oxide, silicon nitride, silicon oxycarbonitride, silicon carbonitride, metal nitride, or a suitable dielectric material. In one embodiment, the gate spacer 109 and the inner spacer 111 include different materials to provide etch selectivity relative to each other.

[0027] The fin-shaped active region 104 and the gate structure 108 define one or more transistors, each of which includes a first epitaxial S / D feature 104b, a second epitaxial S / D feature 104b, a channel region CR extending between the first and second epitaxial S / D features 104b, and a gate structure 108 contacting and disposed above the channel region CR. Additional structures are formed on the one or more transistors, such as a front S / D contact structure 112 electrically connected to the epitaxial S / D feature 104b. The front S / D contact structure 112 may include titanium, ruthenium, copper, nickel, cobalt, tungsten, tantalum, or molybdenum. In one embodiment, a front metal silicide feature 110a is first formed on the epitaxial S / D feature 104b, followed by a front S / D contact structure 112 formed on the front metal silicide feature 110a. The front metal silicide feature 110a may include titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel-platinum silicide (NiPtSi), nickel-platinum-germanium silicide (NiPtGeSi), nickel-germanium silicide (NiGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi), or other suitable compounds. Various dielectric layers may surround the front S / D contact structure 112 and line the surface of the front S / D contact structure 112. As shown, an etch stop layer and / or barrier layer 113 may be disposed on the sidewalls of the front S / D contact structure 112 and on the top surfaces of the gate structure 108 and the gate spacer 109. An interlayer dielectric (ILD) layer 115 may also be provided over the gate structure 108 and between the front-side S / D contact structures 112. In this embodiment, the top surface of the front-side S / D contact structures 112 is disposed above the top surface of the gate structure 108. Furthermore, an etch stop layer 117 may be provided over the front-side S / D contact structures 112 and the ILD layer 115. The etch stop layers 113 and 117 may comprise silicon nitride, and the ILD layer 115 may comprise a different material (e.g., silicon oxide) to provide an etch selectivity for the ILD layer 115 relative to the etch stop layers 113 and 117.

[0028] The various features described above are formed on the front side of semiconductor device 100 and located above semiconductor substrate 102. Additional IC features may be formed on the front side of semiconductor device 100. For example, interconnect structure 120 is formed above front side S / D structure 112. Interconnect structure 120 electrically couples various components (e.g., p-type transistors and / or n-type GAA transistors, other transistors, resistors, capacitors, and / or inductors) and / or various elements (e.g., gate structures and / or epitaxial S / D features of p-type and / or n-type transistors) of semiconductor device 100 so that these components and / or elements can operate according to the design requirements of semiconductor device 100. Interconnect structure 120 includes a combination of dielectric layers and conductive layers (e.g., metal layers), wherein the conductive layers are configured to form various interconnect features. The conductive layers are configured to form vertical interconnect features (e.g., vias) and / or horizontal interconnect features (e.g., conductive lines). Typically, vertical interconnect features connect horizontal interconnect features in different layers (e.g., at different planes) of the interconnect layer. During operation, interconnect structure 120 is configured to route signals between components and / or between components of semiconductor device 100 and / or to transmit signals (e.g., clock signals, voltage signals, and / or ground signals) to semiconductor device 100 and / or components of semiconductor device 100.

[0029] Still refer to Figure 2Backside dielectric plugs 150 are disposed directly below and land on the bottom surface of the epitaxial S / D features 104b. As will be described below, these backside dielectric plugs 150 are formed from the back side of the semiconductor device 100. As shown, the backside dielectric plugs 150 are vertically aligned with the epitaxial S / D features 104b and the frontside S / D contact structure 112. The backside dielectric plugs 150 may extend horizontally between the gate structure 108 (or channel region CR), and their width in the direction X is equal to or less than the width of the epitaxial S / D features 104b in the direction X. In one embodiment, the backside dielectric plugs 150 and the frontside S / D contact structure 112 have substantially the same width. The backside dielectric plugs 150 extend through the semiconductor substrate 102 and are surrounded by the semiconductor substrate 102. The top surface of the backside dielectric plug 150 is located above the bottom surface of the gate structure 108. The backside dielectric plug 150 may include silicon oxide, silicon nitride, a low-k dielectric material, or a combination thereof. In the illustrated embodiment, the backside dielectric plug 150 includes a dielectric filler layer 151 and a barrier layer 152 surrounding the dielectric filler layer 151. The barrier layer 152 can reduce oxidation defects between the semiconductor substrate 102 and the dielectric filler layer 151. The barrier layer 152 can include silicon nitride, and the dielectric filler layer 151 can include silicon oxide or a low-k dielectric material. The barrier layer 152 directly contacts the bottom surface of the epitaxial S / D feature 104b. Although the barrier layer 152 can be part of the backside dielectric plug 150, the present invention is not limited thereto. For example, in some embodiments, the backside dielectric plug 150 does not include the barrier layer 152, but only includes a dielectric filler layer 151, which includes silicon nitride, silicon oxide, or a low-k dielectric material. In other embodiments, the backside dielectric plug 150 may include one or more air gaps 153 to further reduce parasitic capacitance.

[0030] Figure 3 According to another embodiment of the present invention, the semiconductor device 100 is shown along Figure 1 Schematic cross-sectional view of line A-A'. Figure 3 Similar to Figure 2 For the sake of brevity, similar features shared by both are not described in detail. Figure 3The backside S / D contact structure 162 differs from the backside dielectric plug 150 in that it further includes a backside S / D contact structure 162 replacing one of the backside dielectric plugs 150. As will be described below, the backside S / D contact structure 162 is formed on the back side of the semiconductor device 100. As shown, the backside S / D contact structure 162 is vertically aligned with the epitaxial S / D features 104b and the frontside S / D contact structure 112. The backside S / D contact structure 162 extends laterally between the gate structures 108 (or between the channel regions CR), and its width in the direction X is equal to or less than the width of the epitaxial S / D features 104b in the direction X. In one embodiment, the backside S / D contact structure 162 and the frontside S / D contact structure 112 have substantially the same width. The backside S / D contact structure 162 extends through the semiconductor substrate 102 and is surrounded by the semiconductor substrate 102. The top surface of the backside S / D contact structure 162 is located above the bottom surface of the gate structure 108. Backside S / D contact structure 162 is electrically connected to one of the epitaxial S / D features 104 b. Similar to frontside S / D contact structure 112, backside S / D contact structure 162 may comprise titanium, ruthenium, copper, nickel, cobalt, tungsten, tantalum, or molybdenum. In one embodiment, backside metal silicide feature 110 b is first formed below epitaxial S / D feature 104 b, followed by backside S / D contact structure 162 formed below backside metal silicide feature 110 b. The backside metal silicide feature 110b may include titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel-platinum silicide (NiPtSi), nickel-platinum-germanium silicide (NiPtGeSi), nickel-germanium silicide (NiGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi), or other suitable compounds. In the illustrated embodiment, the backside S / D contact structure 162 is surrounded by a barrier layer 163. The barrier layer 163 reduces oxidation and diffusion defects between the semiconductor substrate 102 and the backside S / D contact structure 162. The barrier layer 163 may include silicon nitride. The backside S / D contact structure 162 directly contacts the bottom surface of the epitaxial S / D feature 104b (or the backside metal silicide feature 110b). Described in another way, the backside S / D contact structure 162 and the barrier layer 163 may be collectively referred to as an S / D contact structure, which includes a metal fill structure and a barrier layer surrounding the metal fill structure (analogous to the backside dielectric plug 150 having a dielectric fill layer 151 and a barrier layer 152 surrounding the dielectric fill layer 151).

[0031] Figure 4 According to another embodiment of the present invention, the semiconductor device 100 is shown along Figure 1 Schematic cross-sectional view of line A-A'. Figure 4 Similar to Figure 3 For the sake of brevity, similar features shared by both are not described in detail. Figure 4 The difference is Figure 3 The backside dielectric plugs 150 in the semiconductor device 100 are connected to each other to form an extended dielectric plug 155. As will be described below, the extended dielectric plug 155 is formed from the backside of the semiconductor device 100 and is a variation of the backside dielectric plug 150. As shown, the extended dielectric plug 155 includes a plurality of through-portions 155a vertically aligned with the epitaxial S / D features 104b and the frontside S / D contact structure 112. The through-portions 155a extend laterally between the gate structures 108 (or between the channel regions CR), and their width in the direction X is equal to or less than the width of the epitaxial S / D features 104b in the direction X. The extended dielectric plug 155 further includes a main portion 155b, wherein the through-portions 155a protrude from the main portion 155b. The main portion 155b laterally extends across the width of the plurality of epitaxial S / D features 104b and / or the plurality of channel regions CR. The top surface of the through portion 155a is located above the bottom surface of each gate structure 108, and the top surface of the main portion 155b is located below the bottom surface of each gate structure 108. The extended dielectric plug 155 may include silicon oxide, silicon nitride, a low-k dielectric material, or a combination thereof. In the illustrated embodiment, the extended dielectric plug 155 includes a dielectric fill layer 151 and a barrier layer 152 surrounding the dielectric fill layer 151. The barrier layer 152 can reduce oxidation defects between the semiconductor substrate 102 and the dielectric fill layer 151. The barrier layer 152 can include silicon nitride, and the dielectric fill layer 151 can include silicon oxide or a low-k dielectric material. The barrier layer 152 directly contacts the bottom surface of the epitaxial S / D feature 104b. Although the barrier layer 152 can be part of the extended dielectric plug 155, the present invention is not limited thereto. For example, in some embodiments, the extended dielectric plug 155 does not include the barrier layer 152 but only includes a dielectric filler layer 151, wherein the dielectric filler layer 151 includes silicon nitride, silicon oxide, or a low-k dielectric material. In yet other embodiments, the extended dielectric plug 155 may include one or more air gaps 153 to further reduce parasitic capacitance.

[0032] Figure 5 FIG. 5 is a flow chart of a method 500 for forming a semiconductor device 100 having one or more backside dielectric plugs 150 according to an embodiment of the present invention. Figures 6 to 16 To illustrate method 500. Figures 6 to 16 The semiconductor device 100 is shown at an intermediate manufacturing stage according to the method 500. Figure 1 Schematic cross-sectional view of line A-A'.

[0033] Please refer to Figure 6At operation 502 of method 500 , a workpiece having a fin-shaped active region 104 formed above a semiconductor substrate 102 and a plurality of gate structures 108 formed above a channel region CR of the fin-shaped active region 104 is received. The fin-shaped active region 104 and the gate structures 108 form one or more transistors above the semiconductor substrate 102 , each including a first epitaxial S / D feature 104 b ; a second epitaxial S / D feature 104 b ; a channel region CR having one or more transistor channels 104 a extending between the first epitaxial S / D feature 104 b and the second epitaxial S / D feature 104 b ; and a gate structure 108 (or gate stack) contacting the channel region CR. For the sake of brevity, descriptions of these related features have been provided above and are not repeated here. It should be understood that at operation 502, method 500 may further include receiving (or performing front-side processing to form) additional front-side IC features, such as a front-side S / D contact structure 112 landing on the front-side surface of the epitaxial S / D feature 104b and one or more interconnect structures 120 above the front-side S / D contact structure 112.

[0034] Please refer to Figure 7 At operation 504 of method 500, the semiconductor substrate 102 is thinned from its backside. Operation 504 may be performed before or after the workpiece is flipped over for further backside processing. In the present embodiment, operation 504 includes flipping the workpiece over and placing the workpiece on a carrier that provides structural support. Due to the flipping, the vertically upward axis is now designated as direction -Z. Next, operation 504 thins the semiconductor substrate 102 from its backside by a suitable process, such as chemical mechanical polishing (CMP). The workpiece may be placed on the carrier by any suitable process, such as direct bonding, hybrid bonding, the use of an adhesive, or other bonding process. The semiconductor substrate 102 may be thinned by a mechanical polishing process and / or a chemical thinning process. In the present embodiment, the semiconductor substrate 102 is thinned to a thickness t1 in the range of approximately 10 nm to 50 nm.

[0035] Please refer to Figure 8At operation 506 of method 500, a first hard mask layer is deposited on the backside of the semiconductor substrate 102 using any suitable deposition technique, such as chemical vapor deposition (CVD). In this embodiment, the first hard mask layer includes a silicon nitride film 413 and a silicon oxide film 415. The silicon nitride film 413 is first deposited on the backside surface of the semiconductor substrate 102, followed by the silicon oxide film 415 being deposited on the silicon nitride film 413. In one embodiment, the thickness of the silicon nitride film 413 is in a range from approximately 5 nm to approximately 15 nm, and the thickness of the silicon oxide film 415 is in a range from approximately 15 nm to approximately 45 nm. It should be understood that in other embodiments, the first hard mask layer may include only the silicon nitride film 413 or the silicon oxide film 415.

[0036] Please refer to Figure 9 At operation 508 of method 500, a first trench 419 is formed through the first hard mask layer (e.g., comprising a silicon nitride film 413 and a silicon oxide film 415) and the semiconductor substrate 102 to expose the first epitaxial S / D feature 104b of the transistor. Operation 508 may include patterning the first hard mask layer via a photolithography process, thereby forming a patterned hard mask that exposes the portion of the semiconductor substrate 102 to be etched. Next, operation 508 etches through the exposed portion of the semiconductor substrate 102 using the patterned mask as an etch mask. The etching of the semiconductor substrate 102 may include dry etching, wet etching, reactive ion etching, or other suitable etching techniques. It should be understood that the etching may include intentional overetching into the fin active region 104. Specifically, the first epitaxial S / D feature 104b may be partially recessed (etched) to allow the subsequently formed dielectric plug to further reduce parasitic capacitance. In one embodiment, the depth to which the first epitaxial S / D feature 104b is recessed (etched) may be a distance d1 in the range of about 5nm to about 15nm. In other words, the vertical distance between the exposed concave surface of the first epitaxial S / D feature 104b and the bottom surface of the gate structure 108 is in the range of about 5nm to about 15nm. The range of distance d1 is not meaningless. If the distance d1 is less than 5nm, the effect of reducing parasitic capacitance may be negligible. If the distance d1 is greater than 15nm, there is a risk of adversely affecting the channel operation of the bottommost transistor channel 104a. Still referring to Figure 9 Each first trench 419 may have a width d2 in the direction X that is in the range of approximately 5 nm to approximately 20 nm. The range of width d2 is not trivial. If the distance d2 is less than 5 nm, the effect of reducing parasitic capacitance may be negligible. If the width d2 is greater than 20 nm, there is a risk of overetching and damage to the gate structure 108 (particularly the gate dielectric layer 108 b).

[0037] Please refer to Figure 10 At operation 510 of method 500, a dielectric material 416 is deposited in the first trench 419 by any suitable deposition process. The dielectric material 416 may include silicon oxide, silicon nitride, a low-k dielectric material, or a combination thereof. Operation 510 may include first depositing a conformal barrier film in the first trench 419 and then depositing a dielectric fill material on the conformal barrier film. As a result of this process, a dielectric fill material is formed. Figure 2 、 Figure 3 . Alternatively, the dielectric filling material is deposited only in the first trench 419. The deposition of the dielectric material 416 can be controlled to form an air gap 153 ( Figure 10 Not shown, but shown in Figure 2 and Figure 3 For example, the deposition rate can be increased to intentionally form pores in the first trench 419. In another embodiment, a porous dielectric material is deposited in the first trench 419 to further increase the amount of air trapped in the first trench 419. Due to its low dielectric constant, the air gap 153 can result in lower parasitic capacitance.

[0038] Please refer to Figure 11 At operation 512 of method 500, the workpiece is planarized by a suitable process (such as dielectric CMP) to form a backside dielectric plug 150. The backside dielectric plug 150 corresponds to the reference Figure 2 、 Figure 3 For the sake of brevity, the description of the backside dielectric plug 150 is omitted here. In this embodiment, the workpiece is planarized so that the silicon oxide film 415 is removed and the top surface of the backside dielectric plug 150 is coplanar with the top surface of the silicon nitride film 413. In other embodiments, the workpiece may be planarized so that the silicon nitride film 413 is also removed and the top surface of the backside dielectric plug 150 is coplanar with the top surface of the semiconductor substrate 102.

[0039] Please refer to Figure 12 At operation 514 of method 500, a second hard mask layer is deposited on the backside dielectric plug 150 by any suitable deposition technique, such as CVD. The second hard mask layer may include another silicon nitride film (not shown) and another silicon oxide film 417. In this embodiment, the second hard mask layer includes the silicon oxide film 417 and the silicon nitride film 413. In an embodiment where the silicon nitride film 413 is removed, the second hard mask layer may include another silicon nitride film (not shown) and the silicon oxide film 417 over the other silicon nitride film. In one embodiment, the thickness of the silicon oxide film 417 is in a range from about 15 nm to about 45 nm.

[0040] Please refer to Figure 13 At operation 516 of method 500, a second trench 429 is formed through the second hard mask layer (e.g., including the silicon nitride film 413 and the silicon oxide film 417) and the semiconductor substrate 102 to expose the second epitaxial S / D feature 104b of the transistor. Operation 516 may include patterning the second hard mask layer through a photolithography process, thereby forming a patterned hard mask that exposes the portion of the semiconductor substrate 102 to be etched. Subsequently, operation 516 etches through the exposed portion of the semiconductor substrate 102 using the patterned hard mask as an etch mask. The etching of the semiconductor substrate 102 may include dry etching, wet etching, reactive ion etching, or other suitable etching techniques. In this embodiment, the second trench 429 may be similar in depth and width to the first trench 419.

[0041] Please refer to Figures 14 to 16 At operations 518 and 520 of the method 500, a backside S / D contact structure 162 is formed in the second trench 429. Specifically, at operation 518 of the method 500, a conductive material is deposited in the second trench 429. Subsequently, at operation 520, the workpiece is planarized to form the backside S / D contact structure 162. Figure 14 As shown, operation 518 includes first depositing a barrier layer 163 in the second trench 429 by a suitable deposition process, and then etching a horizontal portion of the barrier layer 163 to form a bottom opening that exposes the surface of the second epitaxial S / D feature 104b. Figure 15 As shown, operation 518 includes depositing a conductive material in the second trench 429 over the exposed surface of the second epitaxial S / D feature 104b to form a backside S / D contact structure 162. In one embodiment, a metal silicide feature 110b is first deposited over the exposed surface of the second S / D feature 104b, and then a metal filling material is deposited over the metal silicide feature 110b. Figure 16 As shown, the workpiece is planarized by a suitable process such as CMP to adjust the backside S / D contact structure 162. In this embodiment, the workpiece is planarized to remove the silicon oxide film 417 and make the top surfaces of the backside dielectric plug 150, the silicon nitride film 413, and the backside S / D contact structure 162 coplanar. In another embodiment, the workpiece is planarized to remove the silicon nitride film 413 as well and make the dielectric plug 150, the backside S / D contact structure 162 coplanar with the top surface of the semiconductor substrate 102. Figure 3The metal silicide feature 110b, backside S / D contact structure 162, and barrier layer 163 are described and are not further described here for the sake of brevity. As shown, the backside of the epitaxial S / D feature 104b can directly contact the backside dielectric plug 150 or the backside S / D contact structure 162, and the backside dielectric plug 150 and / or the backside S / D contact structure 162 are separated from each other by portions of the semiconductor substrate 102. Method 500 may be performed with further operations to complete the fabrication of semiconductor device 100. Additional operations may be provided before, during, or after method 500, and in additional embodiments, the order of some operations of method 500 may be changed, some operations of method 500 may be replaced, or some operations of method 500 may be deleted.

[0042] Figure 17 FIG. 6 is a flow chart of a method 600 for forming a semiconductor device 100 having one or more backside dielectric plugs 150 according to another embodiment of the present invention. Figures 18 to 28 To illustrate method 600. Figures 18 to 28 The semiconductor device 100 is shown at an intermediate manufacturing stage according to the method 600. Figure 1 , a cross-sectional view taken along line AA' of FIG. Method 600 is similar to method 500 , except that at operation 616 , second trench 429 is formed through one or more backside dielectric plugs 150 , rather than through semiconductor substrate 102 (as in operation 516 of method 500 ). Given that method 600 is similar to method 500 , only the differences between the two are described below.

[0043] Please refer to Figures 18 to 24 Operations 602, 604, 606, 608, 610, 612, and 614 of method 600 are similar to operations 502, 504, 506, 508, 510, 512, and 514 of method 500, respectively. The difference of method 600 is that backside dielectric plugs 150 are formed corresponding to both the first epitaxial S / D feature 104b (i.e., the epitaxial S / D feature that does not contact the backside S / D contact structure 162) and the second epitaxial S / D feature 104b (i.e., the epitaxial S / D feature that contacts the backside S / D contact structure 162). In other words, each epitaxial S / D feature 104b in the fin active region 104 is completely patterned and a backside dielectric plug 150 is formed. Next, at operation 616 (refer to Figure 25), method 600 includes forming a second trench 429 through a subset of the second hard mask layer and the backside dielectric plug 150 to expose the second epitaxial S / D feature 104b of the transistor. It should be noted that the advantage of method 600 is at operation 616: a low-resolution lithography process can be used to form the second trench 429, thereby saving manufacturing costs. This is attributable to the fact that operation 616 involves etching through the backside dielectric plug 150, rather than etching through the semiconductor substrate 102. In this regard, the semiconductor substrate 102 has an etch selectivity relative to the backside dielectric plug 150, so that the second trench 429 can be formed by self-aligned etching. In other words, the shape of the second trench 429 will conform to the shape of the previously formed backside dielectric plug 150. Therefore, this patterning operation will not be subject to any slight overlay error. As an example, Figure 25 The patterned openings may have a larger margin in the direction X. Thus, the openings formed in the hard mask layer (e.g., silicon oxide film 417) are larger than the openings formed by etching through the backside dielectric plug 150. In one embodiment, the larger openings are intentionally designed to form a damascene backside powerrail contact structure. Figures 26 to 28 , similar to operations 518 and 520, the method 600 forms the backside S / D contact structure 162 at operations 618 and 620. In one embodiment, the backside S / D contact structure 162 is formed to have the following characteristics: Figure 27 In this embodiment, the planarization process in operation 620 may be omitted.

[0044] Figure 29 FIG. 7 is a flow chart of a method 700 for forming a semiconductor component 100 having an extended backside dielectric plug 155. Figures 30 to 38 To illustrate method 700. Figures 30 to 38 The semiconductor device 100 is shown at an intermediate manufacturing stage according to the method 700. Figure 1 Schematic cross-sectional view of line AA' of FIG. Method 700 is similar to method 500 or method 600, and only the differences are described below. One difference is that method 700 includes a dual-damascene process at multiple operations of patterning and etching semiconductor substrate 102. The dual-damascene process forms a trench having multiple portions extending into semiconductor substrate 102 at different depths.

[0045] Please refer to Figures 30 to 32, operations 702, 704, and 706 of method 700 are similar to operations 502, 504, and 506 of method 500, respectively. Next, at operation 708 (see Figure 33 ), method 700 includes forming a first trench 419 through a first hard mask layer (e.g., a silicon nitride film 413 and a silicon oxide film 415) and the semiconductor substrate 102. Operation 708 may include performing a lithography process to form a patterned photoresist layer above the first hard mask layer, and etching the first hard mask layer to transfer the pattern from the patterned photoresist layer to the first hard mask layer. Thereafter, at operation 708, the exposed portion of the semiconductor substrate 102 is etched using the patterned hard mask as an etch mask. Operation 708 may be the first step of a dual damascene process. The first trench 419 extends into the semiconductor substrate 102 at a first depth z1 (the extension distance downward from the top surface of the semiconductor substrate 102). The depth z1 is less than the thickness t1 of the semiconductor substrate 102. In one embodiment, the depth z1 is less than the thickness t1 by a difference of approximately 5 nm to approximately 15 nm. The first trench 419 is vertically aligned with the back side of the epitaxial S / D feature 104b, but does not expose the epitaxial S / D feature 104b. In other respects, the first trench 419 described herein is similar to Figure 21 A first trench 419 is shown.

[0046] Please refer to Figure 34 At operation 710 of method 700, a second hard mask layer is formed over the back side of semiconductor substrate 102. This may involve further patterning the silicon nitride film 413 and the silicon oxide film 415 to expose a single wide opening 619, or forming another patterned hard mask layer to expose a single wide opening 619. Figure 35 At operation 712 of method 700, a second trench 421 is formed through the single wide opening 619 using a second hard mask layer (e.g., a patterned silicon nitride film 413 and a patterned silicon oxide film 415) as an etch mask. Operation 712 may be the second step of the dual damascene process. The second trench 421 may extend into the semiconductor substrate 102 at a depth z1 (or another depth less than z1). Forming the second trench 421 may cause the first trench 419 to extend through the semiconductor substrate 102 at a deeper depth z2. In this operation, the first trench 419 exposes the first S / D feature 104b of the transistor. The second depth z2 is greater than the thickness t1, for example, by a difference of about 5 nm to about 15 nm. In some embodiments, the difference between the depth z2 and the depth z1 is about 15 nm to about 30 nm.

[0047] Please refer to Figure 36At operation 714 of method 700, a dielectric material 416 is deposited in the first trench 419 and the second trench 421 by any suitable deposition process. As described above, the dielectric material 416 may include silicon oxide, silicon nitride, a low-k dielectric material, or a combination thereof. Operation 714 may include first depositing a conformal barrier film in the first trench 419 and the second trench 421, and then depositing a dielectric fill material over the conformal barrier film. As a result, a dielectric fill material is formed. Figure 4 The barrier layer 152 and dielectric filling layer 151 are shown. Alternatively, the dielectric filling material is deposited only in the first trench 419 and the second trench 421. The deposition of the dielectric material 416 can be controlled to form an air gap 153 ( Figure 36 Not shown, but shown in Figure 4 For example, the deposition rate can be increased to intentionally form pores in the first trench 419 and the second trench 421. In another embodiment, a porous dielectric material is deposited in the first trench 419 and the second trench 421 to further increase the amount of air trapped in the first trench 419 and the second trench 421. Due to its low dielectric constant, the air gap 153 can result in lower parasitic capacitance.

[0048] Please refer to Figure 37 At operation 716 of method 700, the workpiece is planarized by a suitable process to form an extended dielectric plug 155 having a main portion 155b and a plurality of through portions 155a. The extended dielectric plug 155 corresponds to the reference Figure 4 The extended dielectric plug 155 is described, and for the sake of brevity, the description of the extended dielectric plug 155 will not be repeated here. In this embodiment, the workpiece is planarized to remove the silicon oxide film 415, and the top surface of the extended dielectric plug 155 is coplanar with the top surface of the silicon nitride film 413. In another embodiment, the workpiece is planarized to remove the silicon nitride film 413, and the top surface of the extended dielectric plug 155 is coplanar with the top surface of the semiconductor substrate 102.

[0049] Please refer to Figure 38At operation 718 of method 700, further operations may be performed, such as forming one or more backside S / D contact structures 162, to complete the fabrication of semiconductor device 100. Additional operations may be provided before, during, or after method 700, and in additional embodiments, the order of some operations of method 700 may be changed, some operations of method 700 may be replaced, or some operations of method 700 may be deleted. It should be noted that although method 700 includes a more complex process, an advantage of method 700 is that it provides a superior reduction in parasitic capacitance without risking damage to the gate dielectric layer. This can be attributed to the fact that a larger portion of semiconductor substrate 102 is replaced by dielectric material, while the remaining portion of semiconductor substrate 102 can still provide heat dissipation.

[0050] Without limitation, the present invention provides advantages brought about by replacing the substrate material with a dielectric material. For example, one advantage comes from the dielectric plug formed from the back side of the substrate being aligned with the S / D feature in the vertical direction and offset from the gate structure. This avoids damage to the gate dielectric layer. Another exemplary advantage comes from additionally etching the S / D feature as an epitaxial structure when forming the dielectric plug. This further reduces parasitic capacitance. Yet another exemplary advantage comes from only partially removing the substrate, so that the retained portion of the substrate provides a heat dissipation effect. Yet another exemplary advantage comes from forming an extended dielectric plug, which includes a through portion aligned with the S / D feature in the vertical direction and a main portion connected to the through portion. Based on the inclusion of the main portion, the extended dielectric plug can further reduce parasitic capacitance.

[0051] One aspect of the present invention relates to a semiconductor component. The semiconductor component includes: a semiconductor substrate and a transistor formed on the semiconductor substrate. The transistor includes a first source / drain feature, a second source / drain feature, a channel region extending between the first source / drain feature and the second source / drain feature, and a gate stack contacting the channel region. The semiconductor component includes: a first source / drain contact structure landing on the top surface of the first source / drain feature; a second source / drain contact structure landing on the top surface of the second source / drain feature; and a dielectric plug penetrating the semiconductor substrate and landing on the bottom surface of the first source / drain feature. The width of the dielectric plug is equal to or less than the width of the first source / drain feature.

[0052] In one embodiment, the dielectric plug is a first dielectric plug, and the semiconductor device further includes: a second dielectric plug extending through the semiconductor substrate and landing on a bottom surface of the second source / drain feature, wherein the second dielectric plug is separated from the first dielectric plug by a portion of the semiconductor substrate.

[0053] In yet another embodiment, the first dielectric plug further includes a first dielectric filling layer and a first barrier layer surrounding the first dielectric filling layer, wherein the first dielectric filling layer comprises a first dielectric material, the first barrier layer comprises a second dielectric material different from the first dielectric material, and the first barrier layer directly contacts the bottom surface of the first source / drain feature. The second dielectric plug further includes a second dielectric filling layer and a second barrier layer surrounding the second dielectric filling layer, wherein the second dielectric filling layer comprises the first dielectric material, the second barrier layer comprises the second dielectric material, and the second barrier layer directly contacts the bottom surface of the second source / drain feature.

[0054] In one embodiment, the semiconductor device further includes a source / drain contact structure penetrating the semiconductor substrate and landing on a bottom surface of the second source / drain feature, wherein the source / drain contact structure is separated from the dielectric plug by a portion of the semiconductor substrate.

[0055] In yet another embodiment, the dielectric plug further includes a dielectric filling layer and a first barrier layer surrounding the dielectric filling layer, the dielectric filling layer comprising a first dielectric material, the first barrier layer comprising a second dielectric material different from the first dielectric material, and the first barrier layer directly contacts the bottom surface of the first source / drain feature. The source / drain contact structure further includes a conductive filling layer and a second barrier layer surrounding the conductive filling layer, the second barrier layer comprising a second dielectric material, and the conductive filling layer directly contacts the bottom surface of the second source / drain feature.

[0056] In yet another embodiment, the semiconductor substrate comprises silicon, the first dielectric material comprises silicon oxide, a low-k dielectric material, or a combination thereof, and the second dielectric material comprises silicon nitride. In another embodiment, the dielectric fill layer comprises an air gap.

[0057] In one embodiment, a top surface of the dielectric plug is located above a bottom surface of the gate stack. In another embodiment, a vertical distance between the top surface of the dielectric plug and the bottom surface of the gate stack is greater than 5 nm.

[0058] Another aspect of the present invention relates to a semiconductor device. The semiconductor device includes a semiconductor substrate and transistors formed above the semiconductor substrate. Each transistor includes a channel region extending between source / drain features and a gate stack contacting the channel region. The semiconductor device also includes a source / drain contact structure landing on the top surface of the source / drain features; and a dielectric plug extending through the semiconductor substrate and landing on the bottom surface of the source / drain features.

[0059] In one embodiment, one of the dielectric plugs is a first dielectric plug landed on the bottom surface of a first source / drain feature among the source / drain features, and the other of the dielectric plugs is a second dielectric plug landed on the bottom surface of a second source / drain feature among the source / drain features, and the first dielectric plug and the second dielectric plug are embedded in the semiconductor substrate and spaced apart from each other by the semiconductor substrate.

[0060] In one embodiment, each dielectric plug extends laterally between two adjacent portions of the channel region. In another embodiment, each dielectric plug has a lateral width in the range of about 5 nm to about 20 nm. In another embodiment, the lateral width of each dielectric plug is less than the lateral width of the source / drain features.

[0061] In one embodiment, one of the dielectric plugs has a main portion and multiple through-portions protruding from the main portion. The main portion extends into the semiconductor substrate at a first depth, and the multiple through-portions penetrate the semiconductor substrate at a second depth greater than the first depth. The multiple through-portions directly land on the bottom surface of the source / drain. In another embodiment, the top surface of the multiple through-portions is higher than the bottom surface of the gate stack, and the top surface of the main portion is lower than the bottom surface of each gate stack.

[0062] Yet another aspect of the present invention relates to a method for forming a semiconductor device. The method includes receiving a workpiece having transistors formed above a substrate, wherein each transistor includes a channel region extending between source / drain features and a gate stack contacting the channel region; thinning the substrate from a backside of the workpiece; and forming dielectric plugs extending through the thinned substrate and landing on first and second source / drain features of the transistors, wherein the dielectric plugs are spaced apart from each other by the thinned substrate.

[0063] In one embodiment, the method further comprises: etching through the thinned substrate to form a contact structure trench exposing a third source / drain feature of the transistor; and forming a contact structure in the contact structure trench.

[0064] In one embodiment, forming the dielectric plug includes forming a dummy dielectric plug that penetrates the thinned substrate and lands on the third source / drain feature of the transistor, and the method for forming a semiconductor component further includes: removing the dummy dielectric plug to form a contact structure trench; and forming a contact structure in the contact structure trench.

[0065] In one embodiment, forming the dielectric plug includes: etching the thinned substrate to form a first trench exposing the source / drain feature, wherein the etching includes etching a portion of the source / drain feature; and depositing a dielectric material in the first trench.

[0066] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present invention, and that they can make various changes, substitutions, and modifications to the present invention without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor component, characterized in that: include: semiconductor substrates; a transistor formed above the semiconductor substrate, wherein the transistor includes a first source / drain feature, a second source / drain feature, a channel region extending between the first source / drain feature and the second source / drain feature, and a gate stack contacting the channel region; a first source / drain contact structure landing on a top surface of the first source / drain feature; a second source / drain contact structure landing on a top surface of the second source / drain feature; as well as A dielectric plug penetrates the semiconductor substrate and lands on a bottom surface of the first source / drain feature, wherein a width of the dielectric plug is equal to or smaller than a width of the first source / drain feature.

2. The semiconductor component according to claim 1, wherein The dielectric plug is a first dielectric plug, and the semiconductor device further includes: A second dielectric plug penetrates the semiconductor substrate and lands on a bottom surface of the second source / drain feature, wherein the second dielectric plug is spaced apart from the first dielectric plug by a portion of the semiconductor substrate.

3. The semiconductor component according to claim 1, wherein Also includes: A source / drain contact structure penetrates the semiconductor substrate and lands on a bottom surface of the second source / drain feature, wherein the source / drain contact structure is spaced apart from the dielectric plug by a portion of the semiconductor substrate.

4. The semiconductor component according to claim 1, wherein The dielectric plug includes an air gap.

5. The semiconductor component according to claim 1, wherein A top surface of the dielectric plug is located above a bottom surface of the gate stack.

6. A semiconductor component, characterized in that include: semiconductor substrates; transistors formed above the semiconductor substrate, wherein each transistor includes a channel region extending between source / drain features and a gate stack contacting the channel region; a source / drain contact structure landing on a top surface of the source / drain feature; as well as A dielectric plug penetrates the semiconductor substrate and lands on the bottom surface of the source / drain feature.

7. The semiconductor component according to claim 6, wherein: One of the dielectric plugs is a first dielectric plug landed on the bottom surface of a first source / drain feature among the source / drain features, and the other of the dielectric plugs is a second dielectric plug landed on the bottom surface of a second source / drain feature among the source / drain features, and the first dielectric plug and the second dielectric plug are embedded in the semiconductor substrate and spaced apart from each other by the semiconductor substrate.

8. The semiconductor component according to claim 6, wherein Each dielectric plug extends laterally between two adjacent ones of the channel regions.

9. The semiconductor component according to claim 8, wherein The lateral width of each dielectric plug is smaller than the lateral width of the source / drain features.

10. The semiconductor component according to claim 6, wherein One of the dielectric plugs has a main body portion and a plurality of through portions protruding from the main body portion, the main body portion extending into the semiconductor substrate at a first depth, and the plurality of through portions penetrating the semiconductor substrate at a second depth greater than the first depth. The plurality of penetration portions directly land on the bottom surface of the source / drain.

11. The semiconductor component according to claim 10, wherein: Top surfaces of the plurality of penetration portions are higher than bottom surfaces of the gate stacks, and a top surface of the main portion is lower than bottom surfaces of each gate stack.

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