Semiconductor structure

Abstract

Provided is a semiconductor structure. According to the utility model, the semiconductor structure comprises a substrate; the first substrate fin and the second substrate fin are raised from the substrate; the isolation component is arranged above the substrate and is positioned between the first substrate fin and the second substrate fin; a first bottom epitaxial feature over the first base fin; a second bottom epitaxial feature over the second base fin; an isolation layer on the first bottom epitaxial feature; a first source / drain feature over the isolation layer; a second source / drain feature disposed over and in contact with the second bottom epitaxial feature; contacting an etch stop layer over the first source / drain feature and the isolation feature; a first interlayer dielectric layer over the contact etch stop layer; and a second interlayer dielectric layer over and in contact with the second source / drain feature.

Description

Technical Field

[0001] The utility model relates to a semiconductor structure, in particular to a semiconductor structure with reduced defects. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Modern technological advances in IC materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous one. Over the course of IC development, functional density (i.e., the number of interconnected devices per unit chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be produced using a process) has decreased. This process of miniaturization generally benefits by increasing production efficiency and reducing associated costs. However, this miniaturization has also increased the complexity of producing and manufacturing ICs.

[0003] For example, as integrated circuit technology progresses to smaller technology nodes, multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short-channel effects (SCEs). A multi-gate device generally refers to a device having a gate structure or portion of a gate structure disposed above one or more sides of a channel region. Fin-like field effect transistors (FinFETs) and gate-all-around (GAA) transistors, as examples of multi-gate devices, have become popular and promising candidates for high-performance and low-leakage current applications. FinFETs have an elevated channel with a gate wrapped around more than one side (e.g., the gate wraps around the top and sidewalls of a "fin" of semiconductor material extending from a substrate). Gate-all-around transistors have a gate structure that can partially or completely extend around the channel region to provide access to the channel region on two or more sides. Because its gate structure surrounds the channel region, a wrapped-gate transistor is also called a surrounding gate transistor (SGT). Because the channel region of a wrapped-gate transistor can include nanowires or nanosheets, and its configuration is similar to a bridge, a wrapped-gate transistor is also called a multi-bridge-channel (MBC) transistor, a nanowire transistor, or a nanowire transistor.

[0004] Multi-gate devices can be fabricated using either a gate-first process or a gate-last process. In the former, a high-k metal gate structure or portion thereof is formed before forming the source / drain components. In the latter, a dummy gate stack is formed during the formation of the source / drain components and then replaced with a high-k metal gate structure. Utility Model Content

[0005] The purpose of the present invention is to provide a semiconductor structure to solve at least one of the above problems.

[0006] An embodiment of the present invention provides a semiconductor structure, comprising a substrate; a first base fin and a second base fin rising from the substrate; an isolation component disposed above the substrate and located between the first base fin and the second base fin; a first bottom epitaxial component above the first base fin; a second bottom epitaxial component above the second base fin; an isolation layer on the first bottom epitaxial component; a first source / drain component above the isolation layer; a second source / drain component disposed above the second bottom epitaxial component and in contact with the second bottom epitaxial component; a contact etch stop layer above the first source / drain component and the isolation component; a first interlayer dielectric layer above the contact etch stop layer; and a second interlayer dielectric layer above the second source / drain component and in contact with the second source / drain component.

[0007] According to one embodiment of the present invention, the first source / drain feature includes a faceted shape, and the second source / drain feature includes a circular shape.

[0008] According to one embodiment of the present invention, the first source / drain component is separated from the first bottom epitaxial component by an isolation layer.

[0009] According to one embodiment of the present invention, the device further includes: a gap below a sidewall of the second source / drain component away from the first source / drain component.

[0010] According to one embodiment of the present invention, the first source / drain component has a first width, wherein the second source / drain component has a second width, and wherein the second width is greater than the first width.

[0011] According to one embodiment of the present invention, the ratio of the second width to the first width is in a range of 1.2 to 1.5.

[0012] According to one embodiment of the present invention, the first source / drain feature is separated from the first interlayer dielectric layer by the contact etch stop layer, and the second source / drain feature contacts the first interlayer dielectric layer.

[0013] According to one embodiment of the present invention, top surfaces of the first base fin and the second base fin are flush with a top surface of the isolation component.

[0014] According to one embodiment of the present invention, the first interlayer dielectric layer extends into the isolation component.

[0015] According to one embodiment of the present invention, the device further includes: a first silicide layer above the first source / drain component; and a second silicide layer above the second source / drain component. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The embodiments of the present invention are best understood from the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of various elements may be arbitrarily increased or decreased to clearly illustrate the features of the embodiments of the present invention.

[0017] Figure 1 The present invention is a flowchart illustrating a method for forming a semiconductor device according to one or more aspects of the present invention.

[0018] Figures 2 to 27 According to one or more aspects of the present invention, Figure 1 A partial cross-sectional schematic diagram of a workpiece of a manufacturing process performed by the method.

[0019] The reference numerals are as follows:

[0020] 10PC: p-type channel region

[0021] 10NSD: n-type source / drain region

[0022] 10PSD: p-type source / drain region

[0023] 100: Method

[0024] 102,104,106: Box

[0025] 108,110,112: Box

[0026] 114,116,118: Box

[0027] 120,122,124: Box

[0028] 126,128,130,132: Box

[0029] 200:Workpiece

[0030] 202:Substrate

[0031] 204: Stack

[0032] 206: Sacrificial layer

[0033] 208: Channel layer

[0034] 210: Fin structure

[0035] 210B: Base fin

[0036] 211: Groove

[0037] 212: Shallow trench isolation component

[0038] 214: dummy dielectric layer

[0039] 216: dummy electrode layer

[0040] 217: Nitride hard mask layer

[0041] 218: Gate top hard mask layer

[0042] 219: oxide hard mask layer

[0043] 220:Dummy gate stack

[0044] 222: first spacer layer

[0045] 223: Gate spacer layer

[0046] 224: second spacer layer

[0047] 226: Source / drain groove

[0048] 227: Inner spacer groove

[0049] 228:Internal spacer component

[0050] 230: bottom epitaxial layer

[0051] 232: Isolation layer

[0052] 240N: n-type source / drain components

[0053] 240P: p-type source / drain components

[0054] 242: Contact etch stop layer

[0055] 246: interlayer dielectric layer

[0056] 248: Self-aligned capping layer

[0057] 250: Gate structure

[0058] 260: Gate cutting component

[0059] 262: p-type source / drain opening

[0060] 264: Gap

[0061] 270: Top interlayer dielectric layer

[0062] 272: first silicide layer

[0063] 274: Second silicide layer

[0064] 276: Lining

[0065] 278:Metal filling layer

[0066] 280: Source / drain contacts

[0067] 2080: Channel components

[0068] P-P': Section

[0069] W1: first width

[0070] W2: Second width

[0071] X: direction

[0072] Y: direction

[0073] Z: direction DETAILED DESCRIPTION

[0074] The following utility model provides many embodiments or examples for implementing the different elements provided. Specific examples of each element and its configuration are described below to simplify the description of the embodiments of the utility model. Of course, these are merely examples and are not intended to limit the embodiments of the utility model. For example, if the description mentions that a first element is formed on a second element, it may include an embodiment in which the first and second elements are in direct contact, and it may also include an embodiment in which an additional element is formed between the first and second elements so that they are not in direct contact. In addition, the embodiments of the utility model may repeat reference numbers and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity, and is not intended to indicate the relationship between the different embodiments and / or configurations discussed.

[0075] Furthermore, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and similar terms, may be used to facilitate describing the relationship between one component or feature and another component or feature in the drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation, as well as the orientations depicted in the drawings. When the device is rotated 90 degrees or in other orientations, the spatially relative adjectives used therein will also be interpreted based on the rotated orientation.

[0076] Furthermore, when the terms "about," "approximately," or the like are used to describe a number or range of numbers, such terms are intended to encompass numbers within a reasonable range that takes into account variations inherent in manufacturing processes as understood by those skilled in the art. For example, based on known manufacturing tolerances for manufacturing components having the features associated with the number, a number or range encompasses a reasonable range that includes the number, such as within ±10% of the number. For example, given that manufacturing tolerances associated with deposited material layers are known to those skilled in the art to be ±15%, a material layer having a thickness of "about 5 nanometers" may encompass a size range of 4.25 nanometers to 5.75 nanometers.

[0077] During the development of high-k (dielectric constant) metal gate technology, both gate-first and gate-last processes have been proposed. The gate-first process forms a high-k dielectric layer or metal gate structure before forming the source / drain components. In the gate-last process, a dummy gate stack is first formed above the channel region of the active area, which serves as a placeholder for forming the source / drain components. These dummy gate stacks are then removed and replaced with high-k metal gate structures. Because the gate-last process protects the high-k metal gate structure from high-temperature processing, it is known that the gate-last process can provide good thermal stability for the high-k dielectric layer and reduce the threshold voltage shift. When using the gate-last process to form p-type GAA transistors, there are some challenges. For example, in some cases, the process of releasing the channel layer into a suspended channel component may cause damage to the p-type source / drain component. In some cases, the p-type source / drain component may not fully strain the channel region before the channel component is released from the sacrificial layer.

[0078] The present invention provides a method for forming a semiconductor device with improved p-type device performance. This method forms n-type source / drain components before forming the gate structure of a GAA transistor, and forms p-type source / drain components after the gate structure is formed. By forming the p-type source / drain components last, the p-type source / drain components are less prone to defects and can effectively strain the channel region.

[0079] The various aspects of the present invention will now be described in more detail with reference to the accompanying drawings. Figure 1 1 is a flow chart illustrating a method 100 for forming a semiconductor device from a workpiece according to an embodiment of the present invention. The method 100 is merely an example and is not intended to limit the present invention beyond what is explicitly described in the method 100. Additional steps may be provided before, during, and after the method 100, and some steps may be replaced, eliminated, or moved forward or backward for additional embodiments of the method 100. For simplicity, not all steps are described in detail in the present invention. Figures 2 to 27 1 and 2 are schematic partial cross-sectional views of a semiconductor device at different stages of fabrication according to an embodiment of the method 100. Because the workpiece 200 will be fabricated into a semiconductor structure or semiconductor device, the workpiece 200 may be referred to as a semiconductor device 200 or a semiconductor structure 200 in this disclosure, depending on the context. For the avoidance of doubt, Figures 2 to 27 The directions X, Y, and Z are perpendicular to each other. Throughout the present invention, similar reference numerals are used to denote similar components unless otherwise specified. In addition, as used herein, source / drain regions or source / drain components may refer to a source or a drain individually or collectively, depending on the context.

[0080] See also Figure 1 as well as Figure 2 , the method 100 includes block 102, depositing a stack 204 of a sacrificial layer 206 and a channel layer 208 on a substrate 202. Figure 2As shown, workpiece 200 includes substrate 202. In some embodiments, substrate 202 may be a semiconductor substrate, such as a silicon (Si) substrate. Depending on design requirements known in the art, substrate 202 may include various doping configurations. In embodiments where the semiconductor device is p-type, an n-type doping profile (i.e., an n-type well or n-well) may be formed on substrate 202. In some embodiments, the n-type dopant used to form the n-type well may include phosphorus (P) or arsenide (As). In embodiments where the semiconductor device is n-type, a p-type doping profile (i.e., a p-type well or p-well) may be formed on substrate 202. In some implementations, the p-type dopant used to form the p-type well may include boron (B). Appropriate doping may be performed using dopant ion implantation and / or diffusion processes. Substrate 202 may also include other semiconductors, such as silicon germanium (Ge), silicon carbide (SiC), silicon germanium (SiGe), or diamond. Alternatively, substrate 202 may include a compound semiconductor and / or an alloy semiconductor. Additionally, the substrate 202 may optionally include an epitaxial layer (epi-layer), which may be strained to enhance performance, may include a silicon-on-insulator (SOI) or germanium-on-insulator (GeOI) structure, and / or may have other suitable enhancement features.

[0081] In some embodiments, the stack 204 includes sacrificial layers 206 of a first semiconductor composition interleaved with channel layers 208 of a second semiconductor composition. The first and second semiconductor compositions may be different. In some embodiments, the sacrificial layers 206 include silicon germanium (SiGe) and the channel layers 208 include silicon (Si). Figure 2 The depiction of three (3) layers of sacrificial layers 206 and three (3) layers of channel layers 208 in an alternating configuration is for illustrative purposes only and is not intended to limit the present invention beyond the scope of the claims. It should be understood that any number of epitaxial layers may be formed in the stack 204. The number of film layers depends on the desired number of channel components of the semiconductor device 200. In some embodiments, the number of channel layers 208 ranges from 2 to 10.

[0082] In some embodiments, all sacrificial layers 206 may have a substantially uniform first thickness, and all channel layers 208 may have a substantially uniform second thickness. The first thickness and the second thickness may be the same or different. As described in more detail below, the channel layers 208 or portions thereof may serve as (a plurality of) channel components of a subsequently formed multi-gate device, and the thickness of each channel layer 208 is selected based on device performance considerations. The sacrificial layers 206 in the channel region may eventually be removed and used to define the vertical distance (along the Z direction) between adjacent channel regions of the subsequently formed multi-gate device, and the thickness of each sacrificial layer 206 is selected based on device performance considerations.

[0083] The layers in stack 204 may be deposited using a molecular beam epitaxy (MBE) process, a vapor phase epitaxy (VPE) process, and / or other suitable epitaxial growth processes. As described above, in at least some examples, sacrificial layer 206 comprises an epitaxially grown silicon germanium (SiGe) layer and channel layer 208 comprises an epitaxially grown silicon (Si) layer. In some embodiments, sacrificial layer 206 and channel layer 208 are substantially free of dopants (i.e., have a dopant density in the range of approximately 0 cm). -3 to about 1×10 17 cm -3 extrinsic dopant concentration), for example, no intentional doping is performed during the epitaxial growth process of the stack 204 .

[0084] Still see Figure 1 as well as Figure 3 , method 100 includes box 104, forming a fin structure 210 from a portion of the stack 204 and the substrate 202. In order to pattern the stack 204, a hard mask layer (not explicitly shown in the figure) can be deposited over the stack 204 to form an etching mask. The hard mask layer can be a single film layer or a multi-film layer. For example, the hard mask layer can include a pad oxide layer and a pad nitride layer located above the pad oxide layer. The fin structure 210 can be patterned from the stack 204 and the portion of the substrate 202 using a photolithography process and an etching process. The photolithography process can include photoresist coating (e.g., spin-on coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable photolithography techniques and / or combinations thereof. In some embodiments, the etching process can include dry etching (e.g., reactive-ion etching (RIE)), wet etching and / or other etching methods. As Figure 3As shown, the etching process at box 104 forms a groove 211 extending through the stack 204 and a portion of the substrate 202. The groove 211 defines the fin structure 210. In addition to the portion formed from the stack 204, each fin structure 210 includes a base fin 210B extending from the substrate 202. In some embodiments, a double patterning or multiple patterning process can be used to define the fin structure 210, which has a smaller pitch than using a single, direct photolithography process. For example, in one embodiment, a material layer is formed above the substrate and patterned using a photolithography process. Spacers are formed along the patterned material layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers or mandrels can then be used to pattern the fin structure 210 by etching the stack 204 and a portion of the substrate 202. As shown in FIG. Figure 3 As shown, the fin structure 210 extends vertically along the direction Z and longitudinally along the direction X.

[0085] See also Figure 1 as well as Figure 3The method 100 includes block 106 of forming isolation features 212 between the fin structures 210. In some embodiments, the isolation features 212 may be deposited in trenches 211 between adjacent fin structures 210 to isolate them from each other. The isolation features 212 may also be referred to as shallow trench isolation (STI) features 212. For example, in some embodiments, a dielectric material is first deposited over the substrate 202 to fill the trenches 211 with the dielectric material. In some embodiments, the dielectric material may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, combinations thereof, and / or other suitable materials. In various examples, the dielectric layer can be deposited by a spin coating process, a chemical vapor deposition (CVD) process, a subatmospheric CVD (SACVD) process, a flowable CVD (FCVD) process, an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, and / or other suitable processes. The deposited dielectric material is then thinned and planarized, for example, by a chemical mechanical polishing (CMP) process. The planarized dielectric layer is further recessed or pulled back by a dry etch process, a wet etch process, and / or a combination thereof to form the STI features 212. After the recessed etching, the fin structure 210 is raised above the STI features 212.

[0086] See also Figure 1 and Figure 4 as well as Figure 5 The method 100 includes block 108 , forming a dummy gate stack 220 over the fin structure 210 . Figure 4 A partial cross-sectional view along the length direction (ie, direction Y) of the p-type fin structure 210 is shown, which includes a p-type channel region 10PC and p-type source / drain regions 10PSD. Figure 5 A partial cross-sectional view along the length direction (ie, direction X) of the dummy gate stack 220 is shown. Figure 4 can be considered along Figure 5 The cross-sectional view along the cross-sectional line PP' is shown. For simplicity, the partial cross-sectional view along the length direction of the n-type fin structure is omitted.

[0087] exist Figure 4 In some illustrated embodiments, the dummy gate stack 220 includes a dummy dielectric layer 214 and a dummy electrode layer 216. In those embodiments, a gate top hard mask layer 218 used to pattern the dummy gate stack 220 may remain on top of the dummy electrode layer 216 to protect the dummy electrode layer 216. In the illustrated embodiment, the gate top hard mask layer 218 may include a nitride hard mask layer 217 and an oxide hard mask layer 219 located above the nitride hard mask layer 217. In some embodiments, the dummy dielectric layer 214 may include silicon oxide, the dummy electrode layer 216 may include polysilicon, the nitride hard mask layer 217 may include silicon nitride or silicon oxynitride, and the oxide hard mask layer 219 may include silicon oxide. For ease of reference, the dummy gate stack 220 may be used to refer not only to the dummy dielectric layer 214 and the dummy electrode layer 216, but also to the gate top hard mask layer 218 (including the nitride hard mask layer 217 and the oxide hard mask layer 219). The dummy gate stack 220 serves as a placeholder to undergo various processes and is removed in subsequent steps and replaced with a functional gate structure. Figure 4 As shown, the dummy gate stack 220 is disposed in the channel region ( Figure 4 As shown above the p-type channel region 10PC). Figure 4 as well as Figure 5 As shown, the source / drain regions, including the p-type source / drain regions 10PSD and the n-type source / drain regions 10NSD, are not covered by the dummy gate stack 220. Each p-type channel region 10PC is disposed between two p-type source / drain regions 10PSD along the length of the fin structure 210 aligned with the direction Y. Each of the dummy dielectric layer 214, the dummy electrode layer 216, and the gate top hard mask layer 218 can be deposited using a CVD process, an ALD process, or a suitable deposition process. Similar to the fin structure 210, the dummy gate stack 220 can be patterned using photolithography and etching processes.

[0088] See also Figure 1 and Figure 4 as well as Figure 5 The method 100 includes block 110 of depositing a gate spacer layer 223 over the workpiece 200. The gate spacer layer 223 may be a single layer or multiple layers. Figure 4 as well as Figure 5An example of a multi-layer film is shown, in which the gate spacer layer 223 includes a first spacer layer 222 and a second spacer layer 224. The first spacer layer 222 and the second spacer layer 224 are conformally deposited above the workpiece 200, including above the top surface and sidewalls of the dummy gate stack 220. The present invention may use the term "conformally" to describe a film layer having a substantially uniform thickness over various regions. The first spacer layer 222 may have a lower dielectric constant than the second spacer layer 224, and the second spacer layer 224 etches slower than the first spacer layer 222. In some embodiments, the first spacer layer 222 may include silicon oxide, silicon oxycarbide, silicon nitride, or silicon oxycarbon nitride. The second spacer layer 224 may include silicon nitride, silicon oxycarbide, or silicon oxycarbon nitride, aluminum oxide, or a suitable dielectric material. When both the first spacer layer 222 and the second spacer layer 224 include silicon oxycarbide or silicon oxycarbon nitride, the carbon content of the second spacer layer 224 is greater than that of the first spacer layer 222, so as to have a stronger etching resistance. The first spacer layer 222 and the second spacer layer 224 may be deposited on the dummy gate stack 220 using a CVD process, a sub-atmospheric pressure CVD (SACVD) process, a flowable CVD (FCVD) process, an ALD process, a PVD process, or other suitable processes. Figure 4 as well as Figure 5 As shown, the gate spacer layer 223 is not only disposed on the sidewalls and top surface of the dummy gate stack 220 in the p-type channel region 10PC and the n-type channel region (not explicitly shown), but is also disposed on the sidewalls and top surface of the fin structure 210 in the n-type source / drain region 10NSD and the p-type source / drain region 10PSD.

[0089] See also Figure 1 and Figure 6 as well as Figure 7The method 100 includes block 112, where the source / drain regions of the fin structure 210 are recessed. Although not explicitly shown, the operation at block 112 may be performed using a photolithography process and at least one hard mask. At block 112, the n-type source / drain regions 10NSD and the p-type source / drain regions 10PSD of the fin structure 210 that are not covered by the dummy gate stack 220 and the gate spacer layer 223 are etched using a dry etch or suitable etching process to form source / drain recesses 226 (or source / drain trenches 226). For example, the dry etching process may be performed using an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBr3), an iodine-containing gas, other suitable gases and / or plasmas, and / or combinations thereof. exist Figure 6 as well as Figure 7 In some embodiments shown, the n-type source / drain region 10NSD and the p-type source / drain region 10PSD are recessed to expose the sidewalls of the sacrificial layer 206 and the channel layer 208 in the source / drain recess 226. Figure 7 As shown, the recess at block 112 may continue to extend downwardly into a portion of the substrate 202 .

[0090] See also Figure 1 and Figure 8 as well as Figure 9 The method 100 includes block 114 of selectively and partially etching the sacrificial layer 206 to form an inner spacer recess 227. At block 114, the sacrificial layer 206 exposed in the source / drain recess 226 is selectively and partially etched back along a direction Y to form the inner spacer recess 227, while the gate spacer layer 223 and the channel layer 208 are substantially unetched. In embodiments where the channel layer 208 consists essentially of Si and the sacrificial layer 206 consists essentially of SiGe, the selective etching back of the sacrificial layer 206 may include a SiGe oxidation process followed by SiGe oxide removal. In those embodiments, the SiGe oxidation process may include the use of ozone. In some embodiments, the selective etching back may be a selective isotropic etching process (e.g., a selective dry etching process or a selective wet etching process), and the extent of the etching back of the sacrificial layer 206 is controlled by the duration of the etching process. In some embodiments, the selective dry etching process may include using one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. In some embodiments, the selective wet etching process may include using hydrofluoride (HF) or ammonium hydroxide (NH4OH) etchants. Figure 8The illustrated structure may not undergo any changes at block 114 .

[0091] See also Figure 1 and Figure 10 as well as Figure 11 The method 100 includes block 116 of forming an inner spacer member 228 in the inner spacer recess 227. In some embodiments, the operation at block 116 may include blanket depositing an inner spacer material layer over the workpiece 200 and etching back the inner spacer material layer to form the inner spacer member 228. The inner spacer material layer may be a single layer or multiple layers. In some embodiments, the inner spacer material layer may be deposited using CVD, plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), ALD, or other suitable methods. The inner spacer material layer may include a metal oxide, silicon oxide, silicon oxycarbonitride, silicon nitride, silicon oxynitride, carbon-rich silicon carbide, or a low-k dielectric material. The metal oxide may include aluminum oxide, zirconium oxide, tantalum oxide, yttrium oxide, titanium oxide, lanthanum oxide, or other suitable metal oxides.

[0092] The deposited interspacer material layer is then etched back to remove the interspacer material layer from the sidewalls of the channel layer 208, thereby obtaining the interspacer feature 228 in the interspacer recess 227. At block 116, the interspacer material layer may also be removed from the top surfaces of the dummy gate stack 220, the gate spacer layer 223, and the isolation feature 212. In some embodiments, the composition of the interspacer material layer is selected such that the interspacer material layer can be selectively removed without substantially etching the gate spacer layer 223. In some embodiments, the etch-back operation performed at block 116 may include using hydrogen fluoride (HF), fluorine (F2), hydrogen (H2), ammonia (NH3), nitrogen trifluoride (NF3), or other fluorine-based etchants.

[0093] See also Figure 1 and Figure 12 as well as Figure 13The method 100 includes block 118 of forming a bottom epitaxial layer 230 above the source / drain trenches 226. The bottom epitaxial layer 230 may comprise an undoped semiconductor material, such as undoped silicon (Si), undoped germanium (Ge), or undoped silicon germanium (SiGe). In one embodiment, the bottom epitaxial layer 230 comprises undoped silicon (Si). The bottom epitaxial layer 230 may be epitaxially formed from the exposed top surface of the substrate 202 in the n-type source / drain region 10NSD and the p-type source / drain region 10PSD using process conditions that are more conducive to epitaxial growth on the top crystalline surface. Suitable epitaxial processes for block 118 may include an MBE process, a VPE process, an ultra-high vacuum chemical vapor deposition (UHV-CVD) process, a metal-organic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes. Due to the crystal alignment, the bottom epitaxial layer 230 deposited on the sidewalls of the channel layer 208 contains more crystal defects, which allows the bottom epitaxial layer 230 deposited on the sidewalls of the channel layer 208 to be selectively removed in a subsequent etch-back process. The bottom epitaxial layer 230 deposited on the exposed substrate 202 has fewer defects, and when the bottom epitaxial layer 230 with more defects on the sidewalls of the channel layer 208 is removed, the bottom epitaxial layer 230 deposited on the exposed substrate 202 can withstand the etching process.

[0094] See also Figure 1 and Figure 14 as well as Figure 15 Method 100 includes block 120 of forming an isolation layer 232 on the bottom epitaxial layer 230. In some embodiments, the isolation layer 232 is deposited on the bottom epitaxial layer 230 to prevent or reduce leakage current from the n-type source / drain components to the substrate 202. In an exemplary process, the isolation layer 232 is directionally / anisotropically deposited over the workpiece 200 such that the isolation layer 232 is thicker on the top surface than on the sidewalls. An isotropic etch-back process is then performed to remove the thinner isolation layer 232 on the sidewalls, leaving the isolation layer 232 on the bottom epitaxial layer 230. The isolation layer 232 may comprise silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, or silicon oxynitride and carbonitride. In one embodiment, the isolation layer 232 comprises silicon nitride. In some embodiments, the isolation layer 232 may be deposited using CVD or plasma-enhanced CVD (PECVD).

[0095] See also Figure 1 and Figure 14 as well as Figure 15 Method 100 includes block 122 of forming n-type source / drain features 240N over n-type source / drain regions 10NSD. Although not explicitly shown, a masking layer, such as a bottom antireflective coating (BARC), may be deposited over workpiece 200 to cover the p-type active regions, including p-type source / drain regions 10PSD, while leaving n-type source / drain regions 10NSD exposed. At block 122, n-type source / drain features 240N are formed over n-type source / drain regions 10NSD by epitaxially and selectively depositing one or more epitaxial layers on the exposed sidewalls of channel layer 208. The one or more epitaxial layers in n-type source / drain features 240N may include silicon (Si) and be in-situ doped with n-type dopants, such as phosphorus (P) or arsenic (As). When multiple epitaxial layers are present in the n-type source / drain feature 240N, the epitaxial layers closer to the sidewalls of the channel layer 208 may contain a lower n-type dopant concentration than the epitaxial layers farther from the sidewalls of the channel layer 208. Suitable epitaxial deposition processes for depositing the n-type source / drain feature 240N may include an MBE process, a VPE process, an UHV-CVD process, or an MOCVD process. In some embodiments, to ensure the quality of the n-type source / drain feature 240N, the process temperature for depositing the n-type source / drain feature 240N may range from approximately 500° C. to approximately 750° C. To activate the dopants in the n-type source / drain feature 240N, block 122 may include an annealing process to anneal the n-type source / drain feature 240N. In some embodiments, the annealing process may include a rapid thermal annealing (RTA) process, a laser spike annealing process, a flash annealing process, or a furnace annealing process. In some cases, the annealing process includes a peak annealing temperature ranging from about 900° C. to about 1100° C. After forming the n-type source / drain features 240N, the mask layer (e.g., BARC layer) is removed by ashing.

[0096] See also Figure 1 and Figure 16 as well as Figure 17, the method 100 includes block 124, depositing a contact etch stop layer 242 (CESL) and an interlayer dielectric (ILD) layer 246 over the n-type source / drain features 240N, and depositing an isolation layer 232 over the p-type source / drain regions 10PSD. The operations at block 124 may include forming the CESL 242, depositing the ILD layer 246 over the CESL 242, performing a planarization process to remove excess ILD layer material, etching back the ILD layer 246, forming a self-alignment capping (SAC) layer 248, and performing a planarization process to expose the dummy electrode layer 216. Figure 16 as well as Figure 17 As shown, CESL 242 is formed before forming ILD layer 246. In some examples, CESL 242 may include silicon nitride, silicon oxynitride, or a combination thereof. CESL 242 may be formed using ALD, plasma-enhanced chemical vapor deposition (PECVD), and / or other suitable deposition or oxidation processes. ILD layer 246 is then deposited over CESL 242. In some embodiments, ILD layer 246 includes a material such as tetraethylorthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and / or other suitable dielectric materials. ILD layer 246 may be deposited using flowable CVD (FCVD), spin coating, PECVD, or other suitable deposition techniques. In some embodiments, after forming the ILD layer 246 , the workpiece 200 may be annealed to improve the integrity of the ILD layer 246 .

[0097] After depositing the ILD layer 246, a planarization process, such as a chemical mechanical polishing (CMP) process, is performed to remove excess ILD layer material and provide a flat top surface. After the planarization process, a wet etching process that is selective to silicon oxide is used to selectively etch back the ILD layer 246. For example, the wet etching process may include a dilute hydrogen fluoride (DHF) solution or a buffered oxide etch (BOE) process using dilute hydrogen fluoride and ammonium fluoride (NH4F). After the ILD layer 246 is recessed, a SAC layer 248 is deposited over the recessed ILD layer 246. In some embodiments, the SAC layer 248 may include silicon nitride, silicon carbon oxynitride, or silicon oxynitride. A planarization process is performed to remove excess SAC layer 248. Figure 16 as well as Figure 17 In the illustrated embodiment, before forming the SAC layer 248, a dummy gate cutting process is performed to form a cut dummy gate trench through the dummy gate stack 220, the ILD layer 246, and possibly a portion of the CESL 242. A dielectric material such as silicon nitride, aluminum oxide, or hafnium oxide is deposited to form the cut dummy gate trench, thereby forming the gate cutting feature 260. Figure 16 As shown, each gate cut feature 260 may partially extend into the isolation feature 212 .

[0098] See also Figure 1 、 Figure 18 、 Figure 19 and Figure 20 as well as Figure 21 , the method 100 includes block 126 of replacing the dummy gate stack 220 with the gate structure 250. Figure 19As shown, the dummy electrode layer 216 exposed in block 124 is then selectively removed, followed by the selective removal of the dummy dielectric layer 214. Removing the dummy electrode layer 216 and the dummy dielectric layer 214 can include one or more etching processes that are selective to the materials in the dummy electrode layer 216 and the dummy dielectric layer 214. For example, the removal of the dummy electrode layer 216 and the dummy dielectric layer 214 can be performed using a selective wet etch, a selective dry etch, or a combination thereof that is selective to the dummy electrode layer 216 and the dummy electrode layer 214. After removing the dummy electrode layer 216 and the dummy dielectric layer 214, the surface of the channel layer 208 and the sacrificial layer 206 in the channel region is exposed by the gate trench. The sacrificial layer 206 in the channel region is then selectively removed to release the channel layer 208 as a channel feature 2080. The selective removal of the sacrificial layer 206 can be performed by a selective dry etch, a selective wet etch, or other selective etching process. In some embodiments, the selective wet etch comprises an ammonia and hydrogenperoxide mixture (APM) etch (e.g., an ammonium hydroxide-hydrogenperoxide-water mixture). In some embodiments, the selective removal comprises SiGe oxidation followed by SiGeO x For example, oxidation can be provided by ozone cleaning, followed by removal of SiGeO by an etchant such as NH4OH. x .like Figure 18 As shown, the n-type source / drain regions 10NSD and the p-type source / drain regions 10PSD are covered by the SAC layer 248 , the ILD layer 246 , and the CESL 242 .

[0099] Now see Figure 20 as well as Figure 21 After releasing the channel features 2080, a gate structure 250 is formed in the channel region to wrap around each channel feature 2080. Figure 21In the illustrated embodiment, a gate structure 250 is formed over the p-type channel region 10PC to surround each channel feature 2080. The gate structure 250 may be a high-k metal gate structure comprising a high-k gate dielectric material and a metal. Here, a high-k dielectric material refers to a dielectric material having a dielectric constant greater than that of silicon dioxide (approximately 3.9). In various embodiments, each gate structure 250 includes an interfacial layer, a high-k gate dielectric layer formed over the interfacial layer, and / or a gate electrode layer formed over the high-k gate dielectric layer. The interfacial layer may comprise a dielectric material such as silicon oxide, hafnium silicate, or silicon oxynitride. The interfacial layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The high-k gate dielectric layer may comprise a high-k dielectric layer such as hafnium oxide. Alternatively, the high-K gate dielectric layer may include other high-K dielectrics such as TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO3 (BST), Al2O3, Si3N4, oxynitride (SiON), combinations thereof, or other suitable materials. The high-K gate dielectric layer may be formed by ALD, physical vapor deposition (PVD), CVD, oxidation, and / or other suitable methods.

[0100] The gate electrode layer may comprise a single film layer or, alternatively, a multi-layer structure, such as various combinations of a metal layer having a selected work function to enhance device performance (work function metal layer), a liner layer, a wetting layer, an adhesion layer, a metal alloy, or a metal silicide. For example, the gate electrode layer may comprise Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, Re, Ir, Co, Ni, other suitable metal materials, or combinations thereof. In various embodiments, the gate electrode layer may be formed by ALD, PVD, CVD, electron beam evaporation (e-beam evaporation), or other suitable processes. In some embodiments, the gate structure 250 above the p-type channel region 10PC and the n-type channel region (not explicitly shown) may have different compositions and may be formed separately. For example, the gate structure 250 above the p-type channel region 10PC may include a p-type work function metal layer, while the gate structure 250 above the n-type channel region may include an n-type work function metal layer. In various embodiments, a CMP process may be performed to remove excess metal from the workpiece 200, thereby providing a substantially flat top surface of the gate structure 250.

[0101] See also Figure 1 、 Figure 22 as well as Figure 23 The method 100 includes block 128, forming p-type source / drain access openings 262 above the p-type source / drain region 10PSD. After forming the high-k metal gate structure 250 at block 126, photolithography and etching techniques are used to form the p-type source / drain access openings 262 above the p-type source / drain region 10PSD. Figure 22 As representatively shown, p-type source / drain openings 262 are formed, while n-type source / drain features 240N are protected by the SAC layer 248, the ILD layer 246, and the CESL 242. Figure 22 As shown, the p-type source / drain opening 262 can expose the first spacer layer 222 and the second spacer layer 224 above the p-type source / drain region 10PSD. In addition, the p-type source / drain opening 262 also exposes the sidewalls and top surface of the gate cut feature 260 adjacent to the p-type source / drain region 10PSD. Figure 22 as well as Figure 23 In some embodiments shown, in order to provide more semiconductor surface for the p-type source / drain features, the formation of the p-type source / drain openings 262 also removes the isolation layer 232 above the bottom epitaxial layer 230 above the p-type source / drain regions 10PSD. Figure 23 As shown, the p-type source / drain openings 262 expose not only the top surface of the bottom epitaxial layer 230 , but also the sidewalls of the released channel features 2080 that are no longer attached to the sacrificial layer 206 .

[0102] See also Figure 1 and Figure 24 as well as Figure 25Method 100 includes block 130 of forming p-type source / drain features 240P above p-type source / drain region 10PSD. Because p-type source / drain openings 262 expose the sidewalls of channel feature 2080 and the top surface of bottom epitaxial layer 230, p-type source / drain features 240P are epitaxially and selectively deposited on these exposed semiconductor surfaces. In some embodiments, each p-type source / drain feature 240P includes one or more epitaxial layers. One or more epitaxial layers in p-type source / drain features 240P may include silicon germanium (SiGe) and be in-situ doped with a p-type dopant, such as boron (B). When multiple epitaxial layers are present in p-type source / drain features 240P, epitaxial layers closer to the sidewalls of channel feature 2080 and the top surface of bottom epitaxial layer 230 may include a lower p-type dopant concentration than epitaxial layers further from the sidewalls of channel layer 2080 and the top surface of bottom epitaxial layer 230. Suitable epitaxial deposition processes for depositing the p-type source / drain features 240P may include an MBE process, a VPE process, an UHV-CVD process, or an MOCVD process. In some embodiments, to minimize thermal impact on the high-k gate dielectric layer in the formed gate structure 250, the process temperature for depositing the p-type source / drain features 240P may range from about 200° C. to about 500° C., which is lower than the deposition temperature for forming the n-type source / drain features 240N.

[0103] In some embodiments, because the low temperature epitaxial deposition selectivity of the p-type source / drain features 240P is low, the p-type source / drain features 240P are faceted and rounded. When viewed along the channel length direction (direction Y), the p-type source / drain features 240P are significantly wider along direction X. Now referring to Figure 24 The n-type source / drain feature 240N has a first width W1 along the direction X, and the p-type source / drain feature 240P has a second width W2 along the direction X. The second width W2 is greater than the first width W1. In some cases, the ratio of the second width W2 to the first width W1 can range from about 1.2 to about 1.5. In some embodiments, the p-type source / drain feature 240P can directly contact the adjacent gate-cut feature 260, which may hinder the subsequent deposition of a top interlayer dielectric (ILD) layer 270 (described below).

[0104] Forming the p-type source / drain features 240P after forming the gate structure 250 provides several advantages. For example, the p-type source / drain features 240P can more effectively compress the channel feature 2080. Before releasing the channel feature 2080, the sacrificial layer 206 can apply tensile stress to the channel layer 208, thereby preventing compressive stress from being effectively applied to the channel layer 208. For another example, when the channel feature 2080 is released, the p-type source / drain features 240P are more susceptible to damage. Forming the p-type source / drain features 240P after releasing the channel feature 2080 avoids the possibility of such damage.

[0105] See also Figure 1 and Figure 26 as well as Figure 27 The method 100 includes block 132 of forming source / drain contacts 280. The operations at block 132 may include depositing a top ILD layer 270 over the p-type source / drain feature 240P, forming a source / drain contact opening to expose both the p-type source / drain feature 240P and the n-type source / drain feature 240N, forming a first silicide layer 272 over the n-type source / drain feature 240N and a second silicide layer 274 over the p-type source / drain feature 240P, forming a liner 276 over the sidewalls of the source / drain contact opening, and depositing a metal fill layer 278 in the source / drain contact opening. In some embodiments, the top ILD layer 270 may be similar to the ILD layer 246 in terms of composition and formation process. Unlike the ILD layer 246 that is spaced apart from the n-type source / drain feature 240N, the top ILD layer 270 is deposited directly on the p-type source / drain feature 240P. That is, the surface of the p-type source / drain feature 240P is free from a corresponding portion of the CESL 242. In addition, the top ILD layer 270 may be in direct contact with the first spacer layer 222 and the second spacer layer 224 above the p-type source / drain region 10PSD. The p-type source / drain feature 240P, which may be in contact with the sidewall of the gate cut feature 260, may hinder the deposition of the top ILD layer 270. Figure 26 As shown, a gap 264 may exist between the p-type source / drain feature 240P and the gate-cut feature 260 .

[0106] To form the first silicide layer 272 and the second silicide layer 274, a metal precursor (e.g., titanium (Ti), cobalt (Co), or nickel (Ni)) is deposited over the source / drain contact openings. Annealing is then performed to induce silicidation between the metal precursor and the exposed n-type source / drain features 240N and p-type source / drain features 240P. A selective wet etch may be used to selectively remove excess metal precursor that does not become the first silicide layer 272 or the second silicide layer 274. In some embodiments, the first silicide layer 272 may include titanium silicide, cobalt silicide, or nickel silicide, while the second silicide layer 274 may include titanium germanium silicide, cobalt germanium silicide, or nickel germanium silicide. In another exemplary process, a metal halide precursor (e.g., titanium tetrachloride) and a silicon-containing precursor (e.g., SiH4) are used in a CVD process to form the first silicide layer 272 and the second silicide layer 274. After forming the first silicide layer 272 and the second silicide layer 274, a liner 276 is deposited over the workpiece 200 using ALD or CVD. An anisotropic dry etching process may be performed to remove the liner 276 from the first silicide layer 272 and the second silicide layer 274. In some embodiments, the liner 276 comprises silicon nitride or titanium nitride. After forming the liner, a metal fill layer 278 is deposited over the source / drain contact openings to form the source / drain contacts 280. In some cases, the metal fill layer 278 may comprise cobalt (Co), nickel (Ni), tungsten (W), or copper (Cu).

[0107] In one exemplary aspect, the present invention relates to a method for forming a semiconductor structure. The method includes receiving a workpiece, which includes a substrate, the substrate including a first region and a second region, and a first fin-like structure above the first region and a second fin-like structure above the second region, each of the first fin-like structure and the second fin-like structure including a plurality of channel layers interleaved by a plurality of sacrificial layers, forming a first dummy gate stack above the channel region of the first fin-like structure and forming a second dummy gate stack above the channel region of the second fin-like structure, forming at least one gate spacer layer above the first dummy gate stack and the second dummy gate stack, recessing the source / drain region of the first fin-like structure and the source / drain region of the second fin-like structure to form a first source / drain recess and a second source / drain recess, and selectively forming a first source / drain component at A first source / drain groove is formed above the first source / drain groove, while the second source / drain groove is covered by a mask layer, the mask layer is removed, a first interlayer dielectric layer is deposited above the first source / drain component and the second source / drain groove, the first dummy gate stack and the second dummy gate stack are removed, the channel layer in the channel region of the first fin-like structure and the channel region of the second fin-like structure is released to form a plurality of first channel components in the first region and a plurality of second channel components in the second region, a first gate structure is formed to surround each first channel component and a second gate structure is formed to surround each second channel component, and after forming the first gate structure and the second gate structure, an opening is formed above the second source / drain groove, and a second source / drain component is formed above the opening.

[0108] In some embodiments, the first source / drain component comprises an n-type source / drain component, and the second source / drain component comprises a p-type source / drain component. In some embodiments, the step of selectively forming the first source / drain component comprises a first process temperature, and the step of forming the second source / drain component comprises a second process temperature, wherein the second process temperature is less than the first process temperature. In some embodiments, the first process temperature ranges from approximately 500°C to approximately 800°C, and the second process temperature ranges from approximately 200°C to approximately 500°C. In some embodiments, the first source / drain component comprises a faceted shape, and the second source / drain component comprises a rounded shape. In some embodiments, the method further comprises, prior to the step of selectively forming the first source / drain component, depositing a bottom epitaxial layer over the first source / drain recess and the second source / drain recess, and depositing an isolation layer over the bottom epitaxial layer. In some embodiments, the bottom epitaxial layer comprises undoped silicon, undoped silicon germanium, or undoped germanium, and the isolation layer comprises silicon nitride. In some embodiments, the step of forming the opening includes removing the isolation layer above the second source / drain recess to expose the bottom epitaxial layer in the second region, and the step of forming the second source / drain component includes forming the second source / drain component directly above the bottom epitaxial layer. In some embodiments, after the step of selectively forming the first source / drain component, the first source / drain component is separated from the bottom epitaxial layer by the isolation layer.

[0109] In another exemplary aspect, the present invention relates to a method for forming a semiconductor structure, the method comprising receiving a workpiece comprising a substrate, a first base fin and a second base fin over the substrate, and an isolation feature disposed over the substrate and between the first base fin and the second base fin, forming a first bottom epitaxial layer over the first base fin and a second bottom epitaxial layer over the second base fin, forming a first isolation layer over the first bottom epitaxial layer and a second isolation layer over the second bottom epitaxial layer, selectively forming a first source / drain feature over the first isolation layer, forming a contact etch stop layer over the first source / drain feature and the second isolation layer, forming a first interlayer dielectric layer over the contact etch stop layer, forming an opening through the first interlayer dielectric layer, the contact etch stop layer, and the second isolation layer to expose the second bottom epitaxial layer, forming a second source / drain feature over the exposed second bottom epitaxial layer, and forming a second interlayer dielectric layer over the second source / drain feature.

[0110] In some embodiments, the first bottom epitaxial layer and the second bottom epitaxial layer include undoped silicon, undoped silicon germanium, or undoped germanium. In some embodiments, the first source / drain component includes silicon and n-type dopants, and the second source / drain component includes silicon germanium and p-type dopants. In some embodiments, after the step of forming the second interlayer dielectric layer, the second interlayer dielectric layer is in direct contact with the second source / drain component. In some embodiments, the step of selectively forming the first source / drain component includes a first process temperature, and the step of forming the second source / drain component includes a second process temperature, and the second process temperature is less than the first process temperature. In some embodiments, the first process temperature ranges from about 500°C to about 800°C, and the second process temperature ranges from about 200°C to about 500°C. In some embodiments, the step of selectively forming the first source / drain component includes depositing a mask layer to cover the second base fin.

[0111] In another exemplary aspect, the present invention relates to a semiconductor structure comprising a substrate, a first base fin and a second base fin raised from the substrate, an isolation member disposed above the substrate and between the first base fin and the second base fin, a first bottom epitaxial member above the first base fin, a second bottom epitaxial member above the second base fin, an isolation layer above the first bottom epitaxial member, a first source / drain member above the isolation layer, a second source / drain member disposed above and in contact with the second bottom epitaxial member, a contact etch stop layer above the first source / drain member and the isolation member, a first interlayer dielectric layer above the contact etch stop layer, and a second interlayer dielectric layer above and in contact with the second source / drain member.

[0112] In some embodiments, the first source / drain component comprises silicon and n-type dopants, and the second source / drain component comprises silicon germanium and p-type dopants. In some embodiments, the first bottom epitaxial component and the second bottom epitaxial component comprise undoped silicon, undoped silicon germanium, or undoped germanium. In some embodiments, the first source / drain component comprises a faceted shape, and the second source / drain component comprises a rounded shape.

[0113] The features of several embodiments are summarized above so that those skilled in the art to which the present invention belongs can better understand the viewpoints of the embodiments of the present invention. Those skilled in the art to which the present invention belongs should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art to which the present invention belongs should also understand that such equivalent structures do not deviate from the spirit and scope of the present invention, and various changes, substitutions, and replacements can be made without violating the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be defined as defined by the appended claims.

Claims

1. A semiconductor structure, characterized in that include: a substrate; a first base fin and a second base fin rising from the substrate; an isolation component disposed above the substrate and between the first base fin and the second base fin; a first bottom epitaxial component above the first base fin; a second bottom epitaxial member above the second base fin; an isolation layer on the first bottom epitaxial component; a first source / drain component above the isolation layer; a second source / drain component disposed above and in contact with the second bottom epitaxial component; a contact etch stop layer over the first source / drain feature and the isolation feature; a first interlayer dielectric layer over the contact etch stop layer; as well as A second interlayer dielectric layer is above the second source / drain component and contacts the second source / drain component.

2. The semiconductor structure according to claim 1, wherein wherein the first source / drain feature comprises a faceted shape, and The second source / drain component includes a circular shape.

3. The semiconductor structure according to claim 1, wherein: The first source / drain component is separated from the first bottom epitaxial component by an isolation layer.

4. The semiconductor structure according to claim 1, wherein: Also includes: A gap is below a sidewall of the second source / drain component away from the first source / drain component.

5. The semiconductor structure according to claim 1, wherein wherein the first source / drain component has a first width, wherein the second source / drain component has a second width, and The second width is greater than the first width.

6. The semiconductor structure according to claim 5, wherein: The ratio of the second width to the first width is in a range of 1.2 to 1.

5.

7. The semiconductor structure according to claim 1, wherein: wherein the first source / drain feature is separated from the first interlayer dielectric layer by the contact etch stop layer, and The second source / drain component contacts the first interlayer dielectric layer.

8. The semiconductor structure according to claim 1, wherein: The top surfaces of the first base fin and the second base fin are flush with the top surface of the isolation component.

9. The semiconductor structure according to claim 1, wherein: The first interlayer dielectric layer extends into the isolation component.

10. The semiconductor structure according to claim 1, wherein: Also includes: a first silicide layer over the first source / drain feature; as well as A second silicide layer is formed on the second source / drain feature.

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