Semiconductor device

Abstract

A semiconductor device includes a photodiode including a germanium material portion extending laterally in a first horizontal direction, a p-type doped silicon portion, and an n-type doped silicon portion; and a distributed Bragg reflector comprising a plurality of periodic repetitions of a stack of unit layers, the stack of unit layers comprising a first material layer and a second material layer, where an interface between vertically extending portions of the material layers within the distributed Bragg reflector is perpendicular to a first horizontal direction, and wherein the distributed Bragg reflector contacts the germanium material portion.

Description

Technical Field

[0001] The embodiments of the present invention relate to semiconductor technology, and more particularly to semiconductor devices. Background Art

[0002] A photodetector is a semiconductor device that can convert incident photons into electrical signals. Photodetectors are used in a variety of applications such as light detection, lidar, optical communications, cameras, etc. An ideal germanium pin photodetector should have high responsivity, low dark current, and high bandwidth. However, a trade-off between high responsivity and low dark current (or high bandwidth) is usually required in germanium pin photodetectors. For example, optical applications (such as O-band applications using light with a wavelength of 1550nm) use extended photodiode length to provide high responsivity, which increases dark current and reduces bandwidth. Therefore, it is necessary to enhance the light absorption efficiency to provide improved performance of the photodetector. Utility Model Content

[0003] The purpose of the present invention is to provide a semiconductor device to solve at least one of the above problems.

[0004] The utility model provides a semiconductor device, comprising: a photodiode, comprising a germanium material portion, a p-type doped silicon portion, and an n-type doped silicon portion extending laterally along a first horizontal direction; and a distributed Bragg reflector, comprising a plurality of periodic repetitions of a unit layer stack, the unit layer stack comprising a first material layer and a second material layer, wherein a plurality of interfaces between a plurality of vertically extending portions of the material layers within the distributed Bragg reflector are perpendicular to the first horizontal direction, and wherein the distributed Bragg reflector contacts the germanium material portion.

[0005] According to one embodiment of the present disclosure, the germanium material portion includes an inclined protrusion that protrudes laterally into the distributed Bragg reflector, so that in a plan view, two interfaces between the inclined protrusion and the distributed Bragg reflector are adjacent to each other at an angle between 80 degrees and 100 degrees.

[0006] According to one embodiment of the present disclosure, a transverse length of the inclined protruding portion along the first horizontal direction is the same as the thickness of the portion of the first material layer contacting the germanium material.

[0007] According to one embodiment of the present disclosure, each of the two interfaces is located in a corresponding flat vertical plane and is adjacent to a corresponding longitudinal sidewall of the germanium material portion extending laterally along the first horizontal direction.

[0008] According to one embodiment of the present disclosure, the germanium material portion has a uniform width along a second horizontal direction perpendicular to the first horizontal direction.

[0009] According to one embodiment of the present disclosure, the method further includes two shallow trench isolation structures laterally spaced apart from each other through the germanium material portion, wherein each of the shallow trench isolation structures contacts a corresponding longitudinal sidewall of the germanium material portion.

[0010] The utility model provides a semiconductor device, comprising: a silicon waveguide, located above a buried insulating layer and extending laterally along a first horizontal direction; a silicon material substrate, adjacent to an end of the silicon waveguide and embedded with a germanium material portion, the germanium material portion extending laterally along the first horizontal direction and aligned with the end of the silicon waveguide; and a distributed Bragg reflector, comprising a plurality of periodic repetitions of a unit layer stack, the unit layer stack comprising a first material layer and a second material layer, wherein a plurality of interfaces between a plurality of vertically extending portions of the material layers within the distributed Bragg reflector are perpendicular to the first horizontal direction, and wherein the distributed Bragg reflector contacts the germanium material portion.

[0011] According to one embodiment of the present disclosure, the present invention further includes a p-type doped silicon portion and an n-type doped silicon portion embedded in the silicon material matrix and contacting the germanium material portion.

[0012] According to one embodiment of the present disclosure, the germanium material portion includes an inclined protruding portion, which protrudes laterally into the distributed Bragg reflector having a triangular horizontal cross-sectional shape.

[0013] According to one embodiment of the present disclosure, it also includes a dielectric cap layer covering the silicon material substrate, wherein: a top surface of the germanium material portion contacts a side wall of the dielectric cap layer; and each of the first material layer and the second material layer in the distributed Bragg reflector has a corresponding flat top surface in a horizontal plane covering a top surface of the germanium material portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The embodiments of the present invention are best understood by the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various components are not drawn to scale. Indeed, the dimensions of various elements may be arbitrarily increased or decreased to clearly illustrate the components of the embodiments of the present invention.

[0015] Figure 1A-Figure 1D are various views of an exemplary structure after forming a p-type doped silicon portion and an n-type doped silicon portion according to an embodiment of the present invention. Figure 1A It is a top view. Figure 1B It is along Figure 1A Vertical cross-section of the vertical plane B-B'. Figure 1C It is along Figure 1A Vertical cross-section of the vertical plane C-C'. Figure 1D It is along Figure 1A Vertical cross-section of the vertical plane D-D'.

[0016] Figures 2A-2D are various views of an exemplary structure after patterning the top silicon layer into silicon waveguides and a silicon material matrix and forming shallow trench isolation structures according to an embodiment of the present invention. Figure 2A It is a top view. Figure 2B It is along Figure 2A Vertical cross-section of the vertical plane B-B'. Figure 2C It is along Figure 2A Vertical cross-section of the vertical plane C-C'. Figure 2D It is along Figure 2A Vertical cross-section of the vertical plane D-D'.

[0017] Figure 3A-3C are various views of an exemplary structure after forming a dielectric cap layer according to an embodiment of the present invention. Figure 3A It is a top view. Figure 3B It is along Figure 3A Vertical cross-section of the vertical plane B-B'. Figure 3C It is along Figure 3A Vertical cross-section of the vertical plane C-C'.

[0018] Figures 4A-4C are various views of an exemplary structure after forming trenches in a distributed Bragg reflector region according to an embodiment of the present invention. Figure 4A It is a top view. Figure 4B It is along Figure 4A Vertical cross-section of the vertical plane B-B'. Figure 4C It is along Figure 4A Vertical cross-section of the vertical plane C-C'.

[0019] Figures 5A-5C are various views of an example structure after forming a layer of distributed Bragg reflector material according to an embodiment of the present invention. Figure 5A It is a top view. Figure 5B It is along Figure 5A Vertical cross-section of the vertical plane B-B'. Figure 5C It is along Figure 5A Vertical cross-section of the vertical plane C-C'.

[0020] Figures 6A-6C are various views of an exemplary structure after patterning a layer of distributed Bragg reflector material according to an embodiment of the present invention. Figure 6A It is a top view. Figure 6B It is along Figure 6A Vertical cross-section of the vertical plane B-B'. Figure 6C It is along Figure 6AVertical cross-section of the vertical plane C-C'.

[0021] Figures 7A-7C are various views of an example structure after forming a laterally extending cavity according to an embodiment of the present invention. Figure 7A It is a top view. Figure 7B It is along Figure 7A Vertical cross-section of the vertical plane B-B'. Figure 7C It is along Figure 7A Vertical cross-section of the vertical plane C-C'.

[0022] Figures 8A to 8D are various views of an exemplary structure after forming a germanium material portion and a silicon cap layer according to an embodiment of the present invention. Figure 8A It is a top view. Figure 8B It is along Figure 8A Vertical cross-section of the vertical plane B-B'. Figure 8C It is along Figure 8A Vertical cross-section of the vertical plane C-C'. Figure 8D It is along Figure 8B and Figure 8C Horizontal cross-sectional view of an exemplary structure taken along the horizontal plane DD'.

[0023] Figures 9A-9C are various views of an exemplary structure after forming a dielectric cap layer, a contact-level dielectric layer, and a contact via structure according to an embodiment of the present invention. Figure 9A It is a top view. Figure 9B It is along Figure 9A Vertical cross-section of the vertical plane B-B'. Figure 9C It is along Figure 9A Vertical cross-section of the vertical plane C-C'.

[0024] Figure 10 is a vertical cross-sectional view of an alternative configuration of an exemplary structure according to an embodiment of the present invention.

[0025] Figure 11 is a process flow diagram illustrating an exemplary process sequence for forming a semiconductor structure according to an embodiment of the present invention.

[0026] The reference numerals are as follows:

[0027] 4: Process the substrate

[0028] 6:Buried insulation layer

[0029] 10L: Top silicon layer

[0030] 10M: Silicon material matrix

[0031] 10W:Silicon waveguide

[0032] 12: Shallow trench isolation structure

[0033] 16: Shallow trench isolation structure

[0034] 22: Second p-type doped silicon portion

[0035] 24: First p-type doped silicon portion

[0036] 25: Dielectric cap layer

[0037] 26: First n-type doped silicon portion

[0038] 28: Second n-type doped silicon portion

[0039] 40: Distributed Bragg Reflector (DBR)

[0040] 40L: Distributed Bragg reflector (DBR) material layer

[0041] 42: First material layer

[0042] 44: Second material layer

[0043] 46:DBR backing structure

[0044] 48: Dielectric lining

[0045] 49: Reflector area groove

[0046] 62: Germanium material part

[0047] 62P: protruding part

[0048] 64: Silicon cap layer

[0049] 66: dielectric cap layer

[0050] 69: Cavity

[0051] 80: contact level dielectric layer

[0052] 82: Contact guide hole structure

[0053] 88: Contact guide hole structure

[0054] 1110 / 1120 / 1130 / 1140 / 1150: Steps

[0055] α: angle

[0056] B-B': vertical plane

[0057] C-C': vertical plane

[0058] D-D': vertical plane

[0059] hd1: horizontal direction

[0060] hd2: horizontal direction DETAILED DESCRIPTION

[0061] The following disclosure provides many embodiments or examples for implementing the different elements provided. Specific examples of each element and its configuration are described below to simplify the illustration of the embodiments of the present invention. Of course, the above are merely examples and are not intended to limit the embodiments of the present invention. For example, if the description mentions that a first element is formed above a second element, it may include an embodiment in which the first and second elements are in direct contact, and it may also include an embodiment in which an additional element is formed between the first and second elements so that they are not in direct contact. In addition, the embodiments of the present invention may repeat reference numbers and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity, and is not intended to indicate the relationship between the different embodiments and / or configurations discussed.

[0062] Furthermore, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and similar terms, may be used to facilitate describing the relationship between one feature or component and another feature or component in the drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation, as well as the orientations depicted in the drawings. When the device is rotated 90 degrees or otherwise, the spatially relative adjectives used herein will be interpreted based on the resulting orientation.

[0063] According to one aspect of the present invention, a photodetector with enhanced light sensitivity at a specific wavelength is provided. A distributed Bragg reflector (DBR) that provides total internal reflection (TIR) ​​at a specific wavelength is formed on one side of the photodetector, which is the side opposite to the side connected to the waveguide in the photodetector. The TIR provided by the DBR can allow the photodetector to absorb more light at the resonant wavelength of the DBR, thereby increasing its light absorption efficiency at the resonant wavelength. In addition, the light reflection geometry of the photodetector of the various embodiments disclosed herein can provide a longer optical path. Therefore, various embodiments can provide a reduction in the length of the photodetector. The reduction in the length of the photodetector can also reduce the dark current (i.e., the background current generated in the absence of incident light) and increase the bandwidth of the photodetector by reducing the capacitance of the photodetector. Various aspects of the embodiments of the present invention are now described with reference to the accompanying drawings.

[0064] refer to Figures 1A to 1D, which illustrates an exemplary structure according to an embodiment of the present invention, which includes a silicon-on-insulator (SOI) substrate, the substrate including a handle substrate 4, a buried insulating layer 6, and a top silicon layer 10L. The top silicon layer 10L may include single crystal silicon and may have a thickness in the range of 200nm to 600nm, although smaller and larger thicknesses may also be used. The top silicon layer 10L may be intrinsic or may include a low atomic concentration of electrical dopants, for example, less than 1.0×10 16 / cm 3 and / or less than 1.0×10 15 / cm 3 and / or less than 1.0×10 14 / cm 3 The buried insulating layer 6 may comprise silicon oxide and may have a thickness in the range of 500 nm to 2000 nm, although smaller and larger thicknesses may also be used.

[0065] A masked ion implantation process may be performed to form buried doped silicon portions 24, 26 and surface doped silicon portions 22, 28. The buried doped silicon portions 24, 26 may include a first p-type doped silicon portion 24 and a first n-type doped silicon portion 26, the first p-type doped silicon portion 24 and the first n-type doped silicon portion 26 being vertically spaced apart from a horizontal plane including the top surface of the top silicon layer 10L. The surface doped silicon portions 22, 28 may include a second p-type doped silicon portion 22 and a second n-type doped silicon portion 28 formed below the top surface of the top silicon layer 10L.

[0066] The first p-type doped silicon portion 24 includes an atomic concentration of 1.0×10 17 / cm 3 to 1.0×10 20 / cm 3 P-type electrical dopants in the range of, for example, 1.0×10 18 / cm 3 to 5.0×10 19 / cm 3 However, smaller and larger atomic concentrations may also be used. The first n-type doped silicon portion 26 includes an atomic concentration of 1.0×10 17 / cm 3 to 1.0×10 20 / cm 3n-type electrical dopants in the range of, for example, 1.0×10 18 / cm 3 to 5.0×10 19 / cm 3 , but smaller and larger atomic concentrations may also be used. The second p-type doped silicon portion 22 includes an atomic concentration of 5.0×10 19 / cm 3 to 2.0×10 21 / cm 3 P-type electrical dopants in the range of, for example, 1.0×10 20 / cm 3 to 1.0×10 21 / cm 3 , but smaller and larger atomic concentrations may also be used. The second n-type doped silicon portion 28 includes an atomic concentration of 5.0×10 19 / cm 3 to 2.0×10 21 / cm 3 n-type electrical dopants in the range of, for example, 1.0×10 20 / cm 3 to 1.0×10 21 / cm 3 , but smaller and larger atomic concentrations can also be used.

[0067] When measured from the top surface of top silicon layer 10L, the depth of first p-type doped silicon portion 24 and first n-type doped silicon portion 26 may be in a range of 10% to 80% of the thickness of top silicon layer 10L, for example, 30% to 50% of the thickness of top silicon layer 10L. The thickness of first p-type doped silicon portion 24 and first n-type doped silicon portion 26 may be in a range of 20% to 80% of the thickness of top silicon layer 10L, for example, 30% to 60% of the thickness of top silicon layer 10L. The bottom surfaces of first p-type doped silicon portion 24 and first n-type doped silicon portion 26 may or may not contact the bottom surface of top silicon layer 10L. Second p-type doped silicon portion 22 may extend vertically from the top surface of top silicon layer 10L to the top surface of first p-type doped silicon portion 24. Second n-type doped silicon portion 28 may extend vertically from the top surface of top silicon layer 10L to the top surface of first n-type doped silicon portion 26.

[0068] In one embodiment, each of the first p-type doped silicon portion 24, the first n-type doped silicon portion 26, the second p-type doped silicon portion 22, and the second n-type doped silicon portion 28 can extend laterally along a first horizontal direction hd1, which is the direction in which the silicon waveguide is subsequently patterned. In one embodiment, the first p-type doped silicon portion 24 and the first n-type doped silicon portion 26 can be laterally separated from each other by a gap that extends laterally along the first horizontal direction hd1 and has a uniform spacing along a second horizontal direction hd2 that is perpendicular to the first horizontal direction hd1. The width of the gap between the first p-type doped silicon portion 24 and the first n-type doped silicon portion 26 is less than the width of the germanium material portion that will be subsequently formed over the first p-type doped silicon portion 24 and the first n-type doped silicon portion 26. For example, the width of the gap between the first p-type doped silicon portion 24 and the first n-type doped silicon portion 26 can be in a range from 50 nm to 300 nm, such as from 80 nm to 200 nm, although smaller and larger widths can also be used. The lengths of the first p-type doped silicon portion 24 and the first n-type doped silicon portion 26 along the first horizontal direction hd1 may be in the range of 10 microns to 100 microns, although smaller and larger lengths may also be used.

[0069] refer to Figure 2A-2D A first photoresist layer (not illustrated) may be applied over the top silicon layer 10L and may be photolithographically patterned to cover the region including the doped silicon portions 22, 24, 26, 28 and to cover laterally protruding strips of the top silicon layer 10L that protrude laterally along the first horizontal direction hd1 from the gap between the first p-type doped silicon portion 24 and the first n-type doped silicon portion 26. A first anisotropic etching process may be performed to etch unmasked portions of the top silicon layer 10L, i.e., portions of the top silicon layer 10L not covered by the patterned portion of the first photoresist layer.

[0070] The duration of the first anisotropic etching process can be selected so that the top surface of the buried insulating layer 6 is physically exposed in the region where the material of the top silicon layer 10L is etched. The remaining portion of the top silicon layer 10L comprises a patterned silicon layer 10, which includes a silicon material matrix 10M and a silicon waveguide 10W that laterally surrounds each of the doped silicon portions 22, 24, 26, 28. Generally, the first p-type doped silicon portion 24 and the first n-type doped silicon portion 26 are embedded within the silicon material matrix 10M. The silicon waveguide 10W is configured to guide photons at a resonant wavelength of a subsequently formed distributed Bragg reflector. In illustrative examples, the resonant wavelength can be any of the commercially used optical communication wavelengths, such as 850 nm, 1250 nm to 1350 nm, 1304 nm, 1309 nm, 1310 nm, 1490 nm, 1550 nm, 1590 nm, or 1625 nm to 1675 nm. The silicon waveguide 10W may include a uniform width region distal from the silicon material substrate 10M and a tapered width region adjacent to the silicon material substrate 10M. The width and horizontal cross-sectional profile of the silicon waveguide 10W may be selected to provide total internal reflection for photons transmitted through the silicon waveguide 10W. The first photoresist layer may then be removed, for example, by ashing. Generally speaking, the combination of the silicon waveguide 10W and the silicon material substrate 10M may be formed by patterning the top silicon layer 10L overlying the buried insulating layer 6.

[0071] A second photoresist layer (not shown) can be applied over patterned silicon layer 10 and photolithographically patterned to form a slit-shaped opening covering the gap between first p-type doped silicon portion 24 and first n-type doped silicon portion 26. The width of the slit-shaped opening can be at least 50 nm greater than the width of the gap along the second horizontal direction hd2, and preferably greater than 100 nm and / or greater than 200 nm. The slit-shaped opening in the second photoresist layer can be formed between the region of second p-type doped silicon portion 22 and the region of second n-type doped silicon portion 28.

[0072] A second anisotropic etching process is performed to etch the portion of the silicon material substrate 10M not shielded by the second photoresist layer, i.e., the portion of the silicon material substrate 10M below the slit-shaped opening in the second photoresist layer. Line trenches having a uniform width can be formed in the upper portion of the silicon material substrate 10M. The duration of the second anisotropic etching process can be selected so that the strip-shaped edge portions of the first p-type doped silicon portion 24 and the first n-type doped silicon portion 26 are physically exposed in the line trenches. Therefore, the depth of the line trenches (measured from a horizontal plane including the top surface of the patterned silicon layer 10) can be greater than the depth of the top surfaces of the first p-type doped silicon portion 24 and the first n-type doped silicon portion 26, and can be less than the depth of the bottom surfaces of the first p-type doped silicon portion 24 and the first n-type doped silicon portion 26. The second photoresist layer can then be removed, for example, by ashing.

[0073] A dielectric fill material, such as silicon oxide, may be deposited in the cavity formed by removing material from the top silicon layer 10L. The cavity includes a field cavity formed adjacent to the silicon waveguide 10W and the line trench, which covers the physically exposed surfaces of the first p-type doped silicon portion 24 and the first n-type doped silicon portion 26, as well as the recessed surface of the silicon material matrix 10M. Excess dielectric fill material may be removed from above the level of the top surface of the patterned silicon layer 10 by performing a planarization process, which may include a chemical mechanical polishing process and / or a recess etching process. In some embodiments, a hard mask layer (not shown) may be formed over the top silicon layer 10L before forming the cavity therein. The hard mask layer may serve as a planarization stop layer during the planarization process and may subsequently selectively remove the material of the patterned silicon layer 10 and the dielectric fill material.

[0074] The remaining portion of the dielectric filling material filling the cavity in the patterned silicon layer 10 constitutes shallow trench isolation structures 12 and 16, which include, for example, a first shallow trench isolation structure 12 in contact with the first p-type doped silicon portion 24 and the first n-type doped silicon portion 26, and also include a second shallow trench isolation structure 16 in contact with the sidewall of the silicon waveguide 10W. The top surfaces of the shallow trench isolation structures 12 and 16 may be coplanar with the top surface of the patterned silicon layer 10.

[0075] Generally speaking, the silicon waveguide 10W can be formed above the buried insulating layer 6 and can extend laterally along a first horizontal direction hd1. A silicon material matrix 10M can abut the ends of the silicon waveguide 10W and embed a first shallow trench isolation structure 12. The first shallow trench isolation structure 12 extends laterally along the first horizontal direction hd1 and is aligned with the ends of the silicon waveguide 10W along a second horizontal direction hd2. A first p-type doped silicon portion 24 and a first n-type doped silicon portion 26 are embedded within the silicon material matrix 10M and contact the bottom surface of the first shallow trench isolation structure 12.

[0076] refer to Figure 3A-3C A dielectric capping material having a uniform thickness may be deposited over the patterned silicon layer 10 and the shallow trench isolation structures 12 and 16 to form a dielectric capping layer 25. In one embodiment, the dielectric capping layer 25 comprises silicon oxide or silicon nitride. The thickness of the dielectric capping layer 25 may be in a range from 30 nm to 300 nm, such as from 60 nm to 150 nm, although smaller and larger thicknesses may also be used.

[0077] refer to Figures 4A-4C A photoresist layer (not shown) may be applied over the dielectric cap layer 25 and may be photolithographically patterned to form an opening over a region of the silicon material substrate 10M adjacent to the first shallow trench isolation structure 12. In this embodiment, the patterned photoresist layer may have straight edges parallel to the second horizontal direction hd2 and cover edge portions of the first shallow trench isolation structure 12. In one embodiment, the straight edges of the photoresist layer may have a lateral extent that is greater than the combined lateral extent of the second p-type doped silicon portion 22 and the second n-type doped silicon portion 28.

[0078] An anisotropic etching process may be performed to etch portions of the silicon material matrix 10M and at least the upper portion of the buried insulating layer 6 not masked by the patterned photoresist layer. A trench, referred to herein as a reflector region trench 49, is formed in the portions of the silicon material matrix 10M and the buried insulating layer 6 not covered by the patterned photoresist layer. The reflector region trench 49 includes straight vertical sidewalls perpendicular to the first horizontal direction hd1. In one embodiment, the straight vertical sidewalls may include vertical surface portions of the first p-type doped silicon portion 24, vertical surface portions of the first n-type doped silicon portion 26, vertical surface portions of the silicon material matrix 10M, and vertical surface segments of the buried insulating layer 6. Furthermore, the vertical surface segments of the second p-type doped silicon portion 22 and second n-type doped silicon portion 28 may also be optically included.

[0079] In general, the depth of the reflector region trench 49 may be greater than the thickness of the silicon material matrix 10M, and may or may not be greater than the sum of the thickness of the silicon material matrix 10M and the thickness of the buried insulating layer 6. If the depth of the reflector region trench 49 is less than the sum of the thickness of the silicon material matrix 10M and the thickness of the buried insulating layer 6, the recessed surface of the buried insulating layer 6 may be the bottom surface of the reflector region trench 49. If the depth of the reflector region trench 49 is greater than the sum of the thickness of the silicon material matrix 10M and the thickness of the buried insulating layer 6, the recessed surface of the handle substrate 4 may be the bottom surface of the reflector region trench 49. In general, the reflector region trench 49 may be formed by removing portions of the silicon material matrix 10M and the buried insulating layer 6.

[0080] refer to Figures 5A-5C , a distributed Bragg reflector (DBR) material layer 40L can be formed over the dielectric cover layer 25 and the sidewalls and bottom surface of the reflector region groove 49. A distributed Bragg reflector (DBR) is an optical device comprising a periodic structure consisting of alternating layers of materials with different refractive indices. These layers are carefully designed to produce constructive interference for light of a specific wavelength (called the resonant wavelength) while providing low reflection or transmission for other wavelengths. DBR can be used to reflect or filter light of a specific wavelength in a controlled and efficient manner. DBR uses constructive interference of light waves. When light of a resonant wavelength passes through the periodic layers of the DBR, the light undergoes multiple reflections at each interface between the layers. The thickness of the layer is designed to guide the reflected waves to constructively interfere align at the resonant wavelength, so that the DBR provides high reflectivity for the resonant wavelength.

[0081] The DBR material layer 40L may include multiple periodic repetitions of a unit layer stack (i.e., N periodic repetitions, where N is greater than 1) of a first material layer 42 and a second material layer 44 on the sidewalls of the groove. The total number of repetitions of the unit layer stack may be in the range of 2 to 30, for example 3 to 10, but a greater number of repetitions may also be used. In the illustrated example, the total number of repetitions is 4. If the instance of the first material layer 42 is the outermost material layer of the DBR material layer 40L, in addition to the multiple periodic repetitions of the unit layer stack, unpaired instances of the first material layer 42 may be provided on opposite sides of the instance of the first material layer 42 serving as the outermost material layer. In other words, the DBR material layer 40L may include two instances of the first material layer 42 as the two outermost material layers. The reflectivity of the DBR depends on the number of periods and the refractive index of the material.

[0082] In one embodiment, the thickness of each instance of the first material layer 42 and each instance of the second material layer 44 can be set to λ / (4n) to achieve high reflectivity of the layer stack including the DBR material layer 40L. In this embodiment, λ is the wavelength in free space, and n is the refractive index of the respective material layer, which can be the first material layer 42 or the second material layer 44. If each first material layer 42 has a first refractive index n1, and if each second material layer 44 has a second refractive index n2, then the first thickness t1 of each first material layer 42 can be given by λ / (4n1), and the second thickness t2 of each second material layer 44 can be given by λ / (4n2).

[0083] In the illustrative example, if the light reflected by the DBR material layer 40L has a wavelength of 1550 nm in a vacuum, and if each instance of the first material layer 42 includes silicon oxide having a first refractive index n1 of 1.444, then the first thickness of each instance of the first material layer 42 can be given by 1550 nm / (4×1.444)=268 nm. If the light to be reflected by the DBR material layer 40L has a wavelength of 1550 nm in a vacuum, and if each instance of the first material layer 42 includes aluminum oxide having a first refractive index n1 of 1.746, then the first thickness of each instance of the first material layer 42 can be given by 1550 nm / (4×1.746)=222 nm. If the light to be reflected by the DBR material layer 40L has a wavelength of 1550 nm in a vacuum, and if each instance of the second material layer 44 includes silicon nitride having a second refractive index n2 of 1.983, the second thickness of each instance of the second material layer 44 can be given by 1550 nm / (4×1.983)=195 nm. If the light to be reflected by the DBR material layer 40L has a wavelength of 1550 nm in a vacuum, and if each instance of the second material layer 44 includes aluminum nitride having a second refractive index n2 of 2.12, the second thickness of each instance of the second material layer 44 can be given by 1550 nm / (4×2.12)=1183 nm.

[0084] In an embodiment where a set of DBR material layers 40L is composed of a pair of first material layers 42 and second material layers 44, the first material layer 42 has a first refractive index n1 and a first thickness given by λ / (4n1), and the second material layer 44 has a second refractive index n2 and a second thickness given by λ / (4n2), the reflectivity R of such a set of DBR material layers 40L for light of vacuum wavelength λ is given by the following formula:

[0085]

[0086] Here, n0 is the refractive index of the material layer located in front of the DBR material layer 40L, and n3 is the refractive index of the material layer located behind the DBR material layer 40L.

[0087] In an embodiment in which a set of DBR material layers 40L includes N repetitions of a pair of a first material layer 42 and a second material layer 44, the first material layer 42 having a first refractive index n1 and a first thickness given by λ / (4n1), the second material layer 44 having a second refractive index n2 and a second thickness given by λ / (4n2), and further includes another instance of the first material layer 42, the reflectivity R of such a set of DBR material layers 40L for light having a vacuum wavelength λ is given by the following formula:

[0088]

[0089] Here, n0 is the refractive index of the material layer located in front of the DBR material layer 40L, and n3 is the refractive index of the material layer located behind the DBR material layer 40L.

[0090] Although the present invention is described using an embodiment in which the reflector region trench 49 has a bottom surface that is a recessed surface of the buried insulating layer 6, embodiments are expressly contemplated herein in which the reflector region trench 49 has a bottom surface that is a recessed surface of the handle substrate 4. In this embodiment, the bottommost layer of the DBR material layer 40L can contact the recessed horizontal surface of the handle substrate 4.

[0091] refer to Figures 6A-6C A filler material having a high refractive index (e.g., polysilicon) may be deposited over the DBR material layer 40L such that the entire volume of the reflector region trench 49 below a horizontal plane including the top surface of the dielectric cap layer 25 is filled with the material of the DBR material layer 40L and the filler material. A planarization process may be performed to remove portions of the DBR material layer 40L and the filler material above a horizontal plane including the top surface of the dielectric cap layer 25. In general, any planarization process may be used to remove portions of the DBR material layer 40L and the filler material above a horizontal plane including the top surface of the dielectric cap layer 25. For example, the planarization process may include a chemical mechanical polishing process and / or a recess etching process.

[0092] The remaining portion of the DBR material layer 40L that fills the reflector region trench 49 constitutes a distributed Bragg reflector (DBR) 40. The remaining portion of the filling material that fills the remaining portion of the reflector region trench 49 constitutes a DBR backing structure 46. In one embodiment, the DBR backing structure 46 may include a high refractive index material, such as polysilicon, having a refractive index of approximately 3.5. In one embodiment, the thickness of the DBR backing structure 46 may be greater than the thickness of the first shallow trench isolation structure 12. The top surfaces of the DBR 40 and the DBR backing structure 46 may be coplanar with the top surface of the dielectric cap layer 25.

[0093] In general, a dielectric cap layer 25 can be formed on a silicon material substrate 10M, and multiple periodic repetitions of a unit layer stack of a first material layer 42 and a second material layer 44 can be formed in the reflector region trench 49 and on the dielectric cap layer 25. Portions of the multiple periodic repetitions of the unit layer stack can be removed from a horizontal plane above the top surface of the dielectric cap layer 25. A distributed Bragg reflector (DBR) 40 can be formed, which includes the remaining portions of the multiple periodic repetitions of the unit layer stack, the unit layer stack including the first material layer 42 and the second material layer 44. The DBR can be formed directly on the sidewalls of the reflector region trench 49. In one embodiment, the vertical interface between the vertically extending portions of the material layers 42 and 44 within the distributed Bragg reflector 40 can be perpendicular to the first horizontal direction hd1.

[0094] refer to Figures 7A-7C A photoresist layer (not shown) may be applied over the dielectric cap layer 25, the DBR 40, and the DBR backing structure 46, and the photoresist layer may be photolithographically patterned into slit-shaped openings extending along a first horizontal direction hd1 over the first shallow trench isolation structure 12. The slit-shaped openings may have triangular lateral protrusions that span the vertical interface between the silicon material substrate 10M and the DBR 40.

[0095] An anisotropic etching process may be performed to etch unmasked portions of the dielectric cap layer 25, the first shallow trench isolation structure 12, and the peripheral portion of the DBR 40 that are not masked by the patterned photoresist layer. In one embodiment, the anisotropic etching process may selectively etch the material of the first shallow trench isolation structure 12 relative to the material of the silicon material matrix 10M until the surfaces of the silicon material matrix 10M, the first type p-doped silicon portion 24, and the first type n-doped silicon portion 26 are exposed. A laterally extending cavity 69 may be formed in the volume where the material of the dielectric cap layer 25, the first shallow trench isolation structure 12, and the peripheral portion of the DBR 40 are etched. Optionally, the anisotropic etching process may include an overetching step that vertically extends the laterally extending cavity 69.

[0096] The laterally extending cavity 69 will be referred to as Figures 2A-2D The first shallow trench isolation structure 12 formed in the described process steps is divided into two discontinuous first shallow trench isolation structures 12, which are laterally spaced apart by a uniform spacing along the second horizontal direction hd2, which is the width of the laterally extending cavity 69. The laterally extending cavity 69 can be formed between the silicon waveguide 10W and the distributed Bragg reflector 40, such that the sidewalls of the distributed Bragg reflector 40 are exposed to the laterally extending cavity 69, and the silicon waveguide 10W is laterally spaced apart from the laterally extending cavity 69 by the remaining portion of the silicon material substrate 10M.

[0097] In one embodiment, the laterally extending cavity 69 extends laterally along a first horizontal direction hd1 and has end walls aligned with the silicon waveguide 10W. The lateral thickness of the portion of the silicon material matrix 10M remaining between the laterally extending cavity 69 and the silicon waveguide 10W along the first horizontal direction hd1 can be in a range of 30 nm to 600 nm, for example, 60 nm to 300 nm, although smaller and larger lateral thicknesses can also be used. In other words, the distance between the silicon waveguide 10W and the end walls of the laterally extending cavity 69 can be in a range of 30 nm to 600 nm, for example, 60 nm to 300 nm, although smaller and larger distances are also possible.

[0098] In one embodiment, the width of the laterally extending cavity 69 along the second horizontal direction hd2 may be the same as or substantially the same as the width of the most proximal portion of the silicon waveguide 10W. The strip-shaped horizontal surface portion of the first p-type doped silicon portion 24, the strip-shaped horizontal surface portion of the first n-type doped silicon portion 26, and the strip-shaped horizontal surface portion of the silicon material matrix 10M may be physically exposed at the bottom of the laterally extending cavity 69.

[0099] According to an embodiment of the present invention, the laterally extending cavity 69 may include a notched end portion that cuts through an instance of the first material layer 42. In one embodiment, the notched end portion has a triangular horizontal cross-sectional shape. The lateral dimension of the triangular horizontal cross-sectional shape of the notched end portion of the laterally extending cavity along the first horizontal direction hd1 may be the same as the thickness of the first material layer 42 in the DBR 40. Specifically, the two-sided triangular shape may be tilted at respective angles within a range of 40 to 50 degrees (e.g., 45 degrees) relative to the first horizontal direction hd1 and may have a lateral dimension along the first horizontal direction hd1 that is equal to the thickness of the nearest first material layer 42 in the DBR 40. Furthermore, the total lateral length of the two sides of the triangle along the second horizontal direction hd2 may be equal to the spacing between the two first shallow trench isolation structures 12, i.e., the width of the uniform-width portion of the laterally extending cavity 69. In one embodiment, the laterally extending cavity 69 includes an inclined protrusion that protrudes laterally into the distributed Bragg reflector 40 such that two inclined vertical sidewalls of the laterally extending cavity 69 include a sidewall of the nearest first material layer 42 and abut each other at an angle α in a range of 80 to 100 degrees in plan view. Each inclined vertical sidewall of the laterally extending cavity 69 may include an inclined vertical sidewall of the nearest first material layer 42 and may extend laterally from an interface between the nearest first material layer 42 and the silicon material substrate 10M to an interface between the nearest first material layer 42 and the nearest second material layer 44.

[0100] refer to Figures 8A-8D In embodiments where the DBR backing structure 46 comprises a semiconductor material such as polysilicon, a surface oxidation process may be performed to convert the physically exposed surface portion of the DBR backing structure 46 into a dielectric liner 48, which may comprise a silicon oxide liner. The physically exposed surface portion of the silicon material substrate 10M at the bottom of the laterally extending cavity 69 may be converted into a sacrificial silicon oxide liner (not shown). A photoresist layer (not shown) may be applied over the dielectric cap layer 25, the DBR 40, and the dielectric liner 48, and may be photolithographically patterned to remove portions of the photoresist layer from within and above the laterally extending cavity 69 while covering the dielectric liner 48. An isotropic etching process for etching silicon oxide may be performed to remove the sacrificial silicon oxide liner from beneath the laterally extending cavity 69. If the DBR backing structure 46 comprises a dielectric material, the step of forming the dielectric liner 48 may be omitted.

[0101] A selective germanium deposition process may be performed to grow a germanium material portion 62 from the substantially exposed surfaces of the silicon material substrate 10M, the first p-type doped silicon portion 24, and the first n-type doped silicon portion 26. In one embodiment, the selective germanium deposition process may include a selective germanium epitaxy process. The selective germanium deposition process may grow germanium from the substantially exposed semiconductor surfaces while suppressing germanium growth from dielectric surfaces. For example, a germanium precursor gas such as germanium ethane or digermane may be flowed simultaneously or alternately with an etchant gas such as gaseous hydrogen chloride. The growth rate of germanium from the semiconductor surfaces is greater than the growth rate of germanium from the dielectric surfaces. The step of selectively growing germanium only from the semiconductor surfaces may be achieved by setting the flow rate of the etchant gas such that the etchant gas has an etching rate greater than the growth rate of germanium from the dielectric surfaces and less than the growth rate of germanium from the semiconductor surfaces. Thus, germanium may grow only from the substantially exposed surfaces of the silicon material substrate 10M, the first p-type doped silicon portion 24, and the first n-type doped silicon portion 26.

[0102] A germanium material portion 62 can be formed in the laterally extending cavity 69. The germanium material portion 62 can be grown from and formed in the peripheral region of the first p-type doped silicon portion 24 and the peripheral portion of the first n-type doped silicon portion 26. In one embodiment, the duration of the selective germanium deposition process can be selected such that the horizontal top surface of the germanium material portion 62 is formed above a horizontal plane including the bottom surface of the dielectric cap layer 25 and below a horizontal plane including the top surface of the dielectric cap layer 25. In this embodiment, the horizontal top surface of the germanium material portion 62 contacts the sidewalls of the dielectric cap layer 25. In one embodiment, the first material layer 42 and the second material layer 44 in the distributed Bragg reflector 40 have corresponding flat top surfaces in a horizontal plane covering the horizontal top surface of the germanium material portion 62.

[0103] Subsequently, a silicon capping layer 64 can be formed by performing a selective silicon deposition process, such as a selective silicon epitaxial process. The silicon capping layer 64 can be grown from the physically exposed top surface of the germanium material portion 62 and can be formed thereon. In one embodiment, the duration of the selective silicon deposition process can be selected such that the top surface of the silicon capping layer 64 is formed above a horizontal plane including the top surface of the dielectric capping layer 25. In this embodiment, a vertical surface of the silicon capping layer 64 contacts the sidewalls of the dielectric capping layer 25. In one embodiment, each instance of the first material layer 42 and the second material layer 44 in the distributed Bragg reflector 40 has a corresponding flat top surface in a horizontal plane below the horizontal top surface of the silicon capping layer 64.

[0104] Photodiodes 24, 62, and 26 may be formed to include a germanium material portion 62 extending laterally along a first horizontal direction hd1, a p-type doped silicon portion 24, and an n-type doped silicon portion 26. In one embodiment, the germanium material portion 62 includes an inclined protrusion 62P that protrudes laterally into a distributed Bragg reflector (DBR) 40 having a triangular horizontal cross-sectional shape, such that two interfaces between the inclined protrusion and the distributed Bragg reflector 40 abut each other at an angle α in a range of 80 to 100 degrees in a plan view.

[0105] The tilt angle of the perpendicular interface between the germanium material portion within the DBR 40 and the nearest first material layer 42 can be advantageously used to increase the probability that a photon propagating through a series of secondary reflections of the germanium material portion 62 will experience two consecutive reflections at two perpendicular interfaces, so that the photon propagates through the germanium material portion 62 in opposite directions after the two consecutive reflections. This geometry increases the probability that the photodetector of the present invention absorbs the photon. Therefore, the photodetector of the present invention can increase the probability of photon capture through the combination of the geometric structure of the DBR 40 and the dual tilted perpendicular interface between the germanium material portion 62 and the DBR.

[0106] In one embodiment, the lateral length of the inclined protrusion 62P along the first horizontal direction hd1 is the same as the thickness of the instance of the first material layer 42 contacting the germanium material portion 62. In one embodiment, each of the two interfaces lies within a respective flat vertical plane and is adjacent to a respective lengthwise sidewall of the germanium material portion 62 extending laterally along the first horizontal direction hd1.

[0107] In one embodiment, the germanium material portion 62 has a uniform width along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1 between the pair of first shallow trench isolation structures 12. In one embodiment, the two first shallow trench isolation structures 12 can be laterally spaced apart from each other by the germanium material portion 62. Each of the two first shallow trench isolation structures 12 contacts a corresponding longitudinal sidewall of the germanium material portion 62.

[0108] The silicon substrate 10M may embed two first shallow trench isolation structures 12, a germanium portion 62, a first p-type doped silicon portion 24, and a first n-type doped silicon portion 26. In one embodiment, an end surface of the germanium portion 62 perpendicular to the first horizontal direction hd1 contacts the silicon substrate 10M.

[0109] In one embodiment, the first p-type doped silicon portion 24 and the first n-type doped silicon portion 26 are laterally spaced apart from each other at a uniform lateral spacing along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1, and the uniform lateral spacing is less than the width of the germanium material portion 62 along the second horizontal direction hd2.

[0110] The first p-type doped silicon portion 24 and the first n-type doped silicon portion 26 are embedded in the silicon material matrix 10M and contact the germanium material portion 62. In one embodiment, the bottom surface of the germanium material portion 62 includes: a central surface segment 10M contacting the silicon material matrix; a first peripheral surface segment contacting the first p-type doped silicon portion 24; and a second peripheral surface segment contacting the first n-type doped silicon portion 26.

[0111] In an embodiment, each of first p-type doped silicon portion 24 and first n-type doped silicon portion 26 contacts a respective bottom surface segment of germanium material portion 62 and a segment of a respective longitudinal sidewall of germanium material portion 62 .

[0112] The silicon waveguide 10W may be positioned above the buried insulating layer 6 and may extend laterally along a first horizontal direction hd1. A silicon material matrix 10M may abut an end of the silicon waveguide 10W and may embed a germanium material portion 62 that extends laterally along the first horizontal direction hd1 and is aligned with the end of the silicon waveguide 10W. The distributed Bragg reflector 40 includes multiple periodic repetitions of a unit layer stack, each including a first material layer 42 and a second material layer 44. The interface between the vertically extending portions of the material layers 42 and 44 within the distributed Bragg reflector 40 is perpendicular to the first horizontal direction hd1. The distributed Bragg reflector 40 contacts the germanium material portion 62.

[0113] refer to Figures 9A-9C A dielectric cap layer 66 may be formed over dielectric cap layer 25, silicon cap layer 64, and DBR 40. Dielectric cap layer 66 may include silicon oxide or silicon nitride and may have a thickness in the range of 100 nm to 400 nm, although lesser and greater thicknesses may also be used.

[0114] A contact-level dielectric layer 80 may be deposited over the dielectric cap layer 66. The contact-level dielectric layer 80 comprises an interlayer dielectric (ILD) material, such as undoped silicate glass, doped silicate glass, or organosilicate glass, and may have a thickness in the range of 200 nm to 800 nm, although lesser and greater thicknesses may also be used. Contact via structures 82, 88 may be formed through the contact-level dielectric layer 80, the dielectric cap layer 66, and the dielectric cap layer 25. The contact via structures 82, 88 may include a first contact via structure 82 contacting the second p-type doped silicon portion 22 and a second contact via structure 88 contacting the second n-type doped silicon portion 28.

[0115] refer to Figure 10 , which illustrates an alternative configuration of an exemplary structure, which includes a DBR 40 that extends vertically through the silicon material matrix 10M, the buried insulating layer 6 and the upper portion of the handle substrate 4 and contacts the recessed horizontal surface of the handle substrate 4.

[0116] refer to Figure 11 , the process flow diagram illustrates an exemplary process sequence for forming a semiconductor structure according to an embodiment of the present invention.

[0117] Refer to steps 1110 and Figures 1A-2D , a combination of a silicon waveguide 10W and a silicon material matrix 10M can be formed by patterning a silicon layer (eg, a top silicon layer 10L) covering the buried insulating layer 6 .

[0118] Refer to step 1120 and Figures 3A-4C and Figure 10 , a trench (eg, a reflector region trench 49 ) may be formed by removing portions of the silicon material base 10M and the buried insulating layer 6 .

[0119] Refer to step 1130 and Figures 5A-6C and Figure 10 A distributed Bragg reflector 40 may be formed on the sidewalls of a trench (such as the reflector region trench 49 ), the distributed Bragg reflector 40 including multiple periodic repetitions of a unit layer stack including a first material layer 42 and a second material layer 44 .

[0120] Refer to step 1140 and Figures 7A-7C and Figure 10A laterally extending cavity 69 may be formed between the silicon waveguide 10W and the distributed Bragg reflector 40 . At least one sidewall (eg, a pair of vertical sidewalls) of the distributed Bragg reflector 40 is exposed to the laterally extending cavity 69 .

[0121] Refer to steps 1150 and Figures 8A-8D 、 Figures 9A-9C and Figure 10 , a germanium material portion 62 may be formed in the laterally extending cavity 69. The germanium material portion 62 may be a component of the photodiodes 24, 62, 26.

[0122] With reference to all the accompanying drawings and in accordance with various embodiments of the present invention, a semiconductor device is provided, comprising: a photodiode 24, 62, 26, comprising a germanium material portion 62, a p-type doped silicon portion 24, and an n-type doped silicon portion 26 extending laterally along a first horizontal direction hd1; and a distributed Bragg reflector 40, comprising a plurality of periodic repetitions of a unit layer stack, the unit layer stack comprising a first material layer 42 and a second material layer 44, wherein an interface between vertically extending portions of the material layers 42, 44 within the distributed Bragg reflector 40 is perpendicular to the first horizontal direction hd1, and wherein the distributed Bragg reflector 40 contacts the germanium material portion 62.

[0123] In one embodiment, the germanium material portion 62 includes an angled protrusion 62P that protrudes laterally into the distributed Bragg reflector 40, such that two interfaces between the angled protrusion and the distributed Bragg reflector 40 abut each other at an angle α in a range of 80 to 100 degrees in plan view. In one embodiment, the lateral length of the angled protrusion 62P along the first horizontal direction hd1 is the same as the thickness of the instance of the first material layer 42 that contacts the germanium material portion 62. In one embodiment, each of the two interfaces lies within a corresponding flat vertical plane and abuts a corresponding longitudinal sidewall of the germanium material portion 62 that extends laterally along the first horizontal direction hd1.

[0124] In one embodiment, the germanium material portion 62 has a uniform width along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. In one embodiment, the semiconductor device includes two shallow trench isolation structures (e.g., two first shallow trench isolation structures 12) laterally spaced apart from each other by the germanium material portion 62, wherein each of the two shallow trench isolation structures (e.g., two first shallow trench isolation structures 12) contacts a corresponding longitudinal sidewall of the germanium material portion 62.

[0125] In one embodiment, a semiconductor device includes a silicon material body 10M embedded with two shallow trench isolation structures (e.g., two first shallow trench isolation structures 12), a germanium material portion 62, a first p-type doped silicon portion 24, and a first n-type doped silicon portion 26. In one embodiment, an end surface of the germanium material portion 62 perpendicular to the first horizontal direction hd1 contacts the silicon material body 10M.

[0126] In one embodiment, first p-type doped silicon portion 24 and first n-type doped silicon portion 26 are laterally spaced apart from each other at a uniform lateral spacing along a second horizontal direction hd2 that is perpendicular to first horizontal direction hd1, and the uniform lateral spacing is less than a width along second horizontal direction hd2 of germanium material portion 62. In one embodiment, each of first p-type doped silicon portion 24 and first n-type doped silicon portion 26 contacts a corresponding bottom surface segment of germanium material portion 62 and a segment of a corresponding longitudinal sidewall of germanium material portion 62.

[0127] According to another aspect of the present invention, a semiconductor device is provided, comprising: a silicon waveguide 10W, located above a buried insulating layer and extending laterally along a first horizontal direction hd1; a silicon material substrate 10M, adjacent to an end of the silicon waveguide 10W and embedded with a germanium material portion 62 extending laterally along the first horizontal direction hd1 and aligned with the end of the silicon waveguide 10W; and a distributed Bragg reflector 40, comprising a plurality of periodic repetitions of a unit layer stack, the unit layer stack comprising a first material layer 42 and a second material layer 44, wherein an interface between vertically extending portions of the material layers 42 and 44 within the distributed Bragg reflector 40 is perpendicular to the first horizontal direction hd1, and wherein the distributed Bragg reflector 40 contacts the germanium material portion 62.

[0128] In one embodiment, the semiconductor structure includes a p-type doped silicon portion 24 and an n-type doped silicon portion 26 embedded in a silicon material matrix 10M and contacting a germanium material portion 62. In one embodiment, a bottom surface of the germanium material portion 62 includes: a central surface segment contacting the silicon material matrix 10M; a first peripheral surface segment contacting the first p-type doped silicon portion 24; and a second peripheral surface segment contacting the first n-type doped silicon portion 26.

[0129] In one embodiment, the germanium material portion 62 includes an inclined protrusion 62P that laterally protrudes into the distributed Bragg reflector 40 having a triangular horizontal cross-sectional shape. In one embodiment, the semiconductor structure includes a dielectric cap layer 25 covering a silicon material base 10M. The horizontal top surface of the germanium material portion 62 contacts the sidewalls of the dielectric cap layer 25; and each instance of the first material layer 42 and the second material layer 44 in the distributed Bragg reflector 40 has a corresponding flat top surface in a horizontal plane covering the horizontal top surface of the germanium material portion 62.

[0130] Various embodiments of the present invention can be used to provide a photodetector with high detection efficiency, low dark current, and high bandwidth. Furthermore, due to the reflective geometry provided by DBR 40 and the dual-reflection geometry of a pair of perpendicular interfaces between the DBR's germanium material portion 62 and the nearest first material layer 42, the lateral length of the photodetector of the present invention can be shortened along the length of the germanium material portion 62.

[0131] The components of several embodiments are summarized above so that those skilled in the art can more easily understand the viewpoints of the embodiments of the present invention. Each embodiment described using the term "comprising" also naturally discloses an embodiment in which the term "comprising" is replaced by "substantially consisting of..." or with the term "consisting of...", unless otherwise specifically disclosed herein. Whenever two or more components are listed as alternatives in the same paragraph or in different paragraphs, a Markush group comprising two or more components as a list is also implicitly disclosed. Whenever the auxiliary verb "may" is used in the present invention to describe the formation of an element or the execution of a process step, an embodiment in which such an element or such process step is not performed is also explicitly envisioned, as long as the resulting device or apparatus can provide equivalent results. Therefore, whenever the formation of such a component or such process step is omitted, the auxiliary verb "may" applied to the formation of the component or the execution of the process step should also be interpreted as "may" or "may, or may not", as long as the process step can provide the same result or an equivalent result, and an equivalent result includes a slightly better result and a slightly worse result. Those skilled in the art will appreciate that they can design or modify other processes and structures based on the embodiments of the present invention to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art will also appreciate that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and that they can make various changes, substitutions, and replacements without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: a photodiode comprising a germanium material portion, a p-type doped silicon portion, and an n-type doped silicon portion extending laterally along a first horizontal direction; as well as A distributed Bragg reflector (DBR) comprises a plurality of periodic repetitions of a unit layer stack, the unit layer stack comprising a first material layer and a second material layer, wherein a plurality of interfaces between a plurality of vertically extending portions of the material layers within the DBR are perpendicular to the first horizontal direction, and wherein the DBR contacts the germanium material portion.

2. The semiconductor device according to claim 1, wherein The germanium material portion includes an inclined protrusion that protrudes laterally into the DBR such that, in a plan view, two interfaces between the inclined protrusion and the DBR abut each other at an angle between 80 degrees and 100 degrees.

3. The semiconductor device according to claim 2, wherein A transverse length of the inclined protruding portion along the first horizontal direction is the same as a thickness of a portion of the first material layer contacting the germanium material.

4. The semiconductor device according to claim 2, wherein Each of the two interfaces is located in a corresponding flat vertical plane and is adjacent to a corresponding longitudinal sidewall of the germanium material portion extending laterally along the first horizontal direction.

5. The semiconductor device according to claim 1, wherein The germanium material portion has a uniform width along a second horizontal direction perpendicular to the first horizontal direction.

6. The semiconductor device according to claim 1 or 2, wherein: Also included are two shallow trench isolation structures laterally spaced apart from each other through the germanium material portion, wherein each of the shallow trench isolation structures contacts a corresponding longitudinal sidewall of the germanium material portion.

7. A semiconductor device, characterized in that: include: a silicon waveguide located above a buried insulating layer and extending laterally along a first horizontal direction; a silicon material substrate adjacent to an end portion of the silicon waveguide and embedded with a germanium material portion, the germanium material portion extending laterally along the first horizontal direction and aligned with the end portion of the silicon waveguide; as well as A distributed Bragg reflector (DBR) comprises a plurality of periodic repetitions of a unit layer stack, the unit layer stack comprising a first material layer and a second material layer, wherein interfaces between vertically extending portions of the plurality of material layers within the DBR are perpendicular to the first horizontal direction, and wherein the DBR contacts the germanium material portion.

8. The semiconductor device according to claim 7, wherein The invention also includes a p-type doped silicon portion and an n-type doped silicon portion embedded in the silicon material matrix and contacting the germanium material portion.

9. The semiconductor device according to claim 7, wherein The germanium material portion includes an inclined protruding portion that protrudes laterally into the distributed Bragg reflector having a triangular horizontal cross-sectional shape.

10. The semiconductor device according to claim 7, wherein Also included is a dielectric cap layer covering the silicon material substrate, wherein: A top surface of the germanium material portion contacts a sidewall of the dielectric cap layer; and Each of the first material layer and the second material layer in the distributed Bragg reflector has a corresponding flat top surface in a horizontal plane covering a top surface of the germanium material portion.

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