Fully symmetrical low-imbalance vertical Hall device

Abstract

The utility model provides a completely symmetrical low-offset vertical Hall device, which comprises two thin waist type five-contact hole vertical Hall devices which are in anti-phase parallel coupling connection, the thin waist type five-contact hole vertical Hall device comprises a P-type substrate layer, an N well layer, a P well layer, an N-type heavily doped region and a P-type heavily doped region, the N-well layer is arranged above the interior of the P-type substrate layer, and the periphery of the N-well layer is wrapped by the P-well layer; the five N-type heavily doped regions and the four P-type heavily doped regions are alternately arranged above the interior of the N well layer; the P well layer is annular, and the annular interior is of a structure with a small middle part and two large sides and is used for limiting the N well layer, the N-type heavily doped region and the P-type heavily doped region, so that a thin waist type structure is formed; the N-type heavily doped region is used as a contact hole of the device; the anti-phase parallel coupling connection is that the contact holes of the two identical thin waist type five-contact hole vertical Hall devices are connected in an anti-phase manner through metal wires.

Description

Technical Field

[0001] The utility model relates to the technical field of vertical Hall devices, in particular to a completely symmetrical low-offset vertical Hall device. Background Art

[0002] As the requirements for magnetic field detection become increasingly stringent, Hall sensors are required to be able to detect magnetic fields in all directions and realize the detection of three-dimensional magnetic fields. Hall devices can be divided into horizontal and vertical types according to the direction of the detected magnetic field. Horizontal Hall devices are used to detect magnetic fields perpendicular to the sensor surface, while vertical Hall devices are used to detect magnetic fields parallel to the sensor surface. Usually, the two can be combined to form a monolithic integrated three-dimensional Hall magnetic sensor, thereby realizing the detection of three-dimensional magnetic fields in space. However, due to the structure and process of the device itself, the sensitivity of the vertical Hall device is low and the offset is large. In comparison, its performance is far inferior to that of the horizontal Hall device. Therefore, its performance is often difficult to match that of the horizontal Hall device, which seriously limits the overall performance and application areas of the three-dimensional Hall device.

[0003] In recent years, various vertical Hall devices with five-contact holes, four-contact holes, six-contact holes, and dual-three-contact holes have been proposed. However, these devices all suffer from large initial offset or low sensitivity. Compared to other device structures, the five-contact hole vertical Hall device not only has a relatively low initial offset voltage but also has higher Hall sensitivity than other device structures. However, because its structure lacks four-fold rotational symmetry, it still has a large residual offset voltage even when using four-phase rotating current technology. Utility Model Content

[0004] In order to overcome the defects and shortcomings of the existing technology, the present invention aims to propose a completely symmetrical low-offset vertical Hall device, which is composed of two identical thin-waisted five-contact hole vertical Hall devices connected in anti-parallel coupling. Compared with the existing five-contact hole vertical Hall device, the thin-waisted five-contact hole vertical Hall device can effectively reduce the impact of the depletion layer asymmetry caused by the junction field effect on the initial offset, and thus has a lower initial offset and higher sensitivity. The disadvantage is that the device is not completely symmetrical, the offset has a strong nonlinearity, and the offset cannot be eliminated by the existing offset elimination technology. Therefore, in order to solve the shortcomings of a single thin-waisted five-contact hole vertical Hall device, the present invention connects two thin-waisted five-contact hole vertical Hall devices in an anti-parallel coupling manner, so that the overall structure of the device has good rotational symmetry, which not only effectively further reduces the initial offset voltage of the device, but also is better compatible with the four-phase rotating current technology, with lower residual offset and higher Hall sensitivity.

[0005] The utility model specifically adopts the following technical solutions:

[0006] A fully symmetrical low-offset vertical Hall device comprises two anti-parallel coupled thin-waisted five-contact hole vertical Hall devices; the thin-waisted five-contact hole vertical Hall device comprises a P-type substrate layer, an N-well layer, a P-well layer, an N-type heavily doped region, and a P-type heavily doped region; the N-well layer is disposed above the interior of the P-type substrate layer and is surrounded by the P-well layer; five N-type heavily doped regions and four P-type heavily doped regions are alternately arranged above the interior of the N-well layer; the P-well layer is annular, with the interior of the annular ring having a small middle and large sides, for confining the N-well layer, the N-type and P-type heavily doped regions, thereby forming a thin-waisted structure; the N-type heavily doped regions serve as contact holes of the device; the anti-parallel coupling connection comprises: connecting the contact holes of two identical thin-waisted five-contact hole vertical Hall devices in anti-phase via metal wires.

[0007] Furthermore, the N-type heavily doped regions and the P-type heavily doped regions are alternately arranged at equal intervals; the five N-type heavily doped regions have the same shape and size, and the four P-type heavily doped regions have the same shape and size.

[0008] Among them, the N-type heavily doped region serves as the active region of the device, and the contact hole of the device is formed by connecting the metal, while the P-type heavily doped region plays an isolation role;

[0009] In terms of manufacturing process, as an optimal known solution, the five N-type heavily doped regions can be formed by injecting five N-type heavily doped regions of the same size into the N-well layer, and the four P-type heavily doped regions can be formed by injecting a total of four P-type heavily doped regions of the same size at equal intervals among the five N-type heavily doped regions.

[0010] The P-well layer surrounds the N-well layer to form a P-well layer ring. The utility model limits the effective width of the device active area and contact hole by specially designing the shape of the inner side of the P-well ring, so that the active area and contact hole inside the device present a thin waist structure with a small middle and large sides.

[0011] Furthermore, a contact electrode is provided on each of the N-type heavily doped regions; and an electrode for grounding is provided on each of the P-type heavily doped regions.

[0012] Furthermore, among the five contact electrodes, the first and last two contact electrodes are connected to form one contact electrode. Among the four electrodes thus formed, two electrodes serve as bias terminals of the Hall device, and the other two electrodes serve as Hall effect sensing terminals.

[0013] Among the five contact electrodes, the first and last two contact electrodes are connected to form one contact electrode. Among the four electrodes thus formed, two electrodes serve as bias terminals of the Hall device, and the other two electrodes serve as Hall effect sensing terminals.

[0014] The material of the above electrodes is generally metal, which can be prepared by deposition.

[0015] The inverted connection referred to in the present invention is a connection method opposite to the orthogonal coupling commonly used in the prior art described in the specific embodiments below. For reference, its basic implementation method can be found in the appendix of the specification. Figure 8 , the first contact hole and the fifth contact hole of device 1 and device 2 are connected to each other as the contact hole C1 of the device; then C1 of device 1 and C3 of device 2 are connected to each other, C2 of device 1 and C4 of device 2 are connected to each other, C3 of device 1 and C1 of device 2 are connected to each other, and C4 of device 1 and C2 of device 2 are connected to each other.

[0016] Furthermore, the thin waist structure is a symmetrical stepped structure.

[0017] In the structural solution of the present invention, the P-well layer surrounds the N-well layer from the outside to form a P-well ring, thereby determining the specific shape of the thin-waist structure.

[0018] As a preparation reference, the shape and opening of the P-well layer are controlled by the shape of the mask in the process flow. Therefore, during the preparation process, the shape of the mask can be adjusted according to the actual application. This is common knowledge in the semiconductor field.

[0019] In the solution of the present invention, the depths of the P-type substrate layer, the N-well layer, the P-well layer, the N-type heavily doped region, and the P-type heavily doped region are determined by the manufacturing process and are not particularly limited.

[0020] For the doping concentrations of the N-well layer, P-well layer, N-type heavily doped region, and P-type heavily doped region: a clear relationship is: P-type heavily doped region > N-type heavily doped region > P-well layer > N-well layer; when the layers overlap with each other, the region to which they belong is determined by the one with higher doping concentration, and the doping process can adopt the existing conventional process.

[0021] More specifically, in a typical fabrication process, an N-well region is first formed by implantation in a P-type substrate according to a mask. Then, heavily N- and P-type doped layers are implanted into the N-well according to a mask. The N- and P-type heavily doped regions are implanted to a depth of approximately 0.25μm within the N-well (depending on the process). Further implantation through a mask forms the P-well. Because the P-well concentration is greater than the N-well concentration, the portion of the N-well covered by the P-well is replaced by the P-well. However, because the N- and P-type heavily doped regions are implanted at higher concentrations than the P-well, even though covered by the P-well, the N- and P-type heavily doped regions remain intact. These layers are flush on the surface, but their depths vary within the internal regions, determined by the manufacturing process. Therefore, in a narrow-waisted structure, the P-well primarily controls the shape of the N-well active area. The N- and P-type heavily doped regions are effective only within the N-well active area. The N- and P-type heavily doped layers in the N-well portion replaced by the P-well do not function. In other words, only the N and P type doped layers inside the N well are effective, and the N and P type doped layers inside the P well are invalid, so the P well directly limits the internal shape of the N well and indirectly limits the effective width of the N and P type heavily doped layers.

[0022] Compared with the prior art, the present invention and its preferred embodiment have the following outstanding features and beneficial effects:

[0023] 1. The dimensions of the N-well layer and the N-type heavily doped region within the thin-waisted five-contact vertical Hall device structure are modulated by the P-well layer ring, forming a stepped shape with a small opening in the middle and a large opening on the outside. This effectively reduces the influence of the device's junction field effect on device offset, resulting in a lower initial offset voltage and higher Hall sensitivity.

[0024] 2. By coupling two thin-waisted five-contact vertical Hall devices in reverse parallel, this method makes the device structure completely symmetrical, further reducing the initial offset of the device; at the same time, the current flow path of the device under the four rotating current phases is also completely symmetrical, which is well compatible with the rotating current technology for offset elimination; in addition, the device's offset and Hall voltage have good linearity in the four phases, which is conducive to the back-end Hall signal processing circuit to better suppress the offset and amplify the Hall signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0026] Figure 1 This is a plan view of the first embodiment of the thin-waisted five-contact hole vertical Hall device of the present invention.

[0027] Figure 2This is a horizontal cross-section of the first embodiment of the thin-waisted five-contact hole vertical Hall device of the present invention.

[0028] Figure 3 Among them, (a), (b), and (c) are cross-sectional views at dashed lines 1, 2, and 3 of the first embodiment of the thin-waisted five-contact vertical Hall device of the present invention, respectively.

[0029] Figure 4 A depletion layer diagram of the thin-waisted five-contact hole vertical Hall device under four-phase rotating current phases of the utility model.

[0030] Figure 5 A plan view of a second embodiment of a thin-waisted five-contact hole vertical Hall device according to the present invention.

[0031] Figure 6 A plan view of a third embodiment of a thin-waisted five-contact hole vertical Hall device according to the present invention.

[0032] Figure 7 A schematic diagram of the utility model showing a thin waisted five-contact hole vertical Hall device adopting an existing orthogonal coupling connection method.

[0033] Figure 8 This is a structural diagram of a fully symmetrical low-offset vertical Hall device according to an embodiment of the present utility model.

[0034] Figure 9 This is a current flow diagram of a four-phase rotating current technology for a fully symmetrical low-offset vertical Hall device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0035] In order to make the features and advantages of the present invention more clearly understood, the following embodiments are specifically described in detail with reference to the accompanying drawings:

[0036] It should be noted that the following detailed descriptions are exemplary and are intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the present application belongs.

[0037] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, they indicate the presence of features, steps, operations, devices, components and / or combinations thereof.

[0038] like Figures 1-9As shown, the utility model provides a completely symmetrical low-offset vertical Hall device structure, which includes two anti-phase parallel coupled thin-waist five-contact hole vertical Hall devices.

[0039] like Figure 1 、 2 The figure shows a plan view of the first embodiment of the thin-waisted five-contact hole vertical Hall device of the present invention. The N-type heavily doped region in the figure is represented as the N+ layer, the P-type heavily doped region is represented as the P+ layer, the P-type substrate layer is represented as the P-sub, and the N-well layer and the P-well layer are represented as the N-well and P-well layers, respectively. In the first embodiment, the thin-waisted five-contact hole vertical Hall device includes a P-type substrate layer, an N-well layer, a P-type heavily doped region, an N-type heavily doped region, and a P-well layer. An independent N-well layer is set inside a P-sub layer in the existing CMOS process as the active area of ​​the Hall device; the plan view of the N-well layer is a rectangular shape, and the depth is determined by the CMOS process. Five equally spaced N+ layers are implanted onto the N-well layer, arranged symmetrically around the center. Metal electrodes are placed over the N+ layers to form contact holes (metal lines not shown in the figure). P+ layers are placed between the N+ layers, also arranged symmetrically around the center. The P+ layers primarily prevent short circuits between the N+ layers, helping to improve device sensitivity. The N-well layer surrounds the P-well layer, forming a ring. The shape of the P-well ring can be customized with custom mask shapes. In existing CMOS processes, the P-well layer is typically deeper than the N-well layer and has a higher doping concentration than the N-well layer. Therefore, the N-well layer covered by the P-well layer can be considered replaced by the P-well layer. The P-well layer effectively limits the device's active area and contact hole width, while also isolating the device from other external devices. Figure 1 In the first embodiment, by changing the shape of the P-well layer ring inside the device, the vertical dimensions of the active area and contact holes inside the device are small in the middle and large on both sides, which is the so-called thin waist structure. Figure 3 As shown, Figure 3 (a), (b), and (c) correspond to Figure 1 The cross-sections at the dotted lines 1, 2, and 3 show more intuitively how the P-well effectively limits the effective width of the device active area and contact hole, making the width of the active area and contact hole in the center of the device smaller than that on both sides, namely the corresponding N-well layer, N+ layer, and P+ layer.

[0040] The advantage of the above structure is that it weakens the influence of the junction field effect of the existing five-contact vertical Hall device on the device offset and sensitivity, which can be seen from the four-phase rotating current technology, such as Figure 4 Figure 2 shows the depletion layer caused by the junction field effect at four different bias phases for a five-contact vertical Hall device in this embodiment, corresponding to four rotating current phases: Phase 0, Phase 90, Phase 180, and Phase 270. At Phases 0 and 180, the junction field effect modulates the bottom of the N-well symmetrically, resulting in symmetrical depletion layers. Consequently, the device misalignment at these two phases is relatively small. However, at Phases 90 and 270, the junction field effect modulates the bottom of the N-well asymmetrically, significantly increasing the misalignment, typically several times that of Phases 0 and 180. The narrow-waisted five-contact vertical Hall device, by reducing the effective width of the N-well and N+ layers within the device, effectively reduces the misalignment caused by the asymmetric depletion layer at Phases 90 and 270. Furthermore, the reduction in active area and contact hole size improves device sensitivity to a certain extent, resulting in lower initial offset and higher Hall sensitivity than existing five-contact vertical Hall devices. However, this comes at the cost of significant nonlinearity in the device offset and Hall signal. This phenomenon becomes more pronounced as the device bias voltage increases.

[0041] Figure 5 and Figure 6 Plan views of the second and third embodiments of the narrow-waisted, five-contact vertical Hall device are provided. The effective width of the active area and contact holes at the center of the device must be smaller than the effective widths on either side. Unlike the first embodiment, the shape of the P-well ring in the device is different.

[0042] In order to solve the nonlinear problem of the thin waist five-contact vertical Hall device structure and further reduce the offset of the Hall device, the existing Hall offset elimination technology applied to the five-contact hole usually adopts orthogonal coupling technology, such as Figure 7 As shown in FIG, as a demonstration of a degradation scheme, the existing orthogonal coupling method is to connect C1 of device 1 and C2 of device 2, C2 of device 1 and C3 of device 2, C3 of device 1 and C4 of device 2, and C4 of device 1 and C1 of device 2. Figure 3As can be seen from the phases of phase 0 and phase 90, when current is applied to terminals C1 and C3 of device 1, current is also applied to terminals C2 and C4 of device 2. The current flow within the device is not completely symmetrical, so the rotating current technique cannot address the device offset and Hall signal nonlinearity. Therefore, this coupling method is not practical for five-contact vertical Hall devices.

[0043] The novel anti-phase parallel coupling method adopted by the present invention can effectively solve the above problems. The structure is as follows: Figure 8 As shown. Device 1 and device 2 are connected in reverse parallel coupling mode, and the first contact holes and the fifth contact holes of device 1 and device 2 are connected to each other as the contact hole C1 of the device. Then C1 of device 1 and C3 of device 2 are connected to each other, C2 of device 1 and C4 of device 2 are connected to each other, C3 of device 1 and C1 of device 2 are connected to each other, and C4 of device 1 and C2 of device 2 are connected to each other. Figure 9 As can be seen from the current flow diagrams of the four-phase rotating current technology shown in (a), 9 (b), 9 (c), and 9 (d), the current flows of the four phases are completely symmetrical. Therefore, this structure has lower initial offset and residual offset, and can better solve the signal nonlinearity problem caused by the structure of the thin-waisted Hall device itself. At the same time, it can more effectively eliminate the offset, thereby obtaining a completely symmetrical low-offset vertical Hall device.

[0044] It should be noted that, in order to enable those skilled in the art to better understand and reproduce the present invention, a preparation method for the main structure is provided in the specification. However, the design and protection claimed in the present invention are for the innovative structure of the device, not for its preparation method. Furthermore, for those skilled in the art, the preparation method corresponding to the structure of the present invention can be easily selected in one or more implementation methods based on its structural characteristics and utilizing existing known technologies. Therefore, the selection of the preparation process and method should not be regarded as a limitation on the structural solution of the present invention.

[0045] The present invention is not limited to the above-mentioned optimal implementation mode. Anyone can derive various other forms of a completely symmetrical low-offset vertical Hall device based on the inspiration of the present invention. All equivalent changes and modifications made within the scope of the patent application of the present invention should fall within the scope of the present invention.

Claims

1. A fully symmetrical low-offset vertical Hall effect device, characterized by: The invention comprises two anti-parallel coupled thin-waisted five-contact hole vertical Hall device; the thin-waisted five-contact hole vertical Hall device comprises a P-type substrate layer, an N-well layer, a P-well layer, an N-type heavily doped region and a P-type heavily doped region; the N-well layer is placed above the interior of the P-type substrate layer and is surrounded by the P-well layer; five N-type heavily doped regions and four P-type heavily doped regions are alternately arranged above the interior of the N-well layer; the P-well layer is annular, and the interior of the annular ring is a structure with a small middle and large sides, which is used to limit the N-well layer, the N-type and P-type heavily doped regions, thereby forming a thin-waisted structure; the N-type heavily doped region serves as the contact hole of the device; the anti-parallel coupling connection is: the contact holes of two identical thin-waisted five-contact hole vertical Hall devices are anti-connected through metal wires.

2. The fully symmetrical low-offset vertical Hall device according to claim 1, characterized in that: The N-type heavily doped regions and the P-type heavily doped regions are alternately arranged at equal intervals; the five N-type heavily doped regions have the same shape and size, and the four P-type heavily doped regions have the same shape and size.

3. The fully symmetrical low-offset vertical Hall device according to claim 1, characterized in that: A contact electrode is provided on each of the N-type heavily doped regions; and an electrode for grounding is provided on each of the P-type heavily doped regions.

4. The fully symmetrical low-offset vertical Hall device according to claim 3, characterized in that: Among the five contact electrodes, the first and last two contact electrodes are connected to form one contact electrode. Among the four electrodes thus formed, two electrodes serve as bias terminals of the Hall device, and the other two electrodes serve as Hall effect sensing terminals.

5. The fully symmetrical low-offset vertical Hall device according to claim 1, characterized in that: The thin waist structure is a symmetrical stepped structure.

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