Ultra-thin packaging device
Through the design of three-layer wire redistribution layers and conductive through-holes, the electrical connection and heat dissipation structure of high-power packaged devices are optimized, solving the problems of high resistance, high heat and large size in the existing technology, and achieving the compactness and efficient heat dissipation of ultra-thin packaged devices.
Patent Information
- Application Number
- CN202422739639.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-08
- Publication Date
- 2025-09-23
- Estimated Expiration
- 2034-11-08
AI Technical Summary
Existing high-power packaged devices have increased resistance and heat due to long bonding wire distances, resulting in insufficient heat dissipation, and the package size is large, making it difficult to meet the needs of thin devices.
A three-layer wire redistribution layer is used to adjust the connection between chip electrodes and pads, increase heat dissipation copper foil and conductive through-holes, optimize the electrical connection structure, and improve package compactness and heat dissipation efficiency.
The internal resistance and heat of the packaged device are reduced, the heat dissipation efficiency is improved, and the size requirements of the ultra-thin packaged device are met.
Smart Images
Figure CN223378171U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of packaging devices, in particular to an ultra-thin packaging device. Background Art
[0002] Existing high-power packaged devices are generally plastic-sealed by bonding a frame and copper wires. This requires laying long wire bonds to achieve electrical connections between chips, which increases the internal resistance of the device, generates high operating heat, and has insufficient heat dissipation after plastic sealing, affecting device reliability. The packaging structure based on the combination of copper wires and a frame increases the overall size of the packaged device, which cannot meet the packaging size requirements of thin devices. Utility Model Content
[0003] The purpose of the present invention is to overcome the shortcomings of the prior art. The present invention provides an ultra-thin packaging device. By setting a three-layer wire redistribution layer, the connection position and connection distance between the chip electrode and the device pad are adjusted, the compactness of the packaging device structure is improved, and the chip heat dissipation area is increased based on the fan-out electrode, thereby improving the heat dissipation efficiency of the device.
[0004] The utility model provides an ultra-thin package device, which comprises: a planar conductive power chip, a vertical conductive power chip, a first wire redistribution layer, a second wire redistribution layer, and a third wire redistribution layer;
[0005] The planar conductive power chip and the vertical conductive power chip are arranged on the first wire redistribution layer, and the planar conductive power chip and the vertical conductive power chip are connected to the third wire redistribution layer based on the second wire redistribution layer;
[0006] The third wire redistribution layer is configured as pad pins of the ultra-thin package device.
[0007] Furthermore, the first wire redistribution layer is configured with a plurality of heat dissipation copper foils, and the planar conductive power chip and the vertical conductive power chip are correspondingly arranged on the heat dissipation copper foils.
[0008] Furthermore, the chip electrodes of the planar conductive power chip and the vertical conductive power chip are electrically connected based on the second wire redistribution layer.
[0009] Furthermore, the second wire redistribution layer forms a plurality of copper foil areas based on the distribution positions of the planar conductive power chip and the vertical conductive power chip, and a plurality of insulating channels are formed between the plurality of copper foil areas.
[0010] Furthermore, the plurality of insulating channels include a first channel for separating a planar conductive power chip and a vertical conductive power chip, and a second channel for separating a high voltage electrode and a low voltage electrode.
[0011] Furthermore, the width of the first river channel is h1, and the value range of h1 is: 0.16mm
[0012] Furthermore, the width of the second river channel is h2, and the value range of h2 is: 0.2mm≤h2≤0.25mm.
[0013] Furthermore, a plurality of conductive vias are provided in the package device, and the first wire redistribution layer, the second wire redistribution layer, and the third wire redistribution layer are electrically connected based on the plurality of conductive vias.
[0014] Furthermore, the aperture of the conductive through hole is d, and the value range of d is: 100 μm≤d≤500 μm.
[0015] Furthermore, gaps between the first wire redistribution layer, the second wire redistribution layer, the third wire redistribution layer, the planar conductive power chip, and the vertical conductive power chip are encapsulated using an insulating encapsulation material.
[0016] The utility model provides an ultra-thin packaged device. By providing a first, second, and third wire redistribution layer, the electrical connection structure between the device electrode pads and the chip electrodes is adjusted, thereby improving the compactness of the ultra-thin packaged device. By arranging a planar conductive power chip and a vertical conductive power chip on the first wire redistribution layer, the heat dissipation area of the planar conductive power chip and the vertical conductive power chip is increased using fan-out electrodes, thereby improving the heat dissipation efficiency of the packaged device. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0018] Figure 1 This is a schematic diagram of the structure of an ultra-thin packaging device in an embodiment of the present utility model;
[0019] Figure 2 This is a schematic diagram of the structure of the first wire redistribution layer in an embodiment of the present utility model;
[0020] Figure 3 This is a schematic diagram of the structure of the second wire redistribution layer in an embodiment of the present utility model;
[0021] Figure 4 It is a schematic diagram of the structure of the third wire redistribution layer in an embodiment of the present utility model. DETAILED DESCRIPTION
[0022] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.
[0023] Please refer to Figures 1 to 4 An embodiment of the present invention provides an ultra-thin packaging device, comprising: a planar conductive power chip 1, a vertical conductive power chip 2, a first wire redistribution layer 100, a second wire redistribution layer 200, and a third wire redistribution layer 300. The planar conductive power chip 1 and the vertical conductive power chip 2 are arranged on the first wire redistribution layer 100, and the planar conductive power chip 1 and the vertical conductive power chip 2 are connected to the third wire redistribution layer 300 based on the second wire redistribution layer 200. The electrical arrangement structure of the ultra-thin packaging device is adjusted based on the first wire redistribution layer 100, the second wire redistribution layer 200, and the third wire redistribution layer 300, thereby improving the compactness of the packaging structure of the ultra-thin packaging device.
[0024] Furthermore, the wire redistribution layer is a technology used to redistribute electrical connections by forming an additional wiring layer on the chip surface or interposer to reallocate the I / O (input / output) positions of the chip to accommodate different packaging requirements and improve the flexibility of electrical connections.
[0025] Furthermore, the planar conductive power chip 1 is a planar conductive power high electron mobility transistor, configured as a power chip of an ultra-thin package device, and the vertical conductive power chip 2 is a silicon chip, configured as a driver chip of an ultra-thin package device.
[0026] The third wire redistribution layer 300 is configured as the solder pad pin of the ultra-thin package device. The solder pad position of the package device is adjusted through the third wire redistribution layer 300, so that the package device can be easily adapted to the external working circuit, thereby improving the electrical connection reliability of the ultra-thin package device.
[0027] Specifically, the first conductor redistribution layer 100 is configured with a plurality of heat dissipation copper foils, and the planar conductive power chip 1 and the vertical conductive power chip 2 are correspondingly arranged on the heat dissipation copper foils. Figure 2 Four heat dissipation copper foils are provided on the first wire redistribution layer 100, and the four heat dissipation copper foils are symmetrically distributed up and down. The ultra-thin package device is provided with two planar conductive power chips 1 and two vertical conductive power chips 2. The two planar conductive power chips 1 and the two vertical conductive power chips 2 are respectively arranged on the four heat dissipation copper foils. The heat dissipation area of the two planar conductive power chips 1 and the two vertical conductive power chips 2 is increased based on the heat dissipation copper foil, thereby improving the heat dissipation efficiency of the ultra-thin package device.
[0028] Specifically, the chip electrodes of the planar conductive power chip 1 and the vertical conductive power chip 2 are electrically connected via the second conductive redistribution layer 200. The two planar conductive power chips 1 and the two vertical conductive power chips 2 form a half-bridge connection structure based on the second conductive redistribution layer 200. When the input signal turns on the switch in the upper bridge arm, the switch in the lower bridge arm turns off, resulting in a high level at the output. Conversely, when the input signal turns on the switch in the lower bridge arm, the switch in the upper bridge arm turns off, resulting in a low level at the output. By continuously changing the control state of the input signal, a square wave signal can be generated at the output.
[0029] The second wire redistribution layer 200 forms a plurality of copper foil areas 3 based on the distribution positions of the planar conductive power chip 1 and the vertical conductive power chip 2, and a plurality of insulating channels are formed between the plurality of copper foil areas 3. The electrical connection of the electrodes between the planar conductive power chip 1 and the vertical conductive power chip 2 is achieved based on the plurality of copper foil areas 3.
[0030] Specifically, several of the insulating channels include a first channel for separating the planar conductive power chip 1 and the vertical conductive power chip 2, and a second channel for separating the high-voltage electrode and the low-voltage electrode. By setting different insulating channels, different chips and chip electrodes with different voltages are distinguished, so that the packaged device structure can meet the electrical isolation between each chip and improve the compactness of the wiring structure arrangement of each chip.
[0031] Furthermore, the width of the first river channel is h1, and the value range of h1 is: 0.16mm
[0032] Furthermore, the width of the second river channel is h2, and the value range of h2 is: 0.2mm≤h2≤0.25mm. By setting the spacing of 0.2mm to 0.25mm, the copper foil area 3 corresponding to the high-voltage electrode and the low-voltage electrode can have sufficient electrical isolation spacing to meet the requirements of electrical transmission of the high-voltage electrode, and at the same time, the heat dissipation effect of the electrical transmission path of the high-voltage electrode can be improved.
[0033] Based on the second wire redistribution layer 200, the G-pole parasitic inductance of the planar conductive power can be reduced, so that the G-pole of the planar conductive power chip 1 and the S-pole of the vertical conductive power chip 2 are connected in a straight line based on copper foil, avoiding bending or arc connection, thereby reducing the internal electrical resistance of the packaged device.
[0034] Specifically, based on the second wire redistribution layer 200, a straight electrical connection structure for the power loop and the drive loop of the packaged device can be realized, reducing the bending and curvature connection structure between the chip electrodes and the pad leads, thereby reducing the parasitic inductance and resistance of the power loop and the drive loop.
[0035] Specifically, a plurality of conductive vias 4 are provided in the package device, and the first wire redistribution layer 100, the second wire redistribution layer 200, and the third wire redistribution layer 300 are electrically connected based on the plurality of conductive vias 4. The electrical connection between each wire redistribution layer is achieved based on the plurality of conductive vias 4, thereby improving the convenience of electrical connection of each layer of wire redistribution layer.
[0036] Furthermore, the aperture of the conductive through hole 4 is d, and the value range of d is: 100μm≤d≤500μm. A through hole is opened on the wire redistribution layer of the device based on the laser perforation process, and a conductive through hole 4 is formed by plating a copper layer on the surface of the through hole to meet the electrical connection between the layers and at the same time improve the compactness of the packaging structure of the packaged device.
[0037] Specifically, based on the plurality of pad pins formed by the third layer of wire redistribution layer and based on the arrangement position of the pad pins, the creepage distance of the ultra-thin packaged device is met, so that the ultra-thin packaged device can meet the packaging requirements of high-power devices.
[0038] Furthermore, the spacing between the planar conductive power chip 1 and the adjacent conductive via 4 is h3, with the value range of h3 being 1.5d ≤ h3 ≤ 5d. This spacing ensures that the spacing between the planar conductive power chip 1 and the conductive via 4 meets electrical isolation requirements, reducing the risk of internal short circuits. The conductive via 4 adjacent to the planar conductive power chip 1 is configured to connect the conductive via 4 of the first and second conductive redistribution layers 100 and 200, thereby meeting the creepage distance requirements of the packaged device.
[0039] Furthermore, the gaps between the first wire redistribution layer 100 , the second wire redistribution layer 200 , the third wire redistribution layer 300 , the planar conductive power chip 1 , and the vertical conductive power chip 2 are encapsulated using an insulating encapsulation material.
[0040] The present invention provides an ultra-thin packaged device. By providing a first wire redistribution layer 100, a second wire redistribution layer 200, and a third wire redistribution layer 300, the electrical connection structure between the device electrode pads and the chip electrodes is adjusted, thereby improving the compactness of the ultra-thin packaged device. By disposing a planar conductive power chip 1 and a vertical conductive power chip 2 on the first wire redistribution layer 100, the heat dissipation area of the planar conductive power chip 1 and the vertical conductive power chip 2 is increased based on fan-out electrodes, thereby improving the heat dissipation efficiency of the packaged device.
[0041] In addition, the ultra-thin packaging device provided by the embodiment of the present invention is introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for general technical personnel in this field, based on the idea of the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.
Claims
1. An ultra-thin packaging device, characterized in that: The packaged device includes: a planar conductive power chip, a vertical conductive power chip, a first wire redistribution layer, a second wire redistribution layer, and a third wire redistribution layer; The planar conductive power chip and the vertical conductive power chip are arranged on the first wire redistribution layer, and the planar conductive power chip and the vertical conductive power chip are connected to the third wire redistribution layer based on the second wire redistribution layer; The thickness of the planar conductive power chip is consistent with that of the vertical conductive power chip; The third wire redistribution layer is configured as pad pins of the ultra-thin package device.
2. The ultra-thin package device according to claim 1, wherein: The first wire redistribution layer is configured with a plurality of heat dissipation copper foils, and the planar conductive power chip and the vertical conductive power chip are correspondingly arranged on the heat dissipation copper foils.
3. The ultra-thin package device according to claim 1, wherein: There is an insulating material between the planar conductive power chip and the vertical conductive power chip, and the insulating material contains conductive through-holes connecting the first wire redistribution layer and the second wire redistribution layer. The two chip electrodes are electrically connected through the conductive through-holes.
4. The ultra-thin package device according to claim 1, wherein: The second wire redistribution layer forms a plurality of copper foil areas based on the distribution positions of the planar conductive power chip and the vertical conductive power chip, and a plurality of insulating channels are formed between the plurality of copper foil areas.
5. The ultra-thin package device according to claim 4, characterized in that: The plurality of insulating channels include a first channel for separating a planar conductive power chip and a vertical conductive power chip, and a second channel for separating a high voltage electrode and a low voltage electrode.
6. The ultra-thin package device according to claim 5, characterized in that: The width of the first river channel is h1, and the value range of h1 is: 0.16mm<h1≤0.2mm.
7. The ultra-thin package device according to claim 5, wherein: The width of the second river channel is h2, and the value range of h2 is: 0.2mm≤h2≤0.25mm.
8. The ultra-thin package device according to claim 1, wherein: A plurality of conductive through-holes are provided in the package device, and the first wire redistribution layer, the second wire redistribution layer, and the third wire redistribution layer are electrically connected based on the plurality of conductive through-holes.
9. The ultra-thin package device according to claim 8, characterized in that: The aperture of the conductive through hole is d, and the value range of d is: 100 μm≤d≤500 μm.
10. The ultra-thin package device according to claim 1, wherein: Gaps between the first wire redistribution layer, the second wire redistribution layer, the third wire redistribution layer, the planar conductive power chip, and the vertical conductive power chip are encapsulated using an insulating encapsulation material.