Anti-interference circuit

Abstract

The utility model discloses an anti-interference circuit, and relates to the technical field of anti-interference circuits. According to the utility model, a device or module is added for sensing an interference signal and feeding back the interference signal to the MCU, in the same electromagnetic environment, the NPN triode Q3 and the NPN triode Q1 are influenced by the same interference source, and the NPN triode Q3 feeds back a product signal to the MCU; the diode D1 is connected to the device P1 to feed back whether signal interference occurs or not; when an interference source exists, the position A is at a low level, the diode is in forward conduction, and the point B is at a low level and is fed back to the MCU; a PNP triode Q2 is added to cut off the NPN triode Q1, so that the anti-interference effect is realized, and the circuit is prevented from being influenced by interference to make wrong work; the conduction threshold of the NPN triode is that the control end voltage is greater than Vbe (about 0.7 V), but the conduction conditions of the PNP triode are just opposite; the positive voltage enables the PNP triode to be cut off, and the enabling anti-interference effect is achieved.

Description

Technical Field

[0001] The utility model relates to the technical field of anti-interference circuits, in particular to an anti-interference circuit. Background Art

[0002] Tesla coils have the characteristics of high frequency and large electromagnetic radiation power. They are easy to interfere with the circuit. MCU sends pulse signals through transistors or drives electromagnets and other devices (such as Figure 1 As shown); the circuit MCU controls the NPN transistor (or NMOS tube) to control the pull-up resistor to achieve signal transmission, or drives LED lights, optocouplers, buzzers, motors, electromagnets and other devices to achieve circuit control.

[0003] In practical applications, this circuit is susceptible to interference from electromagnetic devices (such as high-frequency Tesla coils, high-frequency dividers, electric shock devices, and other interference devices), causing the P1 device to malfunction. This is because the voltage generated by the interference signal is greater than the threshold voltage Vbe of the NPN transistor, causing the Q1 transistor to conduct and causing the P1 device to malfunction. Because transistors amplify signals, when the amplitude of the interference signal exceeds the startup threshold Vbe of the NPN transistor (NMOS transistor), the transistor's CE junction conducts, sending an erroneous pulse signal to the P1 device (vending machines, game consoles, LED light drivers, optocouplers, buzzers, motors, electromagnets), causing the P1 device to malfunction.

[0004] Application product 1: coin validator or banknote validator uses this circuit to connect to vending machine or game machine. Criminals use Tesla electromagnetic jammer to make the machine automatically increase points;

[0005] Application product 2, electronic access control locks (password locks, fingerprint locks, card locks, etc.) use this circuit to drive the electromagnet to achieve door opening and closing control. Criminals use Tesla electromagnetic jammers to open the electromagnet in the door lock, easily open the door, and break into the house to steal. Utility Model Content

[0006] The purpose of the present invention is to provide an anti-interference circuit to solve the problems raised in the above background technology.

[0007] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0008] An anti-interference circuit includes a chip MCU, an NPN transistor (or NMOS transistor) Q1, a PNP transistor (or PMOS transistor) Q2, and an NPN transistor (or NMOS transistor) Q3.

[0009] The sensor interface of the chip MCU, the NPN transistor (or NMOS tube) Q3, the resistor R6 and the pulse circuit are connected in series in sequence;

[0010] The OUTPUT2 interface of the chip MCU, the resistor R4, the PNP transistor (or PMOS transistor) Q2, the NPN transistor (or NMOS transistor) Q1 and the device P1 are connected in series in sequence;

[0011] The OUTPUT1 interface of the chip MCU, the resistor R1, and the PNP transistor (or PMOS tube) Q1 are connected in series in sequence;

[0012] The device P1 is externally connected to the VCC terminal, and the sensor interface of the chip MCU is electrically connected between the NPN transistor (or NMOS transistor) Q1 and the device P1 through the diode D1.

[0013] Preferably, the connection between the Sensor interface of the chip MCU and the NPN transistor (or NMOS tube) Q3 is externally connected to a resistor R5, the resistor R5 is externally connected to the VCC terminal, and an external resistor R26 is connected between the NPN transistor (or NMOS tube) Q3 and the resistor R6, and the resistor R26 is connected to the ground terminal of the NPN transistor (or NMOS tube) Q3.

[0014] Preferably, an external resistor R3 is connected between the resistor R4 and the PNP transistor (or PMOS transistor) Q2, and the resistor R3 is connected to the ground terminal of the PNP transistor (or PMOS transistor) Q2.

[0015] Preferably, it includes a chip MCU, an NPN transistor Q1, a PNP transistor Q2 and an NPN transistor Q3;

[0016] The sensor interface of the chip MCU, the C pole of the NPN transistor Q3, the B pole of the NPN transistor Q3, the resistor R6 and the pulse circuit are connected in series in sequence;

[0017] The OUTPUT2 interface of the chip MCU, the resistor R4, the B pole of the PNP transistor Q2, the E pole of the PNP transistor Q2, the E pole of the NPN transistor Q1, the C pole of the NPN transistor Q1 and the device P1 are connected in series in sequence;

[0018] The OUTPUT1 interface of the chip MCU, the resistor R1, and the B pole of the PNP transistor Q1 are connected in series in sequence;

[0019] The device P1 is externally connected to the VCC terminal, and the sensor interface of the chip MCU is electrically connected between the C pole of the NPN transistor Q1 and the device P1 through the diode D1;

[0020] The sensor interface of the chip MCU and the C pole of the NPN transistor Q3 are connected to an external resistor R5, and the resistor R5 is externally connected to the VCC terminal. An external resistor R26 is connected between the B pole of the NPN transistor Q3 and the resistor R6, and the resistor R26 is connected to the E pole of the NPN transistor Q3, and the E pole of the NPN transistor Q3 is grounded;

[0021] An external resistor R3 is connected between the resistor R4 and the B pole of the PNP transistor Q2. The resistor R3 is connected to the C pole of the PNP transistor Q2, and the C pole of the PNP transistor Q2 is grounded.

[0022] Preferably, it includes a chip MCU, an NMOS tube Q1, a PMOS tube Q2 and an NMOS tube Q3;

[0023] The sensor interface of the chip MCU, the D pole of the NMOS tube Q3, the G pole of the NMOS tube Q3, the resistor R6 and the pulse circuit are connected in series in sequence;

[0024] The OUTPUT2 interface of the chip MCU, the resistor R4, the G pole of the PMOS tube Q2, the S pole of the PMOS tube Q2, the S pole of the NMOS tube Q1, the D pole of the NMOS tube Q1 and the device P1 are connected in series in sequence;

[0025] The OUTPUT1 interface of the chip MCU, the resistor R1, and the G pole of the PMOS tube Q1 are connected in series in sequence;

[0026] The device P1 is externally connected to the VCC terminal, and the sensor interface of the chip MCU is electrically connected between the D pole of the NMOS tube Q1 and the device P1 through the diode D1.

[0027] Preferably, the sensor interface of the chip MCU and the D pole of the NMOS tube Q3 are connected to an external resistor R5, the resistor R5 is externally connected to the VCC terminal, and an external resistor R26 is connected between the G pole of the NMOS tube Q3 and the resistor R6, the resistor R26 is connected to the S pole of the NMOS tube Q3, and the S pole of the NMOS tube Q3 is grounded;

[0028] An external resistor R3 is connected between the resistor R4 and the G terminal of the PMOS tube Q2. The resistor R3 is connected to the D terminal of the PMOS tube Q2, and the D terminal of the PMOS tube Q2 is treated as a ground terminal.

[0029] Compared with the prior art, the beneficial effects achieved by the present invention are:

[0030] In the present invention, a device or module is added to sense interference signals and feed them back to the MCU. In the same electromagnetic environment, the NPN transistor (or NMOS transistor) Q3 and the NPN transistor (or NMOS transistor) Q1 are affected by the same interference source. The NPN transistor (or NMOS transistor) Q3 feeds back the product signal to the MCU. The diode D1 is connected to the device P1 to feedback whether there is signal interference. When there is an interference source, the A position is low and the diode is forward-conducted, so the B point is low and fed back to the MCU. A PNP transistor (or PMOS transistor) Q2 is added to cut off the NPN transistor (or NMOS transistor) Q1 to achieve anti-interference effect, so that the circuit is not affected by interference and does not work erroneously. Since the conduction threshold of the NPN transistor is that the control terminal voltage is greater than Vbe (about 0.7V), the conduction condition of the PNP transistor (or PMOS transistor) is just the opposite. The forward voltage turns off the PNP transistor (or PMOS transistor), thereby enabling the anti-interference effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0032] Figure 1 It is the circuit diagram recorded in the background technology of this utility model;

[0033] Figure 2 It is a circuit diagram of the entire utility model;

[0034] Figure 3 This is another circuit diagram of the utility model. DETAILED DESCRIPTION

[0035] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0036] like Figure 1 As shown, the MCU of this circuit controls the NPN transistor (or NMOS tube) to control the pull-up resistor to achieve signal transmission, or drives LED lights, optocouplers, buzzers, motors, electromagnets and other devices to achieve circuit control.

[0037] like Figure 2As shown, the utility model provides a technical solution: an anti-interference circuit, including a chip MCU, an NPN transistor Q1, a PNP transistor Q2 and an NPN transistor Q3; the Sensor interface of the chip MCU, the C pole of the NPN transistor Q3, the B pole of the NPN transistor Q3, the resistor R6 and the pulse circuit are connected in series in sequence; the OUTPUT2 interface of the chip MCU, the resistor R4, the B pole of the PNP transistor Q2, the E pole of the PNP transistor Q2, the E pole of the NPN transistor Q1, the C pole of the NPN transistor Q1 and the device P1 are connected in series in sequence; the OUTPUT1 interface of the chip MCU, the resistor R1, the B pole of the PNP transistor Q1 are connected in series in sequence; the device P1 The external VCC end, the Sensor interface of the chip MCU is electrically connected between the C pole of the NPN transistor Q1 and the device P1 through the diode D1; the Sensor interface of the chip MCU and the C pole of the NPN transistor Q3 are connected to the external resistor R5, and the resistor R5 is externally connected to the VCC end, and the B pole of the NPN transistor Q3 and the resistor R6 are externally connected to the resistor R26, and the resistor R26 is connected to the E pole of the NPN transistor Q3, and the E pole of the NPN transistor Q3 is grounded; the external resistor R3 is connected between the resistor R4 and the B pole of the PNP transistor Q2, and the resistor R3 is connected to the C pole of the PNP transistor Q2, and the C pole of the PNP transistor Q2 is connected to the ground.

[0038] like Figure 3 As shown, the utility model provides another set of technical solutions: an anti-interference circuit, including a chip MCU, an NPN transistor Q1, a PNP transistor Q2 and an NPN transistor Q3; the Sensor interface of the chip MCU, the C pole of the NPN transistor Q3, the B pole of the NPN transistor Q3, the resistor R6 and the pulse circuit are connected in series in sequence; the OUTPUT2 interface of the chip MCU, the resistor R4, the B pole of the PNP transistor Q2, the E pole of the PNP transistor Q2, the E pole of the NPN transistor Q1, the C pole of the NPN transistor Q1 and the device P1 are connected in series in sequence; the OUTPUT1 interface of the chip MCU, the resistor R1, the B pole of the PNP transistor Q1 are connected in series in sequence; the device P 1 is externally connected to the VCC terminal, and the Sensor interface of the chip MCU is electrically connected between the C pole of the NPN transistor Q1 and the device P1 through the diode D1; the Sensor interface of the chip MCU and the C pole of the NPN transistor Q3 are connected to an external resistor R5, and the resistor R5 is externally connected to the VCC terminal. An external resistor R26 is connected between the B pole of the NPN transistor Q3 and the resistor R6, and the resistor R26 is connected to the E pole of the NPN transistor Q3, and the E pole of the NPN transistor Q3 is grounded; an external resistor R3 is connected between the resistor R4 and the B pole of the PNP transistor Q2, and the resistor R3 is connected to the C pole of the PNP transistor Q2, and the C pole of the PNP transistor Q2 is connected to the ground.

[0039] Specific working principle:

[0040] When the circuit of the present invention is used as a circuit for improving the anti-interference of a triode circuit:

[0041] 1. Add a device or module to sense the interference signal and feed it back to the MCU;

[0042] Method 1: An NPN transistor (or NMOS transistor) Q3 or an operational amplifier, etc., in the same electromagnetic environment, NPN transistor (or NMOS transistor) Q3 and NPN transistor (or NMOS transistor) Q1 are affected by the same interference source, and NPN transistor (or NMOS transistor) Q3 feeds the product feedback signal to the MCU;

[0043] Method 2: Diode D1 is connected to device P1 to provide feedback on whether there is signal interference. When there is an interference source, point A is at a low level, the diode is forward-conducted, and point B is at a low level, which is fed back to the MCU.

[0044] Second, add another PNP transistor (or PMOS tube) Q2 to cut off the NPN transistor (or NMOS tube) Q1 to achieve anti-interference effect, so that the circuit is not affected by interference and does not work erroneously;

[0045] Since the conduction threshold of the NPN transistor is that the control terminal voltage is greater than Vbe (about 0.7V), but the conduction condition of the PNP transistor (or PMOS tube) is just the opposite; the forward voltage turns off the PNP transistor (or PMOS tube), achieving the anti-interference effect;

[0046] 3. In the non-interference state, the MCU outputs a low level to the PNP transistor (or PMOS tube) Q2. When the MCU receives an interference signal, it outputs a high level to the PNP transistor (or PMOS tube) Q2, cutting off the circuit of the NPN transistor (or NMOS tube) Q1 tube, making the device P1 inoperative and free from interference.

[0047] When the circuit of the present invention is used as a circuit for multiple detection and solving electromagnetic interference theft:

[0048] 1. Multiple Detection Interference Signals

[0049] Detection 1: Using an NPN transistor (or NMOS transistor), in the same electromagnetic environment, NPN transistor (or NMOS transistor) Q3 and NPN transistor (or NMOS transistor) Q1 are affected by the same interference source. NPN transistor (or NMOS transistor) Q3 feeds the product feedback signal to the MCU.

[0050] Method 2: Diode D1 is connected to device P1 to provide feedback on whether there is signal interference. When there is an interference source, point A is at a low level, the diode is forward-conducted, and point B is at a low level, which is fed back to the MCU.

[0051] Second, add another PNP transistor (or PMOS tube) Q2 to cut off the NPN transistor (or NMOS tube) Q1 to achieve anti-interference effect, so that the circuit is not affected by interference and does not work erroneously;

[0052] Since the conduction threshold of the NPN transistor is that the control terminal voltage is greater than Vbe (about 0.7V), but the conduction condition of the PNP transistor (or PMOS tube) is just the opposite; the forward voltage turns off the PNP transistor (or PMOS tube), achieving the anti-interference effect;

[0053] 3. In the non-interference state, the MCU outputs a low level to the PNP transistor (or PMOS tube) Q2. When the MCU receives an interference signal, it outputs a high level to the PNP transistor (or PMOS tube) Q2, cutting off the loop of the NPN transistor (or NMOS tube) Q1, making the device P1 inoperative and free from interference.

[0054] Finally, it should be noted that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art will be able to modify the technical solutions described in the aforementioned embodiments or replace some of the technical features therein with equivalents. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. An anti-interference circuit, comprising a chip MCU, an NPN transistor Q1 or an NMOS transistor Q1, a PNP transistor Q2 or a PMOS transistor Q2, and an NPN transistor Q3 or an NMOS transistor Q3, characterized in that: The sensor interface of the chip MCU, the NPN transistor Q3 or the NMOS transistor Q3, the resistor R6 and the pulse circuit are connected in series in sequence; The OUTPUT2 interface of the chip MCU, the resistor R4, the PNP transistor Q2 or the PMOS transistor Q2, the NPN transistor Q1 or the NMOS transistor Q1 and the device P1 are connected in series in sequence; The OUTPUT1 interface of the chip MCU, the resistor R1, and the NPN transistor Q1 or the NMOS transistor Q1 are connected in series in sequence; The device P1 is externally connected to the VCC terminal, and the sensor interface of the chip MCU is electrically connected between the NPN transistor Q1 or the NMOS transistor Q1 and the device P1 through the diode D1.

2. The anti-interference circuit according to claim 1, characterized in that: The connection between the Sensor interface of the chip MCU and the NPN transistor Q3 or the NMOS tube Q3 is externally connected to the resistor R5, and the resistor R5 is externally connected to the VCC terminal. An external resistor R26 is connected between the NPN transistor Q3 or the NMOS tube Q3 and the resistor R6, and the resistor R26 is connected to the ground terminal of the NPN transistor Q3 or the NMOS tube Q3.

3. The anti-interference circuit according to claim 2, characterized in that: An external resistor R3 is connected between the resistor R4 and the PNP transistor Q2 or the PMOS transistor Q2, and the resistor R3 is connected to the ground terminal of the PNP transistor Q2 or the PMOS transistor Q2.

4. The anti-interference circuit according to claim 3, characterized in that: Including chip MCU, NPN transistor Q1, PNP transistor Q2 and NPN transistor Q3; The sensor interface of the chip MCU, the C pole of the NPN transistor Q3, the B pole of the NPN transistor Q3, the resistor R6 and the pulse circuit are connected in series in sequence; The OUTPUT2 interface of the chip MCU, the resistor R4, the B pole of the PNP transistor Q2, the E pole of the PNP transistor Q2, the E pole of the NPN transistor Q1, the C pole of the NPN transistor Q1 and the device P1 are connected in series in sequence; The OUTPUT1 interface of the chip MCU, the resistor R1, and the B pole of the PNP transistor Q1 are connected in series in sequence; The device P1 is externally connected to the VCC terminal, and the sensor interface of the chip MCU is electrically connected between the C pole of the NPN transistor Q1 and the device P1 through the diode D1; The sensor interface of the chip MCU and the C pole of the NPN transistor Q3 are connected to an external resistor R5, and the resistor R5 is externally connected to the VCC terminal. An external resistor R26 is connected between the B pole of the NPN transistor Q3 and the resistor R6, and the resistor R26 is connected to the E pole of the NPN transistor Q3, and the E pole of the NPN transistor Q3 is grounded; An external resistor R3 is connected between the resistor R4 and the B pole of the PNP transistor Q2. The resistor R3 is connected to the C pole of the PNP transistor Q2, and the C pole of the PNP transistor Q2 is grounded.

5. The anti-interference circuit according to claim 3, characterized in that: Including chip MCU, NMOS tube Q1, PMOS tube Q2 and NMOS tube Q3; The sensor interface of the chip MCU, the D pole of the NMOS tube Q3, the G pole of the NMOS tube Q3, the resistor R6 and the pulse circuit are connected in series in sequence; The OUTPUT2 interface of the chip MCU, the resistor R4, the G pole of the PMOS tube Q2, the S pole of the PMOS tube Q2, the S pole of the NMOS tube Q1, the D pole of the NMOS tube Q1 and the device P1 are connected in series in sequence; The OUTPUT1 interface of the chip MCU, the resistor R1, and the G pole of the PMOS tube Q1 are connected in series in sequence; The device P1 is externally connected to the VCC terminal, and the sensor interface of the chip MCU is electrically connected between the D pole of the NMOS tube Q1 and the device P1 through the diode D1.

6. The anti-interference circuit according to claim 5, characterized in that: The sensor interface of the chip MCU and the D-pole of the NMOS tube Q3 are connected to an external resistor R5, and the resistor R5 is externally connected to the VCC terminal. An external resistor R26 is connected between the G-pole of the NMOS tube Q3 and the resistor R6, and the resistor R26 is connected to the S-pole of the NMOS tube Q3, and the S-pole of the NMOS tube Q3 is grounded; An external resistor R3 is connected between the resistor R4 and the G terminal of the PMOS tube Q2. The resistor R3 is connected to the D terminal of the PMOS tube Q2, and the D terminal of the PMOS tube Q2 is treated as a ground terminal.

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