Voltage and current sensor signal acquisition device and traction control unit

Abstract

The utility model provides a voltage and current sensor signal acquisition device and a traction control unit. The device comprises a sampling conditioning module, an analog-to-digital conversion module, a first programmable gate array module and a first M-LVDS transceiver. The sampling conditioning module is used for collecting a current signal output by a voltage or current sensor and converting the current signal into a voltage signal; the analog-to-digital conversion module is connected with the sampling conditioning module and is used for carrying out alternating current and direct current conversion on the voltage signal to generate a conversion result; the first programmable gate array module is connected with the analog-to-digital conversion module and is used for synchronously acquiring the conversion result through multiple channels according to a preset period, generating an M-LVDS data packet according to the conversion result and converting the M-LVDS data packet into an M-LVDS signal; and the first M-LVDS transceiver is connected with the programmable gate array module and is used for providing the M-LVDS signal to a plurality of external inverter control board cards.

Description

Technical Field

[0001] The present application relates to the technical field of train traction control, and in particular to a voltage and current sensor signal acquisition device and a traction control unit. Background Art

[0002] In rail transit electric locomotives, traction converters, as core components for energy conversion, are responsible for efficiently converting electrical energy into mechanical energy. During this process, the inverter control unit (SPU) within the traction control unit (TCU) needs to collect key physical quantities such as contact line voltage, DC link voltage, output AC current, and input DC current. To ensure these physical quantities are accurately captured and processed by the inverter control unit, voltage and current sensors are typically used to convert the actual voltage and current into voltage signals. These signals are then collected by a dedicated voltage and current sensor (AIO) and provided to the SPU.

[0003] Existing AIO boards may have some deficiencies in design and application:

[0004] 1. The backplane of the board usually uses a parallel bus, which has low availability: Such boards usually consist of conditioning circuits and conversion devices ADC. The ADC drive control is generally performed by the corresponding SPU board. The main control board completes the ADC control via a parallel bus or SPI bus. The parallel bus has many signals, complex wiring, high cost, and problems such as the signal transmission frequency cannot be continuously improved. The SPI bus has poor anti-interference ability and is not suitable for cross-board transmission.

[0005] 2. There is an overlap problem between analog and digital signals: In a TCU, there are usually multiple SPUs to implement drive control of the rectifier or inverter. In some applications, some voltage and current signals need to be transmitted synchronously to multiple SPUs. However, sensor acquisition boards based on parallel buses or SPI cannot provide data to more than one actuator at the same time. Therefore, the only way to achieve this is to output the conditioned analog signal on the backplane, enter another acquisition board, and then collect it by its ADC and read it by the corresponding actuator. This results in the analog signal needing to enter the backplane together with the bus signal, which not only increases the complexity of the system, but also may introduce problems such as signal interference and transmission delay, and greatly limits the standardization of the interface. Utility Model Content

[0006] The purpose of this application is to provide a voltage and current sensor signal acquisition device and a traction control unit to overcome the problems of the prior art caused by the use of a parallel bus or SPI on the backplane, and the overlap problem of analog and digital quantities.

[0007] To achieve the above-mentioned objectives, the present application provides a voltage and current sensor signal acquisition device, which includes: a sampling and conditioning module, an analog-to-digital conversion module, a first programmable gate array module and a first M-LVDS transceiver; the sampling and conditioning module is used to acquire the current signal output by the voltage or current sensor and convert the current signal into a voltage signal; the analog-to-digital conversion module is connected to the sampling and conditioning module and is used to perform AC-DC conversion on the voltage signal to generate a conversion result; the first programmable gate array module is connected to the analog-to-digital conversion module and is used to synchronously acquire the conversion result through multiple channels via a gate array and convert the conversion result into an M-LVDS signal; the first M-LVDS transceiver is connected to the programmable gate array module and is used to provide the M-LVDS signal to multiple external inverter control boards.

[0008] In the above-mentioned voltage and current sensor signal acquisition device, optionally, the first programmable gate array module includes a clock unit, and the clock unit is used to trigger the first programmable gate array module to acquire the conversion result according to a preset period.

[0009] In the above-mentioned voltage and current sensor signal acquisition device, optionally, the first programmable gate array module includes a conversion drive unit and an M-LVDS sending unit; the conversion drive unit is used to drive the analog-to-digital conversion module to acquire the conversion result, and provide the flag bit of the analog-to-digital conversion module and the conversion result to the M-LVDS sending unit; the M-LVDS sending unit is used to generate an M-LVDS data packet according to the flag bit and the conversion result and convert it into an M-LVDS signal to be output by the first M-LVDS transceiver.

[0010] In the above-mentioned voltage and current sensor signal acquisition device, optionally, the M-LVDS sending unit includes a data generation component, a verification component and an encoding component; the verification component is used to combine the multiple conversion results according to the flag bit and generate a verification code; the data generation component is connected to the verification component, and is used to generate an M-LVDS data packet according to the verification code and the conversion result; the encoding component is connected to the data generation component, and is used to convert the M-LVDS data packet into an M-LVDS signal.

[0011] In the above-mentioned voltage and current sensor signal acquisition device, optionally, the sampling and conditioning module includes a sampling resistor unit and a conditioning circuit unit; the sampling resistor unit is used to collect the current signal output by the voltage or current sensor; and the conditioning circuit unit is used to convert the current signal into a voltage signal.

[0012] The present application also provides a traction control unit including the voltage and current sensor signal acquisition device. The traction control unit further includes multiple inverter control boards. The voltage and current sensor signal acquisition device is respectively connected to the multiple inverter control boards.

[0013] In the above-mentioned traction control unit, optionally, the inverter control board includes a second M-LVDS transceiver and a second programmable gate array module; the second M-LVDS transceiver is used to convert the received M-LVDS signal into an IO signal; the second programmable gate array module is connected to the second M-LVDS transceiver, and is used to decode the IO signal and store it locally.

[0014] In the above-mentioned traction control unit, optionally, the second programmable gate array module further includes a receiving unit, which is used to perform consistency check on the M-LVDS data packet according to the received check code, and store the M-LVDS data packet locally when the verification is passed.

[0015] In the above-mentioned traction control unit, optionally, the receiving unit includes a decoding component, a data receiving component and a verification component; the decoding component is used to parse the received M-LVDS signal to obtain a check code and an M-LVDS data packet; the verification component is used to perform a consistency check on the M-LVDS data packet according to the check code to obtain a verification result; the data receiving component is used to store the M-LVDS data packet locally according to the verification result.

[0016] In the above-mentioned traction control unit, optionally, the second programmable gate array module includes a clock unit, and the clock unit is used to trigger the second programmable gate array module to verify the data transmission status according to a preset period.

[0017] The beneficial technical effect of the present application is that 8-24 voltage or current signals can be collected at a synchronous speed of not less than 400kHz with 16-bit accuracy. The A / D conversion control and the M-LVDS transmission action are closely coordinated, and the synchronously collected data can be transmitted to all SPU boards without loss and synchronously, which can fully meet the speed and accuracy requirements of traction control and protection. The backplane interface has only two pairs of M-LVDS differential pairs, which greatly simplifies the overall structure of the traction control unit and the complexity of the backplane. This structure greatly reduces the backplane address and data lines, eliminates the need for backplane analog signals, and avoids the problem of sampling interference caused by the overlap of analog and digital quantities. Since M-LVDS has good anti-interference performance and low external radiation, the availability of the entire control system is also improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The drawings described herein are used to provide a further understanding of the present application, constitute a part of the present application, and do not constitute a limitation of the present application. In the drawings:

[0019] Figure 1A This is a schematic diagram of the structure of a voltage and current sensor signal acquisition device provided in one embodiment of the present application;

[0020] Figure 1B This is a schematic diagram of an application of a voltage and current sensor signal acquisition device provided in one embodiment of the present application;

[0021] Figure 2 A schematic diagram of the internal structure of a voltage and current sensor signal acquisition device provided in one embodiment of the present application;

[0022] Figure 3 A schematic diagram of the internal structure of a programmable logic device provided in one embodiment of the present application;

[0023] Figure 4 A schematic diagram of the FPGA workflow of the M-LVDS transmitter of the AIO provided in one embodiment of the present application;

[0024] Figure 5 This is a schematic diagram of the FPGA workflow of the M-LVDS receiving end of the SPU provided in one embodiment of the present application. DETAILED DESCRIPTION

[0025] The following will describe in detail the implementation methods of this application in conjunction with the accompanying drawings and examples, so that the application can fully understand how technical means are used to solve technical problems and achieve technical effects, and implement them accordingly. It should be noted that as long as there is no conflict, the various embodiments and the various features in each embodiment of this application can be combined with each other, and the resulting technical solutions are all within the scope of protection of this application.

[0026] It should be noted that the terms "including" and "having" and any variations thereof in the specification and claims of this application and the above-mentioned drawings are intended to cover non-exclusive inclusions. For example, a process, method, system, product or apparatus that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or are inherent to these processes, methods, products or apparatuses.

[0027] Please refer to Figure 1AAs shown, the voltage and current sensor signal acquisition device provided in the present application includes: a sampling and conditioning module, an analog-to-digital conversion module, a first programmable gate array module and a first M-LVDS transceiver; the sampling and conditioning module is used to collect the current signal output by the voltage or current sensor and convert the current signal into a voltage signal; the analog-to-digital conversion module is connected to the sampling and conditioning module and is used to perform AC-DC conversion on the voltage signal to generate a conversion result; the first programmable gate array module is connected to the analog-to-digital conversion module and is used to synchronously collect the conversion result through multiple channels through the gate array and convert the conversion result into an M-LVDS signal; the first M-LVDS transceiver is connected to the programmable gate array module and is used to provide the M-LVDS signal to multiple external inverter control boards. Wherein, the sampling and conditioning module includes a sampling resistor unit and a conditioning circuit unit; the sampling resistor unit is used to collect the current signal output by the voltage or current sensor; and the conditioning circuit unit is used to convert the current signal into a voltage signal.

[0028] In the above-mentioned embodiments, the voltage and current sensor signal acquisition device provided in this application utilizes a synchronous ADC chip to acquire input signals, a programmable logic device (FPGA) to drive and control the ADC, and an M-LVDS transceiver for point-to-multipoint data transmission. An ADC driver control program and an M-LVDS high-speed serial communication protocol are also designed. The device structurally comprises: 1. ADC conversion circuitry; 2. FPGA minimum system; 3. M-LVDS transceiver; and software comprises: an ADC driver control module and an M-LVDS transceiver module. It offers advantages such as simple structure, high accuracy, wide data bandwidth, high modularity, and ease of deployment and use.

[0029] For details, please refer to Figure 1B As shown, the traction control unit (TCU) is equipped with an M-LVDS-based AIO card and an SPU card, or any card that needs to receive AIO output (SPU in this example). M-LVDS supports multiple receivers and can support up to 32 nodes, so multiple SPU cards can be deployed to fully meet the needs of the traction control unit. The AIO card is the data transmitter and is responsible for transmission only; all SPU cards synchronously receive data from the AIO.

[0030] In one embodiment of the present application, the first programmable gate array module includes a conversion drive unit and an M-LVDS transmitting unit; the conversion drive unit is used to drive the analog-to-digital conversion module to collect the conversion result according to a preset period, and provide the flag bit of the analog-to-digital conversion module and the conversion result to the M-LVDS transmitting unit; the M-LVDS transmitting unit is used to generate an M-LVDS data packet based on the flag bit and the conversion result and convert it into an M-LVDS signal to be output by the first M-LVDS transceiver. The M-LVDS transmitting unit includes a data generation component, a check component and an encoding component; the check component is used to combine multiple conversion results according to the flag bit and generate a check code; the data generation component is connected to the check component and is used to generate an M-LVDS data packet based on the check code and the conversion result; the encoding component is connected to the data generation component and is used to convert the M-LVDS data packet into an M-LVDS signal. It should be noted that the above functions implemented by the first programmable gate array module provided in this application are mainly implemented through a combination of multiple different components or gate arrays, and it does not include any improvements to the method. Relevant technical personnel in this field can freely adjust and combine the above-mentioned first programmable gate array module through existing technology according to actual needs, and this application does not impose any restrictions on this.

[0031] Please refer to Figure 2 As shown in the figure, in actual operation, the internal structure of the voltage and current sensor signal acquisition device is as follows: the AIO board consists of a sampling resistor / conditioning circuit part, an ADC (A / D converter), namely an analog-to-digital conversion module, an FPGA minimum system, namely a first programmable gate array module, and an M-LVDS transceiver, namely a first M-LVDS transceiver; the output of the voltage and current sensor is generally a current signal of tens to hundreds of mA, which is converted into a voltage recognizable by the ADC through the sampling resistor / conditioning circuit part of the AIO board; an ADC with multi-channel synchronous acquisition should be selected to ensure that the acquisition phase of voltage and current is consistent; the ADC drive control is implemented by the FPGA. Except for the initialization of the ADC at the initial power-on, the FPGA needs to accurately and periodically control and read the ADC; after obtaining the ADC conversion results, the FPGA packages these results into M-LVDS data packets, converts them into M-LVDS signals through the IO, and sends them to all SPUs via the M-LVDS transceiver. Here, the M-LVDS transceiver only plays a sending role.

[0032] The present application also provides a traction control unit including the voltage and current sensor signal acquisition device, the traction control unit also includes a plurality of inverter control boards, and the voltage and current sensor signal acquisition device is respectively connected to the plurality of inverter control boards. The inverter control board includes a second M-LVDS transceiver and a second programmable gate array module; the second M-LVDS transceiver is used to convert the received M-LVDS signal into an IO signal; the second programmable gate array module is connected to the second M-LVDS transceiver, and is used to decode the IO signal and store it locally. Specifically, the second programmable gate array module also includes a receiving unit, and the receiving unit is used to perform consistency check on the M-LVDS data packet according to the received check code, and store the M-LVDS data packet locally when the verification is passed. Furthermore, the receiving unit includes a decoding component, a data receiving component and a verification component; the decoding component is used to parse the received M-LVDS signal to obtain a check code and an M-LVDS data packet; the verification component is used to perform a consistency check on the M-LVDS data packet according to the check code to obtain a verification result; and the data receiving component is used to store the M-LVDS data packet locally according to the verification result.

[0033] For details, please refer to Figure 2 As shown, the SPU board consists of an M-LVDS transceiver, an FPGA minimum system, and a DSP or other processor. The SPU's M-LVDS transceiver only plays a receiving role. It converts the received M-LVDS differential signal into an IO signal and inputs it into the FPGA. The FPGA decodes it and stores it in the local space for use by the DSP. The first programmable gate array module and the second programmable gate array module are the FPGA minimum unit, and their structure can be referred to Figure 3As shown, the AIO's FPGA includes an ADC driver control module and an M-LVDS transmitter module. The M-LVDS transmitter module is further divided into an M-LVDS data generation module, a CRC check module, and an M-LVDS encoding module. The ADC driver module is responsible for periodically sending ADC control commands, reading ADC data, and sending the transmit flag and data to the M-LVDS transmitter module. When the M-LVDS transmitter module begins transmitting data, it simultaneously sends the data to the CRC check module. This continues until the last data item is transmitted. At this point, the CRC check module transmits the generated CRC check code back to the M-LVDS transmitter module, which appends the check code to the last byte of the data packet and transmits it, completing one round of ADC conversion and transmission. The SPU's FPGA includes an M-LVDS receiver module, which converts the M-LVDS clock and data sent by the AIO into parallel data and passes it to the M-LVDS data receiver module. Upon receiving the data, the receiver module activates the CRC check module to calculate the check code. After receiving the complete data packet, the received check code is compared with the calculated check code. If a match is found, it is sent to the local cache for reading by the DSP. Due to the point-to-multipoint output feature of M-LVDS, multiple SPUs can synchronously obtain the latest ADC conversion data.

[0034] Please refer to Figure 4 As shown in the figure, in actual work, this part consists of two parts: ADC control module and M-LVDS transmission module; the FPGA workflow of the M-LVDS transmitter of AIO is as follows:

[0035] After the FPGA is powered on and initialized, it first initializes the ADC, configuring the ADC's reference source, sampling rate, acquisition mode, and other parameters. It then begins periodically sending ADC conversion commands. Normally, after each conversion command is sent, the ADC returns a conversion completion signal. The ADC control module actively evaluates this signal. If no feedback is received or the feedback timeout occurs, the ADC control module reinitializes the ADC. If the feedback signal is received, it begins sending read enables and sequentially reads the ADC's output data. After reading the last data point, the ADC control module synchronously sends all conversion results and a transfer flag to the M-LVDS transmitter module. It then sets the conversion flag to 0 and waits for the next conversion cycle until the next cycle arrives, thus completing the ADC control and conversion cycle. The M-LVDS transmitter module converts all contents, including the header, data, and checksum, into serial data, and simultaneously transmits the M-LVDS clock and data signals. The M-LVDS transmitting module is in an inoperative state by default. After receiving the transmission flag and data from the ADC control module, it enters the transmitting state. The M-LVDS transmitting module first sends a 4-byte fixed content header, then activates the CRC check module and outputs the data content byte by byte to the M-LVDS encoding module and the CRC check module. The M-LVDS encoding module converts the input data into clock and data for external output, and the CRC check module synchronously generates a check code. When all data is sent, the final generated CRC check code is output to the encoding module output, thus completing a packet of M-LVDS data transmission and entering the waiting state for the flag and new data.

[0036] For details, please refer to Figure 5 As shown in the figure, in actual work, this part mainly includes the M-LVDS data receiving module and the CRC check module; the workflow diagram of the M-LVDS receiving end FPGA of the SPU is as follows: the M-LVDS decoding module has a disconnection detection function. When the input clock line or data line does not change within multiple consecutive agreed cycles, it will be determined to be in a disconnected state. In the disconnected state, it will temporarily release the disconnected state when the rising edge of the M-LVDS clock line arrives, and start sampling the input data and realize 1-bit to 8-bit serial-to-parallel conversion. After completing each 8-bit conversion, one byte of data is pushed to the M-LVDS data receiving module; after the M-LVDS data receiving module receives 4 consecutive agreed packet header contents, it starts to receive the actual data content and activates the CRC check module to synchronously generate a CRC check code. When the agreed data packet length is received, the CRC check code of the last byte of the data packet is compared with the locally generated CRC check code. If the two are consistent, the data of the current packet is received. If they are inconsistent, the local data is not updated to prevent erroneous data from being read by the DSP.

[0037] Theoretical transmission capacity calculation: The M-LVDS data generation module generates a packet header with fixed content of 4 bytes, 16-bit conversion results from 8-24 ADCs (maximum 48 bytes), and a 1-byte CRC checksum, totaling 53 bytes, or 424 bits. Considering the need for a certain amount of spacing between packets, a 500-bit value is used. The M-LVDS communication rate is calculated at 50 Mbit / s, allowing for 100,000 transmissions per second. Therefore, this application enables lossless transmission of ADC results from up to 24 channels with a sampling conversion rate below 100,000, meeting most traction calculation and protection needs.

[0038] The beneficial technical effect of the present application is that 8-24 voltage or current signals can be collected at a synchronous speed of not less than 400kHz with 16-bit accuracy. The A / D conversion control and the M-LVDS transmission action are closely coordinated, and the synchronously collected data can be transmitted to all SPU boards without loss and synchronously, which can fully meet the speed and accuracy requirements of traction control and protection. The backplane interface has only two pairs of M-LVDS differential pairs, which greatly simplifies the overall structure of the traction control unit and the complexity of the backplane. This structure greatly reduces the backplane address and data lines, eliminates the need for backplane analog signals, and avoids the problem of sampling interference caused by the overlap of analog and digital quantities. Since M-LVDS has good anti-interference performance and low external radiation, the availability of the entire control system is also improved.

[0039] The various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on the differences from other embodiments.

[0040] Throughout this specification, reference to terms such as "one embodiment," "a specific embodiment," "some embodiments," "for example," "example," "specific example," or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0041] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A voltage and current sensor signal acquisition device, characterized in that: The device comprises: a sampling and conditioning module, an analog-to-digital conversion module, a first programmable gate array module and a first M-LVDS transceiver; The sampling and conditioning module is used to collect the current signal output by the voltage or current sensor and convert the current signal into a voltage signal; The analog-to-digital conversion module is connected to the sampling and conditioning module, and is used to perform AC-DC conversion on the voltage signal to generate a conversion result; The first programmable gate array module is connected to the analog-to-digital conversion module, and is used to synchronously collect the conversion results through multiple channels via the gate array and convert the conversion results into M-LVDS signals; The first M-LVDS transceiver is connected to the programmable gate array module and is used to provide the M-LVDS signal to multiple external inverter control boards.

2. The voltage and current sensor signal acquisition device according to claim 1, characterized in that: The first programmable gate array module includes a clock unit, and the clock unit is used to trigger the first programmable gate array module to collect the conversion result according to a preset period.

3. The voltage and current sensor signal acquisition device according to claim 2, characterized in that: The first programmable gate array module includes a conversion drive unit and an M-LVDS sending unit; The conversion driving unit is used to drive the analog-to-digital conversion module to collect the conversion result, and provide the flag bit of the analog-to-digital conversion module and the conversion result to the M-LVDS sending unit; The M-LVDS sending unit is used to generate an M-LVDS data packet according to the flag bit and the conversion result, and convert the data packet into an M-LVDS signal to be output by the first M-LVDS transceiver.

4. The voltage and current sensor signal acquisition device according to claim 3, characterized in that: The M-LVDS sending unit includes a data generation component, a verification component and an encoding component; The verification component is used to combine the multiple conversion results according to the flag bit and generate a verification code; The data generating component is connected to the verification component, and is used to generate an M-LVDS data packet according to the verification code and the conversion result; The encoding component is connected to the data generating component and is used to convert the M-LVDS data packet into an M-LVDS signal.

5. The voltage and current sensor signal acquisition device according to claim 1, characterized in that: The sampling and conditioning module includes a sampling resistor unit and a conditioning circuit unit; The sampling resistor unit is used to collect the current signal output by the voltage or current sensor; The conditioning circuit unit is used to convert the current signal into a voltage signal.

6. A traction control unit comprising the voltage and current sensor signal acquisition device according to any one of claims 1 to 5, characterized in that: The traction control unit further includes a plurality of inverter control boards, and the voltage and current sensor signal acquisition device is respectively connected to the plurality of inverter control boards.

7. The traction control unit according to claim 6, characterized in that: The inverter control board includes a second M-LVDS transceiver and a second programmable gate array module; The second M-LVDS transceiver is used to convert the received M-LVDS signal into an IO signal; The second programmable gate array module is connected to the second M-LVDS transceiver and is used to decode the IO signal and store it locally.

8. The traction control unit according to claim 7, characterized in that: The second programmable gate array module further includes a receiving unit, which is used to perform consistency check on the M-LVDS data packet according to the received check code, and store the M-LVDS data packet locally when the verification is passed.

9. The traction control unit according to claim 8, characterized in that: The receiving unit includes a decoding component, a data receiving component and a verification component; The decoding component is used to parse the received M-LVDS signal to obtain a check code and an M-LVDS data packet; The verification component is used to perform consistency verification on the M-LVDS data packet according to the verification code to obtain a verification result; The data receiving component is used to store the M-LVDS data packet locally according to the verification result.

10. The traction control unit according to claim 8, characterized in that: The second programmable gate array module includes a clock unit, which is used to trigger the second programmable gate array module to verify the data transmission status according to a preset period.

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