Signal generator

Abstract

The utility model provides a signal generator, and belongs to the technical field of electronics. The device comprises a counter nixie tube display circuit, a frequency division clock signal generation circuit and a dial switch control circuit. A stable clock signal is generated through an NE555 timer, frequency division is carried out on the signal through a 74LS112JK trigger, then a 74LS160 counter is driven, and counting and displaying of pulses are completed. Signals output by the counter are displayed through a nixie tube, and the dial switch control circuit can flexibly adjust the output frequency and period of the signal generator by setting different combinations of switch positions. The signal generator simplifies the generation process of the pulse signal, reduces the use of hardware resources, reduces the operation complexity, and is suitable for wide application in experiment teaching and electronic product development.

Description

Technical Field

[0001] The utility model relates to a signal generator, belonging to the technical field of electronics. Background Art

[0002] During the development and testing of electronic products, generating precise pulse signals is crucial for testing circuit responsiveness and system calibration. Engineers often need to generate a precise number of pulse signals for testing circuit responsiveness or performing system calibration. Traditional pulse generation methods typically rely on complex hardware circuits and programming controls. For example, while crystal oscillators offer excellent frequency stability, their use requires precise crystal selection and strict layout avoidance of parasitic effects that could affect stability. For example, patent application number 201510058501.X, titled "A Signal Generator and Signal Generation Method for Generating Integer Frequency Pulses," outputs a division enable signal based on changes in the input frequency value, divides the system clock frequency by the input frequency value, and generates uniformly distributed integer frequency pulses. However, the circuit design is complex, waveform changes are inconvenient, and the cost is high. It is difficult for operators to quickly learn and is relatively complex to operate.

[0003] In the home appliance manufacturing industry, batch testing of control circuits is often required on production lines. Using traditional high-end signal generators is not only uneconomical, but also complex to debug and requires specialized operator training. Simple signal generators, on the other hand, offer a cost-effective, easy-to-use solution, helping companies significantly reduce production costs and time while ensuring product quality. This gives these devices broad market application prospects and development potential. Summary of the Invention

[0004] The utility model provides a signal generator which outputs the required waveform frequency simply and accurately through a counter digital tube display circuit, a frequency-dividing clock signal generating circuit and a dial switch control circuit.

[0005] The technical solution of the utility model is: a signal generator, including a counter digital tube display circuit 1, a frequency-divided clock signal generating circuit 2, and a dial switch control circuit 3;

[0006] The NE555 timer in the frequency-divided clock signal generating circuit 2 is connected to the 74LS112 JK trigger, the 74LS112 JK trigger is further connected to the 74LS160 counter of the counter digital tube display circuit 1, the 74LS160 counter is further connected to the DCD-HEX digital tube of the counter digital tube display circuit 1, and the dip switch control circuit 3 is connected to the frequency-divided clock signal generating circuit 2.

[0007] Furthermore, the counter digital tube display circuit 1 includes two 74LS160 counters and two DCD-HEX digital tubes; the 74LS160 counter I is used to control the units digit of the DCD-HEX digital tube CK, the ENP terminal, ENT terminal, and CLR terminal of the 74LS160 counter I are connected to the power supply VCC, the A1 terminal, B1 terminal, C1 terminal, and D1 terminal are simultaneously connected to the GND terminal, the LOAD terminal is connected to the LOAD terminal of the 74LS160 counter II, and at the same time, the LOAD terminal is connected to the output terminal of the NAND gate circuit of the dip switch control circuit 3, the QB1 terminal and QC1 terminal of the 74LS160 counter I are respectively connected to the A1 terminal and N1 terminal of the NAND gate circuit, and the CLK terminal is connected to the 74LS160 counter II. The CLK terminal of the DCD-HEX digital tube CK is connected to the QA1 terminal, QB1 terminal, QC1 terminal, and QD1 terminal are respectively connected to the P terminal, O terminal, I terminal, and U terminal of the DCD-HEX digital tube CK, and the CLR terminal is connected to the CLR terminal of the 74LS160 counter II. At the same time, the CLR terminal is connected to the power supply VCC; the 74LS160 counter II controls the tens digit of the DCD-HEX digital tube CK1, and the A terminal, B terminal, C terminal, and D terminal of the 74LS160 counter II are connected to the 74LS112 of the frequency-divided clock signal generating circuit 2. The 1Q end of the JK trigger is connected, the ENP end and ENT end of the 74LS160 counter II are connected to the RCO end of the 74LS160 counter I, the QA end, QB end, QC end, and QD end of the 74LS160 counter II are respectively connected to the Q end, W end, E end, and R end of the 4-bit KE dip switch of the dip switch control circuit 3, and are also connected to the L end, K end, J end, and H end of the DCD-HEX digital tube CK1.

[0008] Furthermore, the frequency-divided clock signal generating circuit 2 includes a NE555 time base integrated circuit, a 74LS112 JK trigger, resistor R1, resistor R2, potentiometer Rw, diodes D1 and D2, capacitor C1, capacitor C2 and NOT gate N; the VCC and RST terminals of the NE555 time-base integrated circuit are simultaneously connected to the power supply VCC, the DIS terminal of the NE555 time-base integrated circuit is connected to the power supply VCC through the resistor R1, the DIS terminal of the NE555 time-base integrated circuit is simultaneously connected to the anode of the diode D1 and the cathode of the diode D2 through the resistor R2, the cathode of the diode D1 and the anode of the diode D2 are connected and then connected to the 1st and 2nd pins of the potentiometer Rw, the 3rd pin of the potentiometer Rw is simultaneously connected to the THR terminal, TRI terminal and one end of the capacitor C1 of the NE555 time-base integrated circuit, the other end of the capacitor C1 is grounded, and the CON terminal of the NE555 time-base integrated circuit is grounded through the capacitor C2; the OUT terminal of the NE555 time-base integrated circuit outputs a pulse signal CP and is connected to the CLK terminal of the 74LS160 counter Ⅰ in the counter digital tube display circuit 1; at the same time, its OUT terminal is connected to the 74LS112 The 1CLK terminal of the JK trigger is connected, the 1J terminal of the 74LS112 JK trigger is connected to its 1Q' terminal and the input terminal of the NOT gate N at the same time, the output terminal of the NOT gate N is connected to the 1K terminal of the 74LS112 JK trigger, the 1PR and 1CLR terminals of the 74LS112 JK trigger are connected to the power supply VCC, and the 1Q terminal output pulse signal CP1 is connected to the counter digital tube display circuit 1.

[0009] Furthermore, the dip switch control circuit 3 includes a 4-bit KE dip switch and a NAND gate circuit; the NAND gate circuit includes a NAND gate B, a resistor R1, a resistor R2, a resistor R3, and a resistor R4; the Q, W, E, and R terminals of the 4-bit KE dip switch are connected to VCC through resistors R6, R5, R4, and R3, respectively, and the 4-bit KE dip switch is connected to the counter digital tube display circuit 1 through a NAND gate B; the Q, W, E, and R terminals of the 4-bit KE dip switch are connected to the QA, QB, QC, and QD terminals of the 74LS160 counter II of the counter digital tube display circuit 1, and the base number of the tens digit is controlled by the different positions of the 4-bit KE dip switch.

[0010] Furthermore, when the base number of the tens digit is controlled by the different positions of the 4-bit KE dial switch, the combination is Q end, W end, E end, R end, QW end, QE end, QR end, WE end, WR, ER end, QWE end, QER end, WER end, and QWER end; wherein, when the dial switch is turned on the Q end, the tens digit returns to zero when it reaches 1, when the dial switch is turned on the W end, the tens digit returns to zero when it reaches 2, when the dial switch is turned on the E end, the tens digit returns to zero when it reaches 4, and when the dial switch is turned on the R end When the dial switch opens the Q and W ends, the tens digit returns to zero when it reaches 8. When the dial switch opens the Q and W ends, the tens digit returns to zero when it reaches 3. When the dial switch opens the Q and E ends, the tens digit returns to zero when it reaches 5. When the dial switch opens the W and E ends, the tens digit returns to zero when it reaches 6. When the dial switch opens the Q, W and E ends, the tens digit returns to zero when it reaches 7. When the dial switch opens the Q and R ends, W and R ends, E and R ends, Q, E and R ends, W and E and R ends, Q, W and E and R ends at the same time, the tens digit returns to zero when it reaches 9.

[0011] The beneficial effects of this utility model are as follows: the utility model generates a stable clock signal through the NE555 timer, divides the signal through the 74LS112 JK flip-flop, and then drives the 74LS160 counter to complete pulse counting and display. The signal output by the counter is displayed through a digital tube, and the DIP switch control circuit can flexibly adjust the output frequency and period of the signal generator by setting different switch positions. This signal generator simplifies the pulse signal generation process, reduces hardware resource usage, and reduces operational complexity, making it suitable for widespread application in experimental teaching and electronic product development.

[0012] In summary, the utility model provides a signal generator that can simply and accurately output the required waveform frequency through a counter digital tube display circuit, a frequency-dividing clock signal generating circuit, and a DIP switch control circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is a schematic diagram of the circuit principle of a signal generator of the utility model;

[0014] Figure 1 The numbers in the figure are: 1-counter digital tube display circuit, 2-frequency division clock signal generating circuit, 3-dip switch control circuit, 74LS160 counter, DCD-HEX-digital tube, R1, R2, R3, R4, R5, R6-resistors, Rw-potentiometer, D1, D2-diodes, C1, C2-capacitors, N-not gate, B-not and gate, S1-dip switch. DETAILED DESCRIPTION

[0015] The signal generator proposed by the present invention is further described below with reference to the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are all simplified and not accurately scaled, and are only used to facilitate and clearly illustrate the embodiments of the present invention.

[0016] Example 1: Figure 1 As shown, the signal generator includes a counter digital tube display circuit 1, a frequency-divided clock signal generating circuit 2, and a dip switch control circuit 3;

[0017] The counter digital tube display circuit 1 includes two 74LS160 counters and two DCD-HEX digital tubes; the 74LS160 counter I is used to control the units digit of the DCD-HEX digital tube CK, the ENP terminal, ENT terminal, and CLR terminal of the 74LS160 counter I are connected to the power supply VCC, the A1 terminal, B1 terminal, C1 terminal, and D1 terminal are simultaneously connected to the GND terminal, the LOAD terminal is connected to the LOAD terminal of the 74LS160 counter II, and at the same time, the LOAD terminal is connected to the output terminal of the NAND gate circuit of the dip switch control circuit 3, the QB1 terminal and QC1 terminal of the 74LS160 counter I are respectively connected to the A1 terminal and N1 terminal of the NAND gate circuit, and the CLK terminal is connected to the 74LS160 counter II. The CLK terminal of the DCD-HEX digital tube CK is connected to the QA1 terminal, QB1 terminal, QC1 terminal, and QD1 terminal are respectively connected to the P terminal, O terminal, I terminal, and U terminal of the DCD-HEX digital tube CK, and the CLR terminal is connected to the CLR terminal of the 74LS160 counter II. At the same time, the CLR terminal is connected to the power supply VCC; the 74LS160 counter II controls the tens digit of the DCD-HEX digital tube CK1, and the A terminal, B terminal, C terminal, and D terminal of the 74LS160 counter II are connected to the 74LS112 of the frequency-divided clock signal generating circuit 2. The 1Q end of the JK trigger is connected, the ENP end and ENT end of the 74LS160 counter II are connected to the RCO end of the 74LS160 counter I, the QA end, QB end, QC end, and QD end of the 74LS160 counter II are respectively connected to the Q end, W end, E end, and R end of the 4-bit KE dip switch of the dip switch control circuit 3, and are also connected to the L end, K end, J end, and H end of the DCD-HEX digital tube CK1.

[0018] The frequency-divided clock signal generating circuit 2 includes a NE555 time base integrated circuit, a 74LS112 JK trigger, resistor R1, resistor R2, potentiometer Rw, diodes D1 and D2, capacitor C1, capacitor C2 and NOT gate N; the VCC and RST terminals of the NE555 time-base integrated circuit are simultaneously connected to the power supply VCC, the DIS terminal of the NE555 time-base integrated circuit is connected to the power supply VCC through the resistor R1, the DIS terminal of the NE555 time-base integrated circuit is simultaneously connected to the anode of the diode D1 and the cathode of the diode D2 through the resistor R2, the cathode of the diode D1 and the anode of the diode D2 are connected and then connected to the 1st and 2nd pins of the potentiometer Rw, the 3rd pin of the potentiometer Rw is simultaneously connected to the THR terminal, TRI terminal and one end of the capacitor C1 of the NE555 time-base integrated circuit, the other end of the capacitor C1 is grounded, and the CON terminal of the NE555 time-base integrated circuit is grounded through the capacitor C2; the OUT terminal of the NE555 time-base integrated circuit outputs a pulse signal CP and is connected to the CLK terminal of the 74LS160 counter Ⅰ in the counter digital tube display circuit 1; at the same time, its OUT terminal is connected to the 74LS112 The 1CLK terminal of the JK trigger is connected, the 1J terminal of the 74LS112 JK trigger is connected to its 1Q' terminal and the input terminal of the NOT gate N at the same time, the output terminal of the NOT gate N is connected to the 1K terminal of the 74LS112 JK trigger, the 1PR and 1CLR terminals of the 74LS112 JK trigger are connected to the power supply VCC, and the 1Q terminal output pulse signal CP1 is connected to the counter digital tube display circuit 1.

[0019] The dip switch control circuit 3 includes a 4-bit KE dip switch and a NAND gate circuit; the NAND gate circuit includes a NAND gate B, a resistor R1, a resistor R2, a resistor R3, and a resistor R4; the Q, W, E, and R terminals of the 4-bit KE dip switch are connected to VCC through resistors R6, R5, R4, and R3, respectively, and the 4-bit KE dip switch is connected to the counter digital tube display circuit 1 through a NAND gate B; the Q, W, E, and R terminals of the 4-bit KE dip switch are connected to the QA, QB, QC, and QD terminals of the 74LS160 counter II of the counter digital tube display circuit 1, and the base number of the tens digit is controlled by the different positions of the 4-bit KE dip switch.

[0020] Furthermore, when the base number of the tens digit is controlled by the different positions of the 4-bit KE dial switch, the combination is Q end, W end, E end, R end, QW end, QE end, QR end, WE end, WR, ER end, QWE end, QER end, WER end, and QWER end; wherein, when the dial switch is turned on the Q end, the tens digit returns to zero when it reaches 1, when the dial switch is turned on the W end, the tens digit returns to zero when it reaches 2, when the dial switch is turned on the E end, the tens digit returns to zero when it reaches 4, and when the dial switch is turned on the R end When the dial switch opens the Q and W ends, the tens digit returns to zero when it reaches 8. When the dial switch opens the Q and W ends, the tens digit returns to zero when it reaches 3. When the dial switch opens the Q and E ends, the tens digit returns to zero when it reaches 5. When the dial switch opens the W and E ends, the tens digit returns to zero when it reaches 6. When the dial switch opens the Q, W and E ends, the tens digit returns to zero when it reaches 7. When the dial switch opens the Q and R ends, W and R ends, E and R ends, Q, E and R ends, W and E and R ends, Q, W and E and R ends at the same time, the tens digit returns to zero when it reaches 9.

[0021] The working principle of this utility model is:

[0022] The NE555 timer forms a stable multivibrator using components such as resistors R1 and R2, potentiometer Rw, and capacitors C1 and C2. This generates a fixed-frequency pulse signal CP. The frequency of this pulse signal is determined by the parameters of resistors R1 and R2, the adjustable resistor Rw, and capacitors C1 and C2. The output CP signal is transmitted through inverter N to the clock input (CLK) of the 74LS112JK flip-flop.

[0023] The 74LS112 is a JK flip-flop configured as a frequency divider. With each rising edge of the CP signal, the Q terminal of the 74LS112 outputs signal CP1. Due to the characteristics of the JK flip-flop, the frequency of CP1 is half that of CP. This means that every time CP1 outputs a full pulse, the CP signal has already output two pulses. CP1, as the divided signal, is used to drive the counter circuit.

[0024] The counter circuit consists of two 74LS160 chips, one for the ones digit and the other for the tens digit. The first-stage counter (74LS160 I) receives a pulse signal from CP1 as its clock input. Each time CP1 receives a rising edge, the first-stage counter increments by 1 and outputs the current binary value to a connected digital display. This digital display shows the ones digit. The second-stage counter (74LS160 II) connects the carry output (RCO) of the first-stage counter to the clock input of the second-stage counter. When the first-stage counter overflows from 15 (1111) to 0, RCO outputs a pulse, triggering the second-stage counter to count up and display the tens digit. These two counters combine to form a hexadecimal counter system (00 to FF), with the current count value displayed on two connected seven-segment digital displays.

[0025] DIP switch S1 is used to set the initial value of the counter. The Q, W, E, and R terminals of the 4-position KE DIP switch are connected to the QA, QB, QC, and QD terminals of the 74LS16074LS160(II) in the counter's digital tube display circuit 1. Changing the position of the 4-position KE DIP switch controls the base of the tens digit. The combinations are Q, W, E, R, QW, QE, QR, WE, WR, ER, QWE, QER, WER, and QWER. When the dial switch is turned on the Q end, the tens digit returns to zero when it reaches 1, when the dial switch is turned on the W end, the tens digit returns to zero when it reaches 2, when the dial switch is turned on the E end, the tens digit returns to zero when it reaches 4, when the dial switch is turned on the R end, the tens digit returns to zero when it reaches 8, when the dial switch is turned on the Q and W ends, the tens digit returns to zero when it reaches 3, when the dial switch is turned on the Q and E ends, the tens digit returns to zero when it reaches 5, when the dial switch is turned on the W and E ends, the tens digit returns to zero when it reaches 6, when the dial switch is turned on the Q, W and E ends, the tens digit returns to zero when it reaches 7, and when the dial switch is turned on the Q and R ends, W and R ends, E and R ends, Q and E and R ends, W and E and R ends, Q and W and E and R ends at the same time, the tens digit returns to zero when it reaches 9.

[0026] The specific embodiments of the present invention are described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Various changes can be made within the knowledge of ordinary technicians in this field without departing from the purpose of the present invention.

Claims

1. A signal generator, characterized in that: It includes a counter digital tube display circuit (1), a frequency-divided clock signal generating circuit (2), and a dial switch control circuit (3); The NE555 timer in the frequency-divided clock signal generating circuit (2) is connected to the 74LS112 JK trigger, the 74LS112JK trigger is further connected to the 74LS160 counter of the counter digital tube display circuit (1), the 74LS160 counter is further connected to the DCD-HEX digital tube of the counter digital tube display circuit (1), and the DIP switch control circuit (3) is connected to the frequency-divided clock signal generating circuit (2); The counter digital tube display circuit (1) includes two 74LS160 counters and two DCD-HEX digital tubes; the 74LS160 counter I is used to control the units digit of the DCD-HEX digital tube CK, the ENP terminal, ENT terminal, and CLR terminal of the 74LS160 counter I are connected to the power supply VCC, the A1 terminal, B1 terminal, C1 terminal, and D1 terminal are simultaneously connected to the GND terminal, the LOAD terminal is connected to the LOAD terminal of the 74LS160 counter II, and at the same time, the LOAD terminal is connected to the output terminal of the NAND gate circuit of the dial switch control circuit (3), the QB1 terminal and QC1 terminal of the 74LS160 counter I are respectively connected to the A1 terminal and N1 terminal of the NAND gate circuit, and the CLK terminal is connected to the 74LS160 counter II. The CLK terminal of the DCD-HEX digital tube CK is connected, the QA1 terminal, QB1 terminal, QC1 terminal, and QD1 terminal are connected to the P terminal, O terminal, I terminal, and U terminal of the DCD-HEX digital tube CK respectively, and the CLR terminal is connected to the CLR terminal of the 74LS160 counter II. At the same time, the CLR terminal is connected to the power supply VCC; the 74LS160 counter II controls the tens digit of the DCD-HEX digital tube CK1, and the A terminal, B terminal, C terminal, and D terminal of the 74LS160 counter II are connected to the 74LS112 of the frequency division clock signal generating circuit (2). The 1Q terminal of the JK trigger is connected, the ENP terminal and ENT terminal of the 74LS160 counter II are connected to the RCO terminal of the 74LS160 counter I, the QA terminal, QB terminal, QC terminal and QD terminal of the 74LS160 counter II are respectively connected to the Q terminal, W terminal, E terminal and R terminal of the 4-bit KE dial switch of the dial switch control circuit (3), and are also connected to the L terminal, K terminal, J terminal and H terminal of the DCD-HEX digital tube CK1; The frequency-divided clock signal generating circuit (2) comprises a NE555 time base integrated circuit, a 74LS112 JK trigger, resistor R1, resistor R2, potentiometer Rw, diodes D1 and D2, capacitor C1, capacitor C2 and NOT gate N; the VCC and RST terminals of the NE555 time base integrated circuit are simultaneously connected to the power supply VCC, the DIS terminal of the NE555 time base integrated circuit is connected to the power supply VCC through the resistor R1, the DIS terminal of the NE555 time base integrated circuit is simultaneously connected to the anode of the diode D1 and the cathode of the diode D2 through the resistor R2, the cathode of the diode D1 and the anode of the diode D2 are connected to the 1st and 2nd pins of the potentiometer Rw, the 3rd pin of the potentiometer Rw is simultaneously connected to the THR terminal, TRI terminal and one end of the capacitor C1 of the NE555 time base integrated circuit, the other end of the capacitor C1 is grounded, and the CON terminal of the NE555 time base integrated circuit is grounded through the capacitor C2; the OUT terminal of the NE555 time base integrated circuit outputs a pulse signal CP which is connected to the CLK terminal of the 74LS160 counter I in the counter digital tube display circuit (1); at the same time, its OUT terminal is connected to the 74LS112 The 1CLK terminal of the JK trigger is connected, the 1J terminal of the 74LS112 JK trigger is connected to its 1Q' terminal and the input terminal of the NOT gate N, the output terminal of the NOT gate N is connected to the 1K terminal of the 74LS112 JK trigger, the 1PR and 1CLR terminals of the 74LS112 JK trigger are connected to the power supply VCC, and the pulse signal CP1 output from the 1Q terminal is connected to the counter digital tube display circuit (1); The dip switch control circuit (3) includes a 4-bit KE dip switch and a NAND gate circuit; the NAND gate circuit includes a NAND gate B, a resistor R1, a resistor R2, a resistor R3, and a resistor R4; the Q end, W end, E end, and R end of the 4-bit KE dip switch are connected to VCC through resistors R6, R5, R4, and R3 respectively, and the 4-bit KE dip switch is connected to the counter digital tube display circuit (1) through the NAND gate B; the Q end, W end, E end, and R end of the 4-bit KE dip switch are connected to the QA end, QB end, QC end, and QD end of the 74LS160 counter II of the counter digital tube display circuit (1), and the base number of the ten-digit digital tube is controlled by different positions of the 4-bit KE dip switch; When the base number of the tens digit is controlled by the different positions of the 4-bit KE dial switch, the combination is Q end, W end, E end, R end, QW end, QE end, QR end, WE end, WR, ER end, QWE end, QER end, WER end, QWER end; wherein, when the dial switch is turned on the Q end, the tens digit returns to zero when it reaches 1, when the dial switch is turned on the W end, the tens digit returns to zero when it reaches 2, when the dial switch is turned on the E end, the tens digit returns to zero when it reaches 4, and when the dial switch is turned on the R end, the tens digit returns to zero when it reaches 4. When the tens digit reaches 8, it returns to zero. When the dial switch opens the Q and W ends, it returns to zero when the tens digit reaches 3. When the dial switch opens the Q and E ends, it returns to zero when the tens digit reaches 5. When the dial switch opens the W and E ends, it returns to zero when the tens digit reaches 6. When the dial switch opens the Q, W and E ends, it returns to zero when the tens digit reaches 7. When the dial switch opens the Q and R ends, W and R ends, E and R ends, Q, E and R ends, W and E and R ends, Q, W and E and R ends at the same time, the tens digit returns to zero when it reaches 9.

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