Wafer carrier and wafer processing tool

Abstract

The utility model discloses a wafer carrier and a wafer processing tool. The wafer carrier comprises a box body and a cover body, the box body is used for accommodating a wafer boat. The cover body is pivoted with the box body, wherein one of the box body and the cover body is provided with a first opening.

Description

Technical Field

[0001] Some embodiments of the present disclosure relate to a wafer carrier and a wafer processing tool. Background Art

[0002] Wafer carriers are used to store and transport multiple wafers in batches between load ports of various wafer processing tools or equipment throughout a semiconductor manufacturing facility ("fab"). These tools typically perform various lithography, etching, material / thin film deposition, curing, annealing, inspection, or other processes used in the manufacture of integrated circuit wafers. Utility Model Content

[0003] According to some embodiments of the present disclosure, a wafer carrier includes a box body and a cover body. The box body is used to accommodate a wafer boat. The cover body is pivotally connected to the box body, wherein one of the box body and the cover body has a first opening.

[0004] According to some embodiments of the present disclosure, a wafer processing tool includes a rack and an exhaust system. The rack includes a plurality of rack levels, wherein each of the rack levels has a bottom plate with a plurality of bottom plate openings, and one of the rack levels is configured to accommodate a wafer carrier. The exhaust system is connected to a lowest level of the rack levels and configured to generate an airflow between the rack levels through the bottom plate openings.

[0005] According to some embodiments of the present disclosure, a wafer processing tool includes a wafer carrier and a rack. The wafer carrier includes a box body and a cover body located above the box body. The box body is used to accommodate a wafer boat. The box body includes a bottom box plate, and the bottom box plate has a first opening. The cover body includes a top cover plate spaced apart from the bottom box plate in a vertical direction, and the top cover plate has a second opening, and the second opening of the top cover plate is staggered in the vertical direction with respect to the wafer boat. The rack includes a plurality of rack layers, wherein each of the plurality of rack layers has a bottom plate, the bottom plate having a plurality of bottom plate openings, and one of the plurality of rack layers is used to accommodate the wafer carrier. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure are best understood from the following detailed description in conjunction with the accompanying drawings. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1A is a schematic diagram of a wafer carrier according to some embodiments of the present disclosure;

[0008] Figure 1B for Figure 1A An exploded diagram of a wafer carrier;

[0009] Figure 1C for Figure 1A Top view of the wafer carrier;

[0010] Figure 1D exhibit Figure 1A The side of the wafer carrier;

[0011] Figure 1E exhibit Figure 1A The back side of the wafer carrier;

[0012] Figure 1F for Figure 1A A bottom view of a wafer carrier;

[0013] Figure 2A is a schematic diagram of a wafer processing tool including a rack with an exhaust system according to some embodiments of the present disclosure;

[0014] Figure 2B illustrate Figure 2A multiple parts of wafer processing tools;

[0015] Figure 3 is a flow chart of a method for processing a wafer according to some embodiments of the present disclosure;

[0016] Figures 4A to 4G describes various stages of fabrication according to some embodiments of the present disclosure;

[0017] Figure 5A is a schematic diagram of a wafer carrier containing a wafer according to some embodiments of the present disclosure;

[0018] Figure 5B exhibit Figure 5A a top surface of a wafer carrier;

[0019] Figure 5C exhibit Figure 5A The side of the wafer carrier;

[0020] Figure 5D exhibit Figure 5A The back side of the wafer carrier;

[0021] Figure 5E exhibit Figure 5A A bottom view of a wafer carrier;

[0022] Figure 6A illustrating the fluorine content on a wafer surface according to some embodiments of the present disclosure;

[0023] Figure 6B Failure rates across multiple wafers according to some embodiments of the present disclosure are illustrated.

[0024]

Explanation of symbols

[0025] 100: Wafer carrier

[0026] 100A: Wafer carrier

[0027] 100B: Wafer carrier

[0028] 110: Lower box

[0029] 112: bottom box board

[0030] 112O, 118O, 122O, 124O, 128O: Open

[0031] 114: Side box panel

[0032] 114C: Carrier handle

[0033] 116:Front box panel

[0034] 118: rear box panel

[0035] 118F: Connecting element

[0036] 120: Upper cover

[0037] 122: Top cover

[0038] 124: Side cover

[0039] 126:Front cover

[0040] 128: rear cover

[0041] 128R: Connecting element

[0042] 200: rack

[0043] 210, 210A~210C: rack layer

[0044] 212: Bottom plate

[0045] 212F: Positioning element

[0046] 212O: Bottom plate opening

[0047] 214: Door

[0048] 214W: Transparent Window

[0049] 220: Ceiling

[0050] 220O: Ceiling opening

[0051] 230: Exhaust system

[0052] 232: Exhaust pipe

[0053] 234: Exhaust funnel

[0054] 236: Valve

[0055] 320:Metal liner

[0056] 330: passivation layer

[0057] AS: Side

[0058] BS: Back side

[0059] DS:Distance

[0060] FG: Fluorine-containing gas

[0061] FP: Fluorine particles

[0062] FS:Front side

[0063] GF: Airflow

[0064] HO, PRO: Open

[0065] LS, LS1, LS2: long side

[0066] M: Method

[0067] PR: Photoresist layer

[0068] S1~S12: Steps

[0069] SS, SS1, SS2: short side

[0070] W: Wafer

[0071] WB:Jingzhou

[0072] WB1: Crystal Boat

[0073] WB2: Crystal Boat

[0074] X, Y, Z: direction DETAILED DESCRIPTION

[0075] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the description below, forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features so that the first and second features may not be in direct contact. In addition, the disclosure may repeat element symbols or letters in various examples. This repetition is for simplicity and clarity and does not, in itself, specify the relationship between the various embodiments or configurations discussed.

[0076] In addition, for ease of description, spatially relative terms such as "below", "under", "below", "above", and "above" may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the accompanying drawings. Spatially relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation depicted in the accompanying drawings. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein should be interpreted accordingly. As used herein, "around", "about", "approximately" or "substantially" generally means within 20%, or within 10%, or within 5% of a given value or range. The numerical values ​​given herein are approximate, meaning that if not explicitly stated, the terms "around", "about", "approximately" or "substantially" can be inferred.

[0077] Figure 1A FIG. 1 is a schematic diagram of a wafer carrier 100 according to some embodiments of the present disclosure. Figure 1B for Figure 1A 1 is an exploded schematic diagram of a wafer carrier 100, wherein the wafer carrier 100 includes a lower box 110 and an upper cover 120. The wafer carrier 100 is a box structure, and illustratively, the wafer carrier 100 includes a lower box 110 and an upper cover 120, and a space for accommodating a wafer boat is formed between the lower box 110 and the upper cover 120. The lower box 110 and the upper cover 120 can be pivotally connected by a rotating shaft. Through the above configuration, the wafer carrier 100 can be opened or closed by flipping the upper cover 120. For example, the upper cover 120 can be rotated relative to the direction X to open or close the wafer carrier 100. In some embodiments of the present disclosure, the lower box 110 and the upper cover 120 of the wafer carrier 100 may have one or more openings. Through the above configuration, the space in the wafer carrier 100 is fluidically connected to the environment.

[0078] The lower case 110 includes a bottom panel 112, two side panels 114, a front panel 116, and a rear panel 118. The upper cover 120 includes a top panel 122, two side panels 124, a front panel 126, and a rear panel 128. The front panel 116 of the lower case 110 and the front panel 126 of the upper cover 120 can be joined together to form the front side FS of the wafer carrier 100. The rear panel 118 of the lower case 110 and the rear panel 128 of the upper cover 120 can be joined together to form the back side BS of the wafer carrier 100. One side plate 114 of the lower box body 110 and one side cover plate 124 of the upper cover body 120 can be joined together to form a side surface AS of the wafer carrier 100 , and the other side plate 114 of the lower box body 110 and the other side cover plate 124 of the upper cover body 120 can be joined together to form another side surface AS of the wafer carrier 100 .

[0079] In some embodiments of the present disclosure, the upper cover 120 and the lower housing 110 may have multiple openings to allow gases released from the wafers to escape from the wafer carrier 100. For example, with respect to the upper cover 120, the top cover 122 may have an opening 122O, the side cover 124 may have an opening 124O, and the rear cover 128 may have an opening 128O. With respect to the lower housing 110, the bottom panel 112 may have an opening 112O, and the rear panel 118 may have an opening 118O. The sizes of these openings 122O, 124O, 128O, 112O, and 118O may be determined based on actual circumstances.

[0080] Figure 1C for Figure 1A 1. A top view of the wafer carrier 100. The opening 122O of the top cover plate 122 may have a rectangular shape, with a length direction substantially parallel to the direction X. The opening 122O may have a long side LS ranging from about 80 mm to about 150 mm and a short side SS ranging from about 20 mm to about 40 mm, and a distance DS between the opening 122O and a side away from the opening 122O is about 180 mm to about 250 mm.

[0081] Figure 1D exhibit Figure 1A The side AS of the wafer carrier 100 is shown. The opening 124O of the side cover 124 may have a rectangular shape, with the longitudinal direction being substantially parallel to the direction Y. For example, the opening 124O may have a long side LS ranging from about 50 mm to about 200 mm and a short side SS ranging from about 5 mm to about 20 mm. Figure 1A and Figure 1D . In some embodiments, the openings 124O of the two opposing side cover plates 124 are symmetrical to each other. In some alternative embodiments, the openings 124O of the side cover plates 124 may be asymmetrical to each other. The wafer carrier 100 includes a pair of carrier handles 114C, which are disposed and / or fixed on the side box plates 114 of the lower box body 110 for conveniently holding, moving or carrying the wafer carrier 100. In some embodiments, the carrier handles 114C are used to manually transport the wafer carrier 100. In these embodiments, there are no openings on the side box plates 114 of the lower box body 110. In some alternative embodiments, each side box plate 114 of the lower box body 110 may have an opening.

[0082] Figure 1E exhibit Figure 1AThe rear side BS of the wafer carrier 100 is formed by pivotally connecting the rear panel 118 of the lower housing 110 to the rear cover 128 of the upper cover 120, so that the wafer carrier 100 can be opened or closed by moving the lower housing 110 and / or the upper cover 120. For example, the rear panel 118 of the lower housing 110 may have connecting elements 118F, which are respectively pivotally connected to the connecting elements 128R of the rear cover 128 of the upper cover 120. The opening 128O of the rear cover 128 and the opening 118O of the rear panel 118 may have a rectangular shape, with the longitudinal direction being substantially parallel to the direction X. For example, the opening 128O may have a long side LS1 ranging from approximately 80 mm to approximately 200 mm and a short side SS1 ranging from approximately 10 mm to approximately 50 mm. For example, the opening 118O may have a long side LS2 ranging from about 50 mm to about 150 mm and a short side SS2 ranging from about 10 mm to about 50 mm. In some embodiments, the aspect ratio of the long side LS1 to the short side SS1 of the opening 128O may be greater than the aspect ratio of the long side LS2 to the short side SS2 of the opening 118O.

[0083] Figure 1F for Figure 1A 1 is a bottom view of the wafer carrier 100. The opening 112O of the bottom box plate 112 may have a rectangular shape, with the longitudinal direction being substantially parallel to the direction X. For example, the opening 112O may have a long side LS ranging from about 50 mm to about 150 mm and a short side SS ranging from about 10 mm to about 50 mm.

[0084] Figure 2A FIG2 is a schematic diagram of a wafer processing tool according to some embodiments of the present disclosure, comprising a rack 200 having an exhaust system 230. The rack 200 may include a plurality of rack levels 210 (stacked one above the other), a ceiling 220 located above the rack levels 210, and an exhaust system 230 fluidly connected to the lowest level of the rack levels 210. One or more wafer carriers 100 and / or one or more wafer boats may be disposed in the rack levels 210 for, for example, purging gases from the wafers via the exhaust system 230. In this context, three rack levels 210 are illustrated. In some alternative embodiments, the number of rack levels 210 may range from 1 to 10. For clarity, the rack levels 210 are labeled as rack levels 210A, 210B, and 210C, with rack level 210B located above rack level 210A and rack level 210C located above rack level 210B. Different rack layers 210A, 210B, and 210C can accommodate wafer boats or wafer carriers for different process steps.

[0085] Figure 2B illustrate Figure 2AMultiple parts of a wafer processing tool. Each rack layer 210 may have a base plate 212 and multiple doors 214. The base plate 212 of each rack layer 210 (on which a wafer boat or wafer carrier is placed) may have multiple base plate openings 212O to allow fluid communication between the rack layers 210. In addition, the base plate 212 of the bottom layer of the rack layer 210 may have multiple base plate openings 212O to allow fluid communication between the exhaust system 230 and the bottom layer of the rack layer 210. In some embodiments, the base plate 212 has a positioning element 212F for positioning the wafer carrier / wafer boat in a target area. The door 214 can be opened or closed to move the wafer carrier / wafer boat into or out of the rack layer 210. The door 214 may have a transparent window 214W so that the operator can observe the wafer carrier / wafer boat through the transparent window 214W without opening the door 214. The ceiling 220 may have a plurality of ceiling openings 220O to allow fluid communication between the topmost layer of the rack layer 210 and the environment. The exhaust system 230 may include a plurality of exhaust pipes 232, a plurality of exhaust funnels 234, and a plurality of valves 236 coupled to the exhaust pipes 232. The exhaust pipes 232 may be connected to a pump. The exhaust funnels 234 are respectively connected to the exhaust pipes 232 and the lowest rack layer 210. With this configuration, by operating the exhaust system 230, a continuous downward airflow GF (e.g., Figure 2A ), passes through the ceiling 220 (eg, through the ceiling opening 220O) and the rack layer 210 (eg, through the bottom plate opening 212O), and reaches the exhaust system 230. A continuous downward airflow GF (eg, Figure 2A (as shown), without having to consider the movement of the wafer boat or wafer carrier. The combination of rack 200 and wafer carrier 100 effectively removes fluorine-containing gases escaping from the wafers, thereby reducing the amount of fluorine-containing gases surrounding the wafers. The configuration of exhaust funnel 234 increases the cross-sectional area through which gas flow GF passes. In the illustrated embodiment, exhaust system 230 is connected to the bottom of rack layer 210. In alternative embodiments, exhaust system 230 may be connected to other portions of rack layer 210 to provide better airflow for exhaust removal.

[0086] Figure 3 is a flow chart of a method M for processing a wafer according to some embodiments of the present disclosure. Figures 4A to 4GThe various stages of manufacturing according to some embodiments of the present disclosure are described. Method M may include steps S1 to S12. In step S1, a photoresist layer is formed on the passivation layer above the wafer. In step S2, the passivation layer is dry-etched, for example, to expose the metal pad. In step S3, the wafer is placed on a first wafer boat, and the first wafer boat is then moved to a rack with an exhaust system for a first gas removal process. In step S4, the photoresist is removed from the wafer by, for example, a dry stripping process. In step S5, the wafer is placed on a first wafer boat, the first wafer boat is moved into a first wafer carrier, and the first wafer carrier is then moved to a rack for a second gas removal process. In step S6, the wafer is inspected after the dry stripping process. In step S7, the photoresist is removed, for example, by a wet stripping process. In step S8, the wafer is placed on a second wafer boat. In step S9, the second wafer boat is moved into the second wafer carrier, and the second wafer carrier is moved to the rack for the third gas removal process. In step S10, the wafer is inspected after the wet stripping process. In step S11, an alloy is formed on the metal pad. In step S12, a wafer acceptance test is performed. It should be understood that Figure 3 Additional steps are provided before, during, and after steps S1 to S12 shown, and some of the steps described below may be replaced or eliminated for additional embodiments of the method. The order of the operations / processes may be interchanged.

[0087] See also Figure 3 and Figure 4A . Method M begins with step S1, in which a photoresist layer PR is formed on a passivation layer 330 over a wafer W. Wafer W may be referred to as a semiconductor substrate. Wafer W may be made of a suitable elemental semiconductor, such as silicon, diamond, or germanium; a suitable alloy or compound semiconductor, such as a Group IV compound semiconductor (silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), GeSn, SiSn, SiGeSn), a Group III-V compound semiconductor (e.g., gallium arsenide (GaAs), indium gallium arsenide (InGaAs), indium arsenide (InAs), indium phosphide (InP), indium antimonide (InSb), gallium arsenide phosphide (GaAsP), or gallium indium phosphide (GaInP)), etc. In addition, wafer W may include an epitaxial layer that may be strained to improve performance and / or may include a silicon-on-insulator (SOI) structure.

[0088] In some embodiments, one or more active and / or passive devices are formed on wafer W. An interconnect structure may be formed above the active and / or passive devices. The interconnect structure may include a metallization pattern comprising horizontally extending metal lines and vertically extending metal vias in a dielectric layer. One or more metal pads 320 (also referred to as a top metal layer) are then formed above the interconnect structure to directly contact the underlying metallization pattern in the interconnect structure. Thus, the metal pads 320 are electrically connected to the underlying metallization pattern in the interconnect structure. The metal pads 320 may be formed of aluminum, aluminum-copper, an aluminum alloy, copper, a copper alloy, or the like. For example, the metal pads 320 may include AlCu pads. The metal pads 320 may also be referred to as bonding pads. A passivation layer 330 is formed covering the metal pads 320. The passivation layer 330 may be formed of a dielectric material (such as undoped silica glass (USG), silicon nitride, silicon oxide, silicon oxynitride, or a non-porous material) using any suitable method (such as CVD, PVD, etc.). The passivation layer 330 may be a single layer or a stack of layers. It should be noted that a single layer of metal liner 320 and passivation layer 330 is shown for illustration purposes only. Therefore, other embodiments may include any number of metal liners and / or passivation layers.

[0089] A photoresist layer PR is formed over the passivation layer 330, for example, by a lithography process. The lithography process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, developing the photoresist, rinsing, drying (e.g., hard baking), and / or other suitable processes. The photoresist layer PR has an opening PRO that exposes the underlying passivation layer 330.

[0090] See also Figure 3 and Figure 4B , the method M proceeds to step S2, wherein the passivation layer 330 is etched to expose the metal liner 320. In these embodiments, a dry etching process (e.g., using a fluorine-containing gas) is performed using the photoresist layer PR as an etching mask, so that the first portion of the passivation layer 330 exposed by the opening PRO of the photoresist layer PR is etched away, and the second portion of the passivation layer 330 covered by the photoresist layer PR is protected from etching. Therefore, according to the profile and position of the opening PRO in the photoresist layer PR, an opening HO is etched in the passivation layer 330. In some embodiments, the metal liner 320 is slightly consumed by the dry etching process, so that the top surface of the first portion of the metal liner 320 exposed by the opening HO is lower than the top surface of the second portion of the metal liner 320 covered by the passivation layer 330.

[0091] In some embodiments, the dry etching process for etching the passivation layer 330 uses a fluorine-containing gas, such as SF6, CF4, CHF3, or a combination thereof. After the dry etching process is completed, fluoride will remain in the sidewall polymer, the photoresist layer PR, and the metal liner 320, and the fluoride may escape from the wafer W. For example, a fluorine-containing gas FG (e.g., a fluorine-containing gas) with fluorine particles FP may be used. Figure 4C (as shown) is released from the wafer W. If the fluorine-containing gas FG escaping from the wafer W is not effectively removed, a reaction may occur between the fluorine-containing gas FG and the exposed AlCu metal liner 320 after the passivation etching process. Crystals may grow on the passivation window, thereby forming a liner defect before packaging. The liner defect may cause bonding failure and reduce wafer reliability. Sometimes, the liner defect may cause the wafer to be scrapped and reduce the manufacturing yield. The reaction chemical formula between the fluorine-containing gas FG and the exposed AlCu metal liner 320 is exemplarily described below:

[0092] Al+xF - →[AlF x ] (x-3)- +3e -

[0093] 2[AlF x ] (x-3)- +4Al+6H2O→Al x O y F z .

[0094] x, y, and z are positive integers. The longer the reaction time, the more serious the gasket defect.

[0095] See also Figure 3 and Figure 4C . Method M proceeds to step S3, wherein the wafer W is moved / placed onto the first wafer boat WB1, and then the first wafer boat WB1 is moved / placed onto the rack 200 for a first gas removal process. The first wafer boat WB1 may include a plurality of slots / clamps for accommodating a plurality of wafers W and spacing the wafers W apart from each other. In some embodiments, the first wafer boat WB1 is angled relative to the horizontal plane so that the wafers W are guided onto their respective rear surfaces and the front or upper surfaces of the wafers W do not come into contact with any object. The wafer boat WB1 does not substantially surround the wafers W. Therefore, when the first wafer boat WB1 is moved / placed onto the rack 200, the wafers W are exposed to a space in the rack 200, which is fluidically connected to the environment and the exhaust system 230. The first wafer boat WB1 may include a label indicating the identity of the wafer W and may be used at various stages of the process. The first wafer boat WB1 may also be referred to as a wafer box.

[0096] In some embodiments of the present disclosure, a first gas removal process is performed by moving / positioning a wafer boat WB1 onto a rack 200 equipped with an exhaust system 230. The exhaust system 230 effectively removes fluorine-containing gas FG containing fluorine particles FP released from the wafers W. This suppresses the formation of crystals on the passivation window, thereby reducing liner defects. In these embodiments, the wafers W are positioned substantially along the direction Z on the wafer boat WB1, and the gas flow GF generated by the exhaust system 230 flows substantially along the direction Z. This configuration allows the gas flow GF to flow more uniformly across the wafers W. In the illustrated embodiment, the first wafer boat WB1 is moved onto the rack level 210A of the rack 200.

[0097] See also Figure 4D The method M proceeds to step S4, wherein the photoresist is removed from the wafer W by a dry stripping process. The photoresist layer PR is removed by a dry stripping process using a suitable gas, such as N2, O2, etc. or a combination thereof (see Figure 4C Before the photoresist is removed, the first wafer boat WB1 is moved away from the rack 200 (see Figure 4C ), and then the wafer W is taken from the first wafer boat WB1 (see Figure 4C ) is moved out to the chamber for a dry stripping process (ie, photoresist removal). After the photoresist is removed, photoresist residue PRR remains on the wafer W, that is, the residue of the photoresist layer PR (see Figure 4C ). In addition, fluoride will still remain in the sidewall polymer, the photoresist residue PRR and the metal liner 320, and the fluorine-containing gas FG will escape from the wafer W. Figure 4C ) uses the rack 200, so the amount of fluorine-containing gas FG escaping from the wafer W in this step is less than that in step S2 (see Figure 4B ) is the amount of fluorine-containing gas FG escaping from the wafer W.

[0098] See also Figure 4E , the method M proceeds to step S5, wherein the wafer W is placed on the first wafer boat WB1, the first wafer boat WB1 is moved / placed in the first wafer carrier 100A, and then the first wafer carrier 100A is moved / placed on the rack 200 for the second gas removal process. In the illustrated embodiment, the first wafer carrier 100A is moved / placed on the rack layer 210B of the rack 200. In this step, the space of the first wafer carrier 100A is opened through the openings 122O, 124O and 112O of the first wafer carrier 100A (and the openings 118O and 128O of the first wafer carrier 100A, as shown in FIG. Figure 1B As shown) is in fluid communication with the space of the rack layer 210B.

[0099] In some embodiments of the present disclosure, a second gas removal process is performed by moving or placing the first wafer carrier 100A onto a rack 200 equipped with an exhaust system 230. The exhaust system 230 effectively removes fluorine-containing gas FG containing fluorine particles FP released from the wafers W. This suppresses the formation of crystals on the passivation window, thereby reducing liner defects. In these embodiments, the wafers W are positioned substantially along the direction Z within the wafer carrier 100A, and the gas flow GF generated by the exhaust system 230 flows substantially along the direction Z. This configuration allows the gas flow GF to flow more uniformly across the wafers W.

[0100] After step S4 (i.e., removing the photoresist using a dry strip process) and step S5, method M may proceed to step S6, where the wafer W is inspected to check the condition of the photoresist residue PRR and the passivation layer 330 after the dry strip process. In some embodiments, the first wafer carrier 100A is removed from the rack 200 (see FIG. 1 ) before the inspection process. Figure 4E ), the first wafer boat WB1 is moved away from the first wafer carrier 100A (see Figure 4E ), and then the wafer W is taken from the first wafer boat WB1 (see Figure 4E ) is moved out to the chamber for inspection process.

[0101] See also Figure 4F The method M proceeds to step S7, wherein the photoresist is removed from the wafer W after the inspection process of step S6. The photoresist residue PRR is removed by a wet stripping process using a suitable gas such as NH2OH, H2O, etc. or a combination thereof (see Figure 4D After the wet stripping process, a small amount of fluoride may remain in the metal liner 320. Figure 4E ) uses the rack 200, so the amount of fluorine-containing gas escaping from the wafer W in this step is less than that in step S4 (see Figure 4D ) is the amount of fluorine-containing gas escaping from wafer W.

[0102] In some embodiments, the inspection process of step S6 may be omitted / skipped. In these embodiments, the first wafer carrier 100A is moved away from the rack 200 (see FIG. 1 ) before the photoresist is removed. Figure 4E ), the first wafer boat WB1 is moved away from the first wafer carrier 100A (see Figure 4E ), and then the wafer W is taken from the first wafer boat WB1 (see Figure 4E ) is moved out to a chamber for a wet stripping process (i.e., photoresist removal).

[0103] See also Figure 4G, the method M proceeds to step S8, wherein the wafer W is moved / placed onto the second wafer boat WB2. In this step, the wafer W is transported to the first wafer boat WB1 (see FIG. 1 ) used in the previous step. Figure 4E ) A second wafer boat WB2 is different. Using the second wafer boat WB2 can prevent the first wafer boat WB1 (see Figure 4E ) into subsequent processes.

[0104] Subsequently, method M enters step S9, wherein the second wafer boat WB2 is moved / placed into the second wafer carrier 100B, and then the second wafer carrier 100B is moved / placed onto the rack 200 for a third gas removal process. In some embodiments of the present disclosure, the second wafer carrier 100B is moved / placed onto the rack 200 by the exhaust system 230 for a third gas removal process, wherein the exhaust system 230 can effectively remove the fluorine-containing gas FG with fluorine particles FP released from the wafer W. Therefore, the generation of crystals on the passivation window can be suppressed. Therefore, the pad defects can be reduced. In the illustrated embodiment, the second wafer carrier 100B is moved onto the rack layer 210C of the rack 200. In this step, the space of the second wafer carrier 100B is opened via the openings 122O, 124O and 112O of the second wafer carrier 100B (and the openings 118O and 128O of the second wafer carrier 100B, as shown in FIG. Figure 1B 210C). In these embodiments, the wafers W are substantially positioned in the wafer carrier 100B along the direction Z, and the airflow GF generated by the exhaust system 230 flows substantially along the direction Z. With this configuration, the airflow GF can flow through the wafers W in a more uniform manner.

[0105] Then, the method M enters step S10, wherein the wafer W is inspected to check the condition of the photoresist and the passivation layer 330 after the wet stripping process. In some embodiments, before the inspection process, the second wafer carrier 100B is moved away from the rack 200 (see FIG. Figure 4G ), move the second wafer boat WB2 away from the second wafer carrier 100B (see Figure 4G ), and then the wafer W is taken from the second wafer boat WB2 (see Figure 4G ) is moved out to the chamber for inspection process.

[0106] After the inspection process is completed, method M may proceed to step S11, where an alloy is formed on the metal pad 320 exposed by the passivation layer 330. In some alternative embodiments, step S11 (alloy formation) may be skipped or omitted. Method M may then proceed to step S12, where a wafer acceptance test (WAT) is performed. The WAT can ensure the quality and stability of the wafer to a certain extent.

[0107] In some embodiments, see Figure 2A 、 Figure 4C 、 Figure 4E and Figure 4G Steps S3, S5, and S9 may utilize different rack levels 210A, 210B, and 210C of the same rack 200. For example, in step S3, the first wafer boat WB1 is moved or placed onto the first rack level 210A of the rack 200; in step S5, the first wafer carrier 100A is moved or placed onto the second rack level 210B of the rack 200; and in step S9, the second wafer carrier 100B is moved or placed onto the third rack level 210C of the rack 200. In other words, different rack levels 210A, 210B, and 210C may accommodate wafer boats or wafer carriers in different steps of method M. In some alternative embodiments, steps S3, S5, and S9 utilize different racks 200. In some alternative embodiments, steps S3 , S5 , and S9 use the same rack layer 210 of the same rack 200 (eg, one of the rack layers 210A, 210B, and 210C of the same rack 200 ).

[0108] Figure 5A FIG. 1 is a schematic diagram of a wafer carrier 100 containing a wafer W according to some embodiments of the present disclosure. Figure 5B for Figure 5A 1. The top view of the wafer carrier 100. When viewed from the top, the opening 122O of the top cover plate 122 is offset from the wafer W in the wafer carrier 100. For example, the opening 122O of the top cover plate 122 is offset from the center of the top cover plate 122. Figure 5A As shown, the opening 122O of the top cover plate 122 does not expose the wafer boat WB carrying the wafers W. This configuration prevents particles from the environment from falling onto the wafers W in the wafer carrier 100. The opening 122O of the top cover plate 122 has a longitudinal direction substantially parallel to a direction substantially parallel to the surface of the wafer W (e.g., direction X). In some embodiments, the long side LS of the opening 122O is smaller than the diameter of the wafer W. The number of wafers W supported by the wafer boat WB2 and placed in the second wafer carrier 100B is shown in the figure for illustrative purposes only and may vary depending on various circumstances.

[0109] Figure 5C exhibit Figure 5A The wafer carrier 100 is disposed vertically on the side AS of the wafer carrier 100. The wafer W can be placed vertically in the wafer carrier 100. The openings 124O of the two opposing side covers 124 can expose a portion of the wafer boat WB and the edge portions of the wafer W, thereby facilitating the removal of fluorine-containing gas from the wafer W. In some embodiments, the long side LS of the opening 124O is much larger than the thickness of the wafer W, so that multiple edge portions of the wafer W can be exposed by the opening 124O.

[0110] Figure 5Dexhibit Figure 5A The back side BS of the wafer carrier 100 is shown. The wafer W can be vertically arranged in the wafer carrier 100. The openings 118O and 128O can expose portions of the wafer W, thereby facilitating the removal of fluorine-containing gas from the wafer W. The opening 128O of the rear cover plate 128 and / or the opening 118O of the rear box plate 118 can have a longitudinal direction substantially parallel to the direction (e.g., direction X). In some embodiments, the long side LS1 of the opening 128O is smaller than the diameter of the wafer W. In some embodiments, the long side LS2 of the opening 118O is smaller than the diameter of the wafer W. The number of wafers W supported by the wafer boat WB2 and placed in the second wafer carrier 100B is shown in the figure for illustration only and may vary according to various circumstances.

[0111] Figure 5E exhibit Figure 5A 1 is a bottom view of the wafer carrier 100. The wafer W may be vertically disposed in the wafer carrier 100. The opening 112O may expose the wafer W, thereby facilitating removal of the fluorine-containing gas from the wafer W. For example, the opening 112O may overlap with an area of ​​the wafer boat WB.

[0112] Figure 6A The vertical axis represents the fluorine content on the wafer surface. Condition #1 represents the fluorine content on the wafer surface of wafer W before the degassing function is performed, for example, without using the degassing function in the process. Figures 1A to 1F Wafer carrier 100 and Figure 2A and Figure 2B Condition #2 represents the fluorine content on the wafer surface of the wafer W after the degassing function is performed, for example, in the process using Figures 1A to 1F Wafer carrier 100 and Figure 2A and Figure 2B Rack 200.

[0113] Comparing Condition 2 with Condition 1, the fluorine content of Condition 2 is much lower than that of Condition 1. This indicates that the implementation of the degassing function (e.g., using Figures 1A to 1F Wafer carrier 100 and / or Figure 2A and Figure 2B The rack 200) can significantly reduce the fluorine content on the wafer surface.

[0114] Figure 6B The figure illustrates the failure rate across multiple wafers according to some embodiments of the present disclosure. The vertical axis represents the failure rate in parts per million (ppm) across the wafer surface. The horizontal axis represents the timing of when the degas function was performed. Condition #1 represents the timing before the degas function was performed, and Condition #2 represents the timing after the degas function was performed.

[0115] Comparing condition #2 with condition #1, the failure rate of condition #2 is much lower than that of condition #1. This indicates that the implementation of the degassing function (e.g., using Figures 1A to 1F Wafer carrier 100 and / or Figure 2A and Figure 2B Rack 200) can significantly reduce the failure rate.

[0116] Based on the above discussion, it can be seen that the embodiments of the present disclosure provide advantages. However, it should be understood that other embodiments may provide additional advantages, and not all advantages must be disclosed here, and all embodiments do not require specific advantages. One advantage is that the wafer carrier is designed with openings that allow fluorine-containing gases to be peeled off from the wafer and escape to other places, thereby preventing fluorine-containing gases from escaping from exposed AlCu, thereby reducing the formation of pad defects. Another advantage is that the shape and size of the opening of the wafer carrier can be adjusted and determined according to practice to optimize the production steps. Another advantage is that the rack is designed with a rack layer with multiple holes and an exhaust system connected to the rack layer fluid, which is conducive to removing fluorine-containing gases escaping from the wafer.

[0117] According to some embodiments of the present disclosure, a method for processing a wafer is provided. The method includes forming a photoresist layer above a passivation layer on a wafer; etching an opening in the passivation layer; after etching the opening in the passivation layer, moving the wafer into a first wafer carrier, wherein the first wafer carrier has a first box and a first cover pivotally connected to the first box, and one of the first box and the first cover has an opening; and performing a first gas removal process to remove gas released by the wafer from the first wafer carrier through the opening in the first box and the first cover.

[0118] In some embodiments, the first gas removal process uses an exhaust system to direct the gas from the first wafer carrier.

[0119] In some embodiments, the first gas removal process includes moving the first wafer carrier onto a rack level; and directing the gas from the rack level using an exhaust system.

[0120] In some embodiments, the method further includes performing a dry stripping process to remove the photoresist layer from the passivation layer after etching the layer opening in the passivation layer and before moving the wafer into the first wafer carrier.

[0121] In some embodiments, the method further includes performing a wet stripping process after the first gas removal process to remove the photoresist layer from the passivation layer.

[0122] In some embodiments, the method further includes, after etching the layer opening in the passivation layer, moving the wafer into a second wafer carrier, wherein the second wafer carrier has a second box body and a second cover pivotally connected to the second box body, and one of the second box body and the second cover has an opening; and after the wet stripping process, performing a second gas removal process to remove the gas released from the wafer from the second wafer carrier through the opening of one of the second box body and the second cover.

[0123] In some embodiments, the second gas removal process includes moving the second wafer carrier onto a rack level; and directing the gas from the rack level using an exhaust system.

[0124] In some embodiments, a step of etching an opening in the passivation layer is performed such that the opening in the passivation layer exposes a metal pad on the wafer.

[0125] According to some embodiments of the present disclosure, a method for processing a wafer is provided, comprising: moving a wafer into a wafer carrier, wherein the wafer stands substantially vertically in the wafer carrier, and the wafer carrier has at least one opening; moving the wafer carrier onto a rack level of a rack, wherein a space in the wafer carrier is in fluid communication with a space in the rack level via the at least one opening in the wafer carrier; and generating airflow substantially vertically in the rack level of the rack using an exhaust system.

[0126] In some embodiments, when the airflow is generated, the wafer carrier is moved to the rack level of the rack.

[0127] In some embodiments, after the wafer is moved into the wafer carrier, the wafer is located above the opening of the wafer carrier.

[0128] In some embodiments, the opening of the wafer carrier is aligned with the wafer along the vertical direction.

[0129] In some embodiments, after the wafer is moved into the wafer carrier, the wafer is located below the opening of the wafer carrier.

[0130] In some embodiments, the opening of the wafer carrier is staggered with respect to the wafer along the vertical direction.

[0131] In some embodiments, the step of moving the wafer into the wafer carrier includes placing the wafer on a wafer boat; and moving the wafer boat into the wafer carrier.

[0132] According to some embodiments of the present disclosure, a wafer processing tool includes a wafer carrier and a rack. The wafer carrier includes a box body and a cover body located above the box body. The box body is used to accommodate a wafer boat. The box body includes a bottom box plate, and the bottom box plate has a first opening. The cover body includes a top cover plate spaced apart from the bottom box plate in a vertical direction, and the top cover plate has a second opening, and the second opening of the top cover plate is staggered in the vertical direction with respect to the wafer boat. The rack includes a plurality of rack layers, wherein each of the plurality of rack layers has a bottom plate, the bottom plate having a plurality of bottom plate openings, and one of the plurality of rack layers is used to accommodate the wafer carrier.

[0133] In some embodiments, the second opening of the top cover plate and the first opening of the bottom box plate are staggered along the vertical direction.

[0134] In some embodiments, the cover includes a side cover extending from the top cover toward the box body, and the side cover includes a third opening.

[0135] In some embodiments, the wafer processing tool further includes an exhaust system connected to the lowest layer of the plurality of rack layers and configured to generate an airflow between the plurality of rack layers through the plurality of bottom plate openings.

[0136] In some embodiments, the rack includes a ceiling located above the topmost layer of the plurality of rack layers, and the ceiling has a plurality of ceiling openings.

[0137] According to some embodiments of the present disclosure, a wafer carrier includes a box body and a cover body. The box body is used to accommodate a wafer boat. The cover body is pivotally connected to the box body, wherein one of the box body and the cover body has a first opening.

[0138] In some embodiments, the other of the box body and the cover body has a second opening.

[0139] In some embodiments, a depth-to-width ratio of a long side to a short side of the first opening is greater than a depth-to-width ratio of a long side to a short side of the second opening.

[0140] According to some embodiments of the present disclosure, a wafer processing tool includes a rack and an exhaust system. The rack includes a plurality of rack levels, wherein each of the rack levels has a bottom plate with a plurality of bottom plate openings, and one of the rack levels is configured to accommodate a wafer carrier. The exhaust system is connected to a lowest level of the rack levels and configured to generate an airflow between the rack levels through the bottom plate openings.

[0141] In some embodiments, the rack includes a ceiling located above the topmost layer of the plurality of rack layers, and the ceiling has a plurality of ceiling openings.

[0142] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will understand that they can easily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications may be made to these equivalent constructions without departing from the spirit and scope of the present disclosure.

Claims

1. A wafer carrier, characterized in that: Include: a box body for accommodating a wafer boat; and A cover is pivotally connected to the box body, wherein one of the box body and the cover has a first opening.

2. The wafer carrier according to claim 1, wherein: The other one of the box body and the cover body has a second opening.

3. The wafer carrier according to claim 2, wherein: The aspect ratio of the long side to the short side of the first opening is greater than the aspect ratio of the long side to the short side of the second opening.

4. A wafer processing tool, characterized in that Include: A rack comprising a plurality of rack layers, wherein each of the plurality of rack layers has a bottom plate having a plurality of bottom plate openings, and one of the plurality of rack layers is used to accommodate a wafer carrier; and An exhaust system is connected to the lowest layer of the plurality of rack layers and is used to generate an airflow between the plurality of rack layers through the plurality of bottom plate openings.

5. The wafer processing tool according to claim 4, wherein: The rack includes a ceiling located above the topmost layer of the multiple rack layers, and the ceiling has a plurality of ceiling openings.

6. A wafer processing tool, characterized in that: Include: A wafer carrier, comprising: A box body for accommodating a wafer boat, wherein the box body comprises a bottom box plate, and the bottom box plate has a first opening; and a cover body located above the box body, wherein the cover body includes a top cover plate spaced apart from the bottom box plate along a vertical direction, the top cover plate having a second opening, and the second opening of the top cover plate is staggered with the wafer boat along the vertical direction; and A rack comprises a plurality of rack layers, wherein each of the plurality of rack layers has a bottom plate with a plurality of bottom plate openings, and one of the plurality of rack layers is used to accommodate the wafer carrier.

7. The wafer processing tool according to claim 6, wherein: The second opening of the top cover plate and the first opening of the bottom box plate are staggered along the vertical direction.

8. The wafer processing tool according to claim 6, wherein: The cover body includes a side cover plate extending from the top cover plate toward the box body, and the side cover plate includes a third opening.

9. The wafer processing tool according to claim 6, wherein: Also includes: An exhaust system is connected to the lowest layer of the plurality of rack layers and is used to generate an airflow between the plurality of rack layers through the plurality of bottom plate openings.

10. The wafer processing tool according to claim 9, wherein: The rack includes a ceiling located above the topmost layer of the multiple rack layers, and the ceiling has a plurality of ceiling openings.

Images