Charging pile power-down master control power supply voltage holding circuit

Abstract

The utility model discloses a charging pile power-down master control power supply voltage holding circuit. The circuit comprises an energy storage farad capacitor C1, a power supply monitoring controller U1 and a synchronous boost controller U2, wherein the power supply monitoring controller U1 and the synchronous boost controller U2 are used for being connected with the power supply output end of a charging pile; by means of real-time detection and judgment of a power monitoring controller U1, when the power voltage of the power output end of the charging pile is reduced to a certain low voltage or is zero, the enabling end of a synchronous boost controller U2 is changed into a high level through charging of a farad capacitor C1 under the normal power voltage, the synchronous boost controller U2 works, voltage VOUT is output for a charging pile master control (CPU) to work, and the charging pile master control (CPU) works. The charging pile master control (CPU) can maintain a period of time to timely store charging data when the power supply voltage of the charging pile is reduced to a certain low voltage or zero, and the safety and convenience of the charging data of the charging pile are improved.

Description

Technical Field

[0001] The utility model relates to a main control power supply voltage maintaining circuit for a charging pile when power is lost, belonging to the technical field of charging piles. Background Art

[0002] With the increasing number of new energy electric vehicles, the number of AC and DC charging piles installed and operated in society is increasing. However, during the operation of the charging pile, if a sudden power outage occurs, the charging power and other data of the charging pile will be lost, which will cause losses to the charging pile operator and users. Therefore, the charging pile main control (CPU) needs to be able to work for a period of time after the charging pile loses power so that the charging pile main control (CPU) can store the charging data in time. This requires that the power supply voltage of the charging pile main control (CPU) can be maintained for a period of time after the charging pile loses power. Therefore, being able to maintain the power supply voltage of the charging pile main control (CPU) for a certain period of time after the charging pile loses power is of great significance in practical applications. Utility Model Content

[0003] The utility model provides a charging pile power-off main control power supply voltage maintaining circuit, which can maintain the charging pile main control power supply voltage for a period of time after the charging pile suddenly loses power, so that the charging pile main control can store data such as charging power in time to avoid losses.

[0004] In order to achieve the above-mentioned purpose / solve the above-mentioned technical problems, the present invention is implemented by adopting the following technical solutions.

[0005] On the one hand, the utility model provides a charging pile power-off main control power supply voltage maintenance circuit, comprising: an energy storage farad capacitor C1 and a power monitoring controller U1 and a synchronous boost controller U2 for connecting to the charging pile power output terminal;

[0006] The charging pile power output end is connected to the VCC power supply end of the power monitoring controller U1, the RST reset end of the power monitoring controller U1 is connected to the base of the transistor Q1, the collector of the transistor Q1 is connected to the EN enable end of the synchronous boost controller U2, and the emitter of the transistor Q1 and the GND end of the power monitoring controller U1 are grounded;

[0007] The power output end of the charging pile is connected to the positive electrode of the diode V1, the negative electrode of the diode V1 is connected to one end of the resistor R1, the other end of the resistor R1 is respectively connected to the positive electrode of the farad capacitor C1, one end of the capacitor C2, one end of the resistor R3 and the IN power input end of the synchronous boost controller U2, the other end of the resistor R3 is connected to the collector of the transistor Q1, and the negative electrode of the farad capacitor C1 and the other end of the capacitor C2 are grounded;

[0008] The OUT output terminal of the synchronous boost controller U2 is used to connect to the charging pile main control power supply voltage input terminal VDD, and the AGND terminal of the synchronous boost controller U2 is grounded.

[0009] Furthermore, the other end of the resistor R1 is connected to one end of the inductor L1, the other end of the inductor L1 is respectively connected to the switch node SW end of the synchronous boost controller U2 and one end of the resistor R2, the other end of the resistor R2 is connected to the capacitor C3 and then grounded, the inductor L1 is the energy storage inductor of the DCDC synchronous boost control integrated circuit U2, and the resistor R2 and the capacitor C3 are used to absorb high-frequency interference from the switch node SW end.

[0010] Furthermore, resistors R4, R5, and capacitor C4 are connected between the power output terminal of the charging pile and the VCC power terminal of the power monitoring controller U1. Capacitor C4 is a decoupling capacitor, which has two functions: on the one hand, it serves as an energy storage capacitor for the power monitoring controller U1, and on the other hand, it bypasses the high-frequency noise of the device.

[0011] The power output end of the charging pile is connected to one end of the resistor R4, and the other end of the resistor R4 is respectively connected to one end of the resistor R5, one end of the capacitor C4 and the VCC end of the power monitoring controller U1. The other end of the resistor R5 and the other end of the capacitor C4 are grounded. The resistor R4 is a current limiting resistor, and the resistor R5 is a discharge resistor of the capacitor C4. When the power supply of the charging pile is cut off, the power on the capacitor C4 is quickly discharged, so that the power monitoring controller U1 can work quickly.

[0012] Furthermore, resistors R7 and R8 are connected in sequence between the OUT output terminal and the AGND terminal of the synchronous boost controller U2, and the FB output voltage feedback terminal of the synchronous boost controller U2 is connected between the resistors R7 and R8. Resistors R7 and R8 are output voltage sampling feedback, and the feedback is input into the FB output voltage feedback terminal of the synchronous boost controller U2 to control the output voltage +VOUT to a stable constant value.

[0013] Furthermore, the OUT output terminal of the synchronous boost controller U2 is also connected to one end of a capacitor C5 and one end of a capacitor C6, and the other end of the capacitor C5 and the other end of the capacitor C6 are grounded. The capacitors C5 and C6 are output filter capacitors.

[0014] Furthermore, a diode V2 is provided between the OUT output terminal of the synchronous boost controller U2 and the main power supply voltage input terminal VDD of the charging pile. The OUT output terminal of the synchronous boost controller U2 is connected to the positive pole of the diode V2, and the negative pole of the diode V2 is used to connect to the main power supply voltage terminal VDD of the charging pile. The diode V2 has a function to prevent voltage backflow.

[0015] Furthermore, the power supply monitoring controller U1 is IM809SEUR.

[0016] Furthermore, the synchronous boost controller U2 is MP3414A.

[0017] Compared with the prior art, the beneficial effects achieved by the present invention are as follows: the present invention utilizes the real-time detection and judgment of the power monitoring controller U1. When the power supply voltage at the output end of the charging pile power supply drops to a certain low voltage or is zero, the enable end of the synchronous boost controller U2 becomes a low level, so that the synchronous boost controller U2 works, and the output voltage VOUT is supplied to the charging pile main control (CPU). Since the farad capacitor C1 is charged at a normal power supply voltage, the farad capacitor C1 has a large capacitance and the voltage on it is maintained for a long time after charging, so that the output voltage VOUT of the synchronous boost controller U2 is maintained for a long time, so that the charging pile main control (CPU) can maintain the charging data for a period of time when the power supply voltage of the charging pile drops to a certain low voltage or is zero, thereby improving the safety and convenience of the charging data of the charging pile. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a schematic diagram of the principle of the holding circuit of the utility model;

[0019] Figure 2 This is the block diagram of the power-off retention circuit system. DETAILED DESCRIPTION

[0020] The technical solution of the present invention is described in detail below through the accompanying drawings and specific embodiments. It should be understood that the embodiments of the present invention and the specific features in the embodiments are detailed descriptions of the technical solution of the present invention, rather than limitations on the technical solution of the present invention. In the absence of conflict, the embodiments of the present invention and the technical features in the embodiments can be combined with each other.

[0021] The term "and / or" simply describes a relationship between related objects, indicating that three possible relationships exist. For example, "A and / or B" can mean: A exists alone, A and B exist simultaneously, or B exists alone. Additionally, the character " / " generally indicates an "or" relationship between the related objects. Example

[0022] like Figure 1 An embodiment shown in the figure provides a charging pile power-off main control power supply voltage maintenance circuit, including a diode V1, a diode V2, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a farad capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, a power monitoring controller U1, a synchronous boost controller U2, a transistor Q1 and an inductor L1. The power monitoring controller U1 is IM809SEUR; the synchronous boost controller U2 is MP3414A;

[0023] The positive electrode of diode V1 is connected to the output voltage +V of the charging pile power supply, the negative electrode of diode V1 is connected to one end of resistor R1, the other end of resistor R1 is connected to the positive electrode of farad capacitor C1, one end of capacitor C2, one end of inductor L1, one end of resistor R3 and the power input 1 pin of synchronous boost controller U2, the negative electrode of farad capacitor C1 and the other end of capacitor C2 are connected to the power ground, the other end of inductor L1 is connected to one end of resistor R2 and the switch node 3 pin of synchronous boost controller U2, and the other end of resistor R2 is connected to one end of capacitor C3 The other end of capacitor C3 is connected to the power ground. The voltage output pin 2 of the synchronous boost controller U2 is connected to one end of resistor R7, one end of capacitor C5, one end of capacitor C6, and the positive electrode of diode V2. The other end of resistor R7 is connected to the feedback input pin 7 of synchronous boost controller U2 and one end of resistor R8. The other end of resistor R8 is connected to the ground pin 6 of synchronous boost controller U2 to the power ground. The other end of capacitor C5 and the other end of capacitor C6 are connected to the power ground. The negative electrode of diode V2 is connected to the charging pile main control (CPU) power supply VDD.

[0024] One end of the resistor R4 is connected to the charging pile power supply output voltage +V, the other end of the resistor R4 is connected to one end of the resistor R5, one end of the capacitor C4 and the power input 3 pin of the power monitoring controller U1, the other end of the resistor R5 and the other end of the capacitor C4 are connected to the ground 1 pin of the power monitoring controller U1 and the power ground, the reset output 2 pin of the power monitoring controller U1 is connected to one end of the resistor R6, the other end of the resistor R6 is connected to the base of the transistor Q1, the emitter of the transistor Q1 is grounded, and the collector of the transistor Q1 is connected to the other end of the resistor R3 and the enable terminal 8 pin of the synchronous boost controller U2.

[0025] like Figure 2 As shown, when the charging pile is working, the charging pile power supply is connected to the charging pile power-off main control power supply voltage holding circuit input end and the charging pile power-off main control power supply input end of the present application, and the charging pile power-off main control power supply voltage holding circuit output end is connected to the charging pile power-off main control source input end;

[0026] When the output voltage +V of the charging pile power supply is stable or higher than the voltage VCC threshold of the power supply pin 3 of the power supply monitoring controller U1, the reset pin 2 of the power supply monitoring controller U1 outputs a high level, and the current is limited to the base of the transistor Q1 through the resistor R6. Due to the high level of the base, the transistor Q1 is turned on, and the collector of the transistor Q1 is low, so that the enable pin 8 of the synchronous boost controller U2 is low. Then the synchronous boost controller U2 does not work and has no output, that is, the output voltage +VOUT is zero. The main control (CPU) power supply voltage holding circuit of this charging pile does not work when it is powered off.

[0027] When the output voltage +V of the charging pile power supply drops below the voltage VCC threshold of the power supply pin 3 of the power supply monitoring controller U1 or is suddenly powered off to zero, the reset pin 2 of the power supply monitoring controller U1 outputs a low level, and the transistor Q1 is cut off due to the low base level, and the enable pin 8 of the synchronous boost controller U2 is pulled up to a high level through the resistor R3, so that the synchronous boost controller U2 works normally, and the output voltage +VOUT is output to the charging pile main control (CPU) power supply voltage VDD through the diode V2. Since the farad capacitor C1 has a large capacity and a lot of energy storage, the voltage +VIN can be maintained for a period of time, and the output voltage +VOUT can be maintained for a period of time, so that the charging pile main control (CPU) power supply voltage VDD is maintained for a period of time, so that the charging pile main control (CPU) can work normally for a period of time when the charging pile power supply voltage is reduced or the power is cut off, so that the charging pile can store charging data in time when the voltage is reduced or the power is cut off.

[0028] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the purpose of the present invention and the claims, which are all within the protection of the present invention.

Claims

1. A charging pile power failure main control power supply voltage maintenance circuit, characterized in that: include: Energy storage capacitor C1 and power monitoring controller U1 and synchronous boost controller U2 for connecting to the power output of the charging pile; The charging pile power output end is connected to the VCC power supply end of the power monitoring controller U1, the RST reset end of the power monitoring controller U1 is connected to the base of the transistor Q1, the collector of the transistor Q1 is connected to the EN enable end of the synchronous boost controller U2, and the emitter of the transistor Q1 and the GND end of the power monitoring controller U1 are grounded; The power output end of the charging pile is connected to the positive electrode of the diode V1, the negative electrode of the diode V1 is connected to one end of the resistor R1, the other end of the resistor R1 is respectively connected to the positive electrode of the farad capacitor C1, one end of the capacitor C2, one end of the resistor R3 and the IN power input end of the synchronous boost controller U2, the other end of the resistor R3 is connected to the collector of the transistor Q1, and the negative electrode of the farad capacitor C1 and the other end of the capacitor C2 are grounded; The OUT output terminal of the synchronous boost controller U2 is used to connect to the charging pile main control CPU power supply VDD, and the AGND terminal of the synchronous boost controller U2 is grounded.

2. The charging pile power-off main control power supply voltage maintaining circuit according to claim 1, characterized in that: The other end of the resistor R1 is connected to one end of the inductor L1 , the other end of the inductor L1 is respectively connected to the switch node SW of the synchronous boost controller U2 and one end of the resistor R2 , and the other end of the resistor R2 is connected to the capacitor C3 and then grounded.

3. The charging pile power-off main control power supply voltage maintaining circuit according to claim 1, characterized in that: Resistors R4, R5 and C4 are connected between the power output terminal of the charging pile and the VCC terminal of the power monitoring controller U1. The charging pile power output end is connected to one end of the resistor R4, and the other end of the resistor R4 is respectively connected to one end of the resistor R5, one end of the capacitor C4 and the VCC power supply end of the power monitoring controller U1, and the other end of the resistor R5 and the other end of the capacitor C4 are grounded.

4. The charging pile power-off main control power supply voltage maintaining circuit according to claim 1, characterized in that: The resistors R7 and R8 are connected in sequence between the OUT output terminal and the AGND terminal of the synchronous boost controller U2 , and the FB output feedback terminal of the synchronous boost controller U2 is connected between the resistors R7 and R8 .

5. The charging pile power-off main control power supply voltage maintaining circuit according to claim 1, characterized in that: The OUT output terminal of the synchronous boost controller U2 is further connected to one end of the capacitor C5 and one end of the capacitor C6, and the other end of the capacitor C5 and the other end of the capacitor C6 are grounded.

6. The charging pile power-off main control power supply voltage maintaining circuit according to claim 1, characterized in that: A diode V2 is set between the OUT output end of the synchronous boost controller U2 and the charging pile main control CPU power supply voltage VDD. The OUT output end of the synchronous boost controller U2 is connected to the positive electrode of the diode V2, and the negative electrode of the diode V2 is used to connect to the charging pile main control CPU power supply voltage VDD.

7. The charging pile power-off main control power supply voltage maintaining circuit according to claim 1, characterized in that: The power supply monitoring controller U1 is IM809SEUR.

8. The charging pile power-off main control power supply voltage maintaining circuit according to claim 1, characterized in that: The synchronous boost controller U2 is MP3414A.

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