Multilayer ceramic plate

Abstract

The utility model provides a multilayer ceramic plate which comprises a ceramic substrate, a plurality of resistor bodies are arranged on the upper surface of the ceramic substrate, and insulating layers are filled among the resistor bodies. The resistor body comprises a plurality of stacked metal film layers, an interconnection line layer is arranged between every two adjacent metal film layers, and each interconnection line layer comprises at least one interconnection line through hole; and the orthographic projections of the edges of all the metal film layers of the same resistor body on the surface of the ceramic substrate are completely overlapped. The utility model provides a multilayer ceramic plate which can be used for manufacturing a high-density resistor body and improving the yield.

Description

Technical Field

[0001] The utility model belongs to the technical field of semiconductors, and in particular relates to a multi-layer ceramic plate. Background Art

[0002] A probe card is a key component used in front-end semiconductor wafer testing, establishing an electrical connection between the wafer chip and the tester. It consists of multiple probes that test the electrical properties of the wafer chip by contacting it. The ceramic board is the core component of the probe card. As the number of probes increases and the size of the ceramic board increases, multiple layers of metal film are required to ensure resistance and bonding space for the probes. When forming multiple layers of metal film, an insulating layer must be formed between adjacent metal film layers. Interconnection line holes are prepared in the insulating layer to enable electrical connection between adjacent metal film layers, thus forming a multilayer ceramic board.

[0003] However, the metal film layers of existing multilayer ceramic boards are staggered, resulting in each resistor occupying a large space. Furthermore, the diameter of the interconnect vias is typically 60µm. Under current copper plating processes, a copper layer at least 25µm thick must be formed to avoid plating dishing. Utility Model Content

[0004] The utility model provides a multi-layer ceramic plate, which can be used to manufacture high-density resistors and improve the yield rate.

[0005] In order to solve the above technical problems, the embodiment of the present utility model provides a multi-layer ceramic plate, such as Figure 1 As shown, it includes a ceramic substrate, the upper surface of which is provided with a plurality of resistors, and an insulating layer is filled between the resistors; the resistors include a plurality of stacked metal film layers, and an interconnection layer is provided between adjacent metal film layers, and the interconnection layer includes at least one interconnection through-hole; the orthographic projections of the edges of all metal film layers of the same resistor on the surface of the ceramic substrate completely overlap.

[0006] As a further improvement of the present invention, the orthographic projections of the edges of all interconnection line layers of the same resistor on the surface of the ceramic substrate completely overlap.

[0007] As a further improvement of the present invention, the center line of the interconnection line layer of the same resistor body coincides with the center line of the metal film layer.

[0008] As a further improvement of the present invention, there are two interconnection line through holes.

[0009] As a further improvement of the present invention, there are three interconnection through holes, and the three interconnection through holes are sequentially connected at the center points of the orthographic projections of the surface of the ceramic substrate to form an equilateral triangle.

[0010] As a further improvement of the present invention, the diameter of the interconnection line through hole is 20 to 30 μm.

[0011] As a further improvement of the present invention, the cross section of the interconnection line through hole is circular.

[0012] As a further improvement of the present invention, a copper layer, a nickel layer and a gold layer are stacked in sequence from bottom to top on the bottom of the interconnection line through hole.

[0013] As a further improvement of the present invention, the insulating layer is formed by non-photosensitive polyimide.

[0014] As a further improvement of the present invention, the insulating layer is formed by photosensitive polyimide.

[0015] Compared with the prior art, the technical solution of the utility model has the following beneficial effects:

[0016] The embodiment of the present invention provides a multilayer ceramic plate, in which the edges of all metal film layers of the same resistor body completely overlap in their orthographic projections on the surface of the ceramic substrate, that is, all metal film layers are arranged in an upper and lower corresponding overlapping manner without misalignment, thereby reducing the space for a single resistor body, and more resistor bodies can be formed on a ceramic substrate of the same size, thereby obtaining a multilayer ceramic plate with a high-density resistor body. The embodiment of the present invention provides a multilayer ceramic plate, which reduces the diameter of the interconnection line through-hole, thereby reducing the thickness of the copper plating layer, improving the plating filling performance, and improving the yield. The embodiment of the present invention provides a multilayer ceramic plate, in which three interconnection line through-holes are provided in the interconnection line layer, thereby increasing the connection area. Even if one of the interconnection line through-holes has a poor connection, the resistor body will not have an open circuit failure, thereby reducing the electrical open circuit failure rate caused by the poor interconnection line through-hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is a schematic structural diagram of a multilayer ceramic plate according to an embodiment of the present invention;

[0018] Figure 2 yes Figure 1 Cross-section of a single resistor.

[0019] The figure includes: a ceramic substrate 1 , a metal film layer 2 , an interconnection layer 3 , interconnection vias 31 , and an insulating layer 4 . DETAILED DESCRIPTION

[0020] The technical solution of the present utility model is described in detail below with reference to the accompanying drawings.

[0021] The present invention provides a multi-layer ceramic plate. Figure 1As shown, it includes a ceramic substrate 1, and a plurality of resistor bodies are provided on the upper surface of the ceramic substrate 1, and an insulating layer 4 is filled between the resistor bodies. The resistor body includes a plurality of stacked metal film layers 2, and an interconnection layer 3 is provided between adjacent metal film layers 2. The interconnection layer 3 includes at least one interconnection through-hole 31. Preferably, the cross-section of the interconnection through-hole 31 is circular. The inner wall of the interconnection through-hole is plated with a copper layer. The orthographic projections of the edges of all metal film layers 2 of the same resistor body on the surface of the ceramic substrate completely overlap, that is, each metal film layer 2 has the same shape and size, and all metal film layers 2 are arranged overlapping from top to bottom.

[0022] In the multilayer ceramic board of this embodiment, the orthographic projections of the edges of all metal film layers of the same resistor on the surface of the ceramic substrate completely overlap, that is, all metal film layers are stacked without misalignment, which reduces the space for a single resistor. More resistors can be formed on a ceramic substrate of the same size, resulting in a multilayer ceramic board with a high-density resistor.

[0023] Preferably, the orthographic projections of the edges of all interconnect layers 3 of the same resistor on the surface of the ceramic substrate completely overlap. Each interconnect layer 3 has the same shape and size, and all interconnect layers 3 are arranged overlapping from top to bottom. Further preferably, the centerline of the interconnect layer 3 of the same resistor coincides with the centerline of the metal film layer 2.

[0024] Preferably, there are two interconnection line through holes 31 .

[0025] Or, preferably, Figure 2 As shown, there are three interconnection vias 31, which are connected sequentially at the center of their orthographic projections on the ceramic substrate surface to form an equilateral triangle. In this embodiment, three interconnection vias are provided in the interconnect layer to increase the connectivity area. Furthermore, even if one of the interconnection vias fails, the resistor will not experience an open circuit failure, thus reducing the electrical open failure rate caused by a failed interconnection via.

[0026] Preferably, the diameter of the interconnection line through hole 31 is 20-30 μm. This embodiment reduces the diameter of the interconnection line through hole, thereby reducing the thickness of the copper plating layer, improving the plating filling performance, and improving the yield rate.

[0027] In order to prevent the lower metal film layer from being damaged or adsorbed due to heat, preferably, the bottom of the interconnection line through hole is stacked with a copper layer, a nickel layer and a gold layer in sequence from bottom to top to prevent the formation of an oxide film.

[0028] Preferably, the insulating layer 4 is formed of non-photosensitive polyimide. If the insulating layer 4 is formed of non-photosensitive polyimide, an ultraviolet laser etching process is used to prepare the interconnection line through-holes.

[0029] Alternatively, preferably, the insulating layer 4 is formed of photosensitive polyimide. If the insulating layer 4 is formed of photosensitive polyimide, a photolithography process can be used to prepare the interconnection line through-holes, thereby improving the position accuracy of the interconnection line through-holes.

[0030] The above is only a specific implementation method of the present invention, but the protection scope of the present invention is not limited to this. Any changes or replacements that can be easily thought of by any technician familiar with this technical field within the technical scope disclosed in the present invention should be included in the protection scope of the present invention.

Claims

1. A multilayer ceramic board, characterized in that: The invention comprises a ceramic substrate (1), wherein the upper surface of the ceramic substrate (1) is provided with a plurality of resistor bodies, and an insulating layer (4) is filled between the resistor bodies; the resistor body comprises a plurality of stacked metal film layers (2), an interconnection layer (3) is provided between adjacent metal film layers (2), and the interconnection layer (3) comprises at least one interconnection through hole; and the orthographic projections of the edges of all metal film layers (2) of the same resistor body on the surface of the ceramic substrate completely overlap.

2. The multilayer ceramic board according to claim 1, wherein The orthographic projections of the edges of all interconnection line layers (3) of the same resistor body on the surface of the ceramic substrate completely overlap.

3. The multilayer ceramic board according to claim 2, characterized in that The center line of the interconnection line layer (3) of the same resistor body coincides with the center line of the metal film layer (2).

4. The multilayer ceramic board according to claim 1, wherein There are two interconnection line through holes (31).

5. The multilayer ceramic board according to claim 1, characterized in that There are three interconnection line through holes (31), and the three interconnection line through holes (31) are sequentially connected at the center points of the orthographic projections of the surface of the ceramic substrate to form an equilateral triangle.

6. The multilayer ceramic board according to claim 5, characterized in that The diameter of the interconnection line through hole (31) is 20 to 30 μm.

7. The multilayer ceramic board according to claim 1, wherein The cross section of the interconnection line through hole (31) is circular.

8. The multilayer ceramic board according to claim 1, wherein The bottom of the interconnection line through hole (31) is stacked with a copper layer, a nickel layer and a gold layer in sequence from bottom to top.

9. The multilayer ceramic board according to claim 1, wherein The insulating layer (4) is formed by non-photosensitive polyimide.

10. The multilayer ceramic board according to claim 1, wherein The insulating layer (4) is formed by photosensitive polyimide.

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