Reference circuit, driving chip and display device

Abstract

The embodiment of the utility model provides a reference circuit, a driving chip and a display device, and relates to the technical field of display screens. The reference circuit is small in area and low in power consumption. The reference circuit comprises an impedance circuit, a first current mirror circuit and a temperature stabilizing circuit; the first end of the first current mirror circuit is electrically connected with a first voltage end, and the second end of the first current mirror circuit is electrically connected with the first end of the impedance circuit; the first end of the temperature stabilizing circuit is electrically connected with the second end of the impedance circuit, the second end of the temperature stabilizing circuit is electrically connected with the second end of the first current mirror circuit, and the third end of the temperature stabilizing circuit is electrically connected with the grounding end; the first current mirror circuit and the impedance circuit are configured to generate a first reference current according to the first voltage; the first reference current is related to the internal size of a transistor included in the first current mirror circuit; the temperature stabilization circuit is configured to cancel the positive and negative temperature coefficients such that the generated first reference current is approximately temperature independent.

Description

Technical Field

[0001] The utility model relates to the technical field of display screens, and in particular to a reference circuit, a driving chip and a display device. Background Art

[0002] Many driver chips are used in LED display technology. The overall area of ​​the reference circuit in the existing driver chip is large, and the power consumption is high, which is not conducive to further promotion. Utility Model Content

[0003] The embodiments of the present invention provide a reference circuit, a driver chip and a display device. The reference circuit has a small area and low power consumption.

[0004] In a first aspect, some embodiments of the present application provide a reference circuit, which includes: an impedance circuit, a first current mirror circuit and a temperature stabilization circuit; the first end of the first current mirror circuit is electrically connected to the first voltage end, and the second end of the first current mirror circuit is electrically connected to the first end of the impedance circuit; wherein the first voltage end is configured to output a first voltage; the first end of the temperature stabilization circuit is electrically connected to the second end of the impedance circuit, the second end of the temperature stabilization circuit is electrically connected to the second end of the first current mirror circuit, and the third end of the temperature stabilization circuit is electrically connected to the ground end; the first current mirror circuit and the impedance circuit are configured to generate a first reference current according to the first voltage; the first reference current is related to the internal size of the transistor included in the first current mirror circuit; the temperature stabilization circuit is configured to offset positive and negative temperature coefficients, so that the generated first reference current is approximately independent of temperature.

[0005] Based on the above scheme, some embodiments of the present application provide a reference circuit, which uses a temperature stabilization circuit to replace the first transistor and the second transistor. The temperature stabilization circuit has a smaller area, which can reduce the overall area of ​​the reference circuit and achieve the offset of positive and negative temperature coefficients. During the operation of the reference circuit, the impact of temperature increase will be further reduced, and by changing the width-to-length ratio of the transistor in the first current mirror circuit, the threshold voltage of the transistor can be changed, thereby changing the size of the first reference current.

[0006] In some embodiments, the temperature stabilization circuit includes: a first transistor and a second transistor; the control terminal of the first transistor is the first terminal of the temperature stabilization circuit, the first terminal of the first transistor is electrically connected to the second terminal of the first transistor, and the third terminal of the first transistor is the third terminal of the temperature stabilization circuit; the control terminal of the second transistor is the second terminal of the temperature stabilization circuit, the first terminal of the second transistor is electrically connected to the second terminal of the second transistor, and the third terminal of the second transistor is the third terminal of the temperature stabilization circuit;

[0007] The first transistor and the second transistor are configured to cancel positive and negative temperature coefficients so that the first reference current is approximately independent of temperature.

[0008] In some embodiments, the impedance circuit includes: a first resistor; a first end of the first resistor is the first end of the impedance circuit, and a second end of the first resistor is the second end of the impedance circuit.

[0009] In some embodiments, the control end of the impedance circuit is electrically connected to the control end of the first current mirror circuit, the third end of the impedance circuit is electrically connected to the ground end, and the fourth end of the impedance circuit is electrically connected to the first voltage end; the fifth end of the impedance circuit is electrically connected to the fourth end of the first current mirror circuit; the first current mirror circuit is configured to generate a second voltage based on the first voltage, and output the second voltage to the impedance circuit through the control end to change the impedance of the impedance circuit.

[0010] In some embodiments, the impedance circuit includes: a self-bias voltage module and an impedance module; the control end of the self-bias voltage module is the control end of the impedance circuit, the first end of the self-bias voltage module is electrically connected to the first voltage end, the second end of the self-bias voltage module is the fifth end of the impedance circuit, the third end of the self-bias voltage module is the third end of the impedance circuit, and the fourth end of the self-bias voltage module is electrically connected to the control end of the impedance module; the first end of the impedance module is the first end of the impedance circuit, and the second end of the impedance module is the second end of the impedance circuit; the self-bias voltage module is configured to receive the second voltage and output a third voltage to the impedance module to change the impedance of the impedance module.

[0011] In some embodiments, the self-bias voltage module includes: a third transistor, a fourth transistor and a fifth transistor; the control end of the third transistor is the second end of the self-bias voltage module, the first end of the third transistor is the first end of the self-bias voltage module, and the second end of the third transistor is electrically connected to the first end of the fourth transistor; the control end of the fourth transistor is the control end of the self-bias voltage module, and the second end of the fourth transistor is electrically connected to the first end of the fifth transistor; the control end of the fifth transistor is electrically connected to the first end of the fifth transistor, the control end of the fifth transistor is the fourth end of the self-bias voltage module, and the second end of the fifth transistor is the third end of the self-bias voltage module.

[0012] In some embodiments, the self-bias voltage module also includes: a sixth transistor; the control end of the sixth transistor is electrically connected to the second end of the fourth transistor, the first end of the sixth transistor is electrically connected to the second end of the sixth transistor, and the third end of the sixth transistor is the third end of the self-bias voltage module.

[0013] In some embodiments, the impedance module includes: a seventh transistor; the control end of the seventh transistor is the control end of the impedance module, the first end of the seventh transistor is the first end of the impedance module, and the second end of the seventh transistor is the second end of the impedance module.

[0014] In a second aspect, some embodiments of the present application provide a driver chip, which includes the above-mentioned reference circuit, a second current mirror circuit and a control circuit; the input end of the second current mirror circuit is electrically connected to the output end of the reference circuit, the control end of the second current mirror circuit is electrically connected to the output end of the control circuit, and the output end of the second current mirror circuit is electrically connected to the cathode of the light-emitting diode; the positive pole of the light-emitting diode is electrically connected to the power supply end; the second current mirror circuit is configured to convert the first reference current into a second reference current and transmit the second reference current to the light-emitting diode; wherein the first reference current and the second reference current are in proportional relationship; the control circuit is configured to control the number of bits of the second current mirror circuit to control the magnitude of the second reference current.

[0015] In a third aspect, some embodiments of the present application provide a display device comprising: a plurality of the above-mentioned driver chips and a light board; the light board is provided with a plurality of light-emitting diodes, and the plurality of driver chips are correspondingly connected to the plurality of light-emitting diodes.

[0016] The beneficial effects of the display device are the same as those of the above-mentioned reference circuit, and will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings are used to provide a further understanding of the technical solution of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the technical solution of the present invention and do not constitute a limitation on the technical solution of the present invention.

[0018] Figure 1 A circuit diagram of an existing reference circuit provided in an embodiment of the present application;

[0019] Figure 2 A schematic diagram of a reference circuit provided in an embodiment of the present application;

[0020] Figure 3 A schematic diagram of another reference circuit provided in an embodiment of the present application;

[0021] Figure 4 A schematic diagram of an impedance circuit provided in an embodiment of the present application;

[0022] Figure 5 Another impedance circuit schematic diagram provided in an embodiment of the present application;

[0023] Figure 6 A structural block diagram of an impedance circuit provided in an embodiment of the present application;

[0024] Figure 7 A schematic diagram of a self-bias voltage module provided in an embodiment of the present application;

[0025] Figure 8 A schematic diagram of an impedance module provided in an embodiment of the present application;

[0026] Figure 9 A schematic diagram of a driver chip provided in an embodiment of the present application;

[0027] Figure 10 A schematic diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0028] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0029] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative position relationship, movement status, etc. between the various components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0030] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include one or more of such features. In the description of this utility model, unless otherwise specified, "plurality" means two or more.

[0031] In the description of this utility model, it should be noted that, unless otherwise expressly specified or limited, the terms "connected" and "connect" should be understood broadly. For example, they can refer to fixed connections, removable connections, or integral connections. Those skilled in the art will understand the specific meanings of these terms in this utility model based on the specific circumstances. Furthermore, when describing pipelines, the terms "connected" and "connected" in this utility model have the meaning of conducting electricity. The specific meaning should be understood in the context.

[0032] In the embodiments of the present invention, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present invention should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0033] Many driver chips are used in LED display technology. The overall area of ​​the reference circuit in the existing driver chip is large, and the power consumption is high, which is not conducive to further promotion.

[0034] For example, refer to Figure 1 , Figure 1 The reference circuit in the embodiment includes a first transistor Q1 and a second transistor Q2. The base of the first transistor Q1 is electrically connected to the base of the second transistor Q2 and is grounded. The collector of the first transistor Q1 is connected to a resistor Rx, and the emitter of the first transistor Q1 is connected to the base. The collector of the second transistor Q2 is connected to a transistor, and the emitter of the second transistor Q2 is connected to the base. VDD generates a bias current through multiple transistors and resistor Rx, which is then replicated and output by the transistor. However, the resistors and transistors are large in size and area, making a small-scale circuit design impossible.

[0035] Based on this, some embodiments of the present application provide a reference circuit, such as Figure 2 As shown, the reference circuit 100 includes: a first current mirror circuit 1 , an impedance circuit 2 and a temperature stabilization circuit 3 .

[0036] The first current mirror circuit 1 includes a first terminal 101 , a second terminal 102 and a third terminal 103 .

[0037] The impedance circuit 2 includes a first terminal 201 and a second terminal 202 .

[0038] The temperature stabilization circuit 3 includes a first terminal 301 , a second terminal 302 and a third terminal 303 .

[0039] The first terminal 101 of the first current mirror circuit 1 is electrically connected to the first voltage terminal VDD, and the second terminal 102 of the first current mirror circuit 1 is electrically connected to the first terminal 201 of the impedance circuit 2. The first voltage terminal VDD is configured to output a first voltage U1.

[0040] The first terminal 301 of the temperature stabilization circuit 3 is electrically connected to the second terminal 202 of the impedance circuit 2 , the second terminal 302 of the temperature stabilization circuit 3 is electrically connected to the second terminal 102 of the first current mirror circuit 1 , and the third terminal 303 of the temperature stabilization circuit 3 is electrically connected to the ground terminal VSS.

[0041] The first current mirror circuit 1 and the impedance circuit 2 are configured to generate a first reference current according to the first voltage U1 ; the temperature stabilization circuit 3 is configured to offset positive and negative temperature coefficients so that the generated first reference current is approximately independent of temperature.

[0042] The first reference current is related to the internal dimensions of the transistors included in the first current mirror circuit. The first current mirror circuit generally includes multiple transistors. The first reference current is generated based on the first voltage U1. Therefore, if the resistance of the impedance circuit 2 is constant, changing the magnitude of the first reference current requires changing the voltage across the impedance circuit 2.

[0043] The voltage across the impedance circuit 2 is related to the first voltage U1, but the transistor in the first current mirror needs to exceed the threshold voltage in order to be turned on. In other words, the voltage across the impedance circuit 2 is the first voltage U1 minus the threshold voltage of the transistor in series with the impedance circuit 2.

[0044] In some embodiments, the transistor is a MOS transistor. The threshold voltage of a MOS transistor refers to the voltage required for the charge formed in the channel to offset the electric field applied by the gate when the gate voltage is zero. This is the critical voltage at which the MOS transistor transitions from the off state to the on state (or vice versa). When the gate voltage reaches or exceeds the threshold voltage, the number of carriers in the channel increases significantly, causing the MOS transistor to enter the on state. The magnitude of the threshold voltage depends on the process parameters and material properties of the MOS transistor.

[0045] The internal dimensions of the transistors mentioned above refer to the width-to-length ratio of the MOS transistors, which is the ratio of the transistor's channel width W to its channel length L. The channel width refers to the channel width of the MOS transistor, while the channel length refers to the channel length of the MOS transistor.

[0046] When the channel width W of the transistor is large, the additional charge Qchw can be ignored. However, when the channel width W is small, Qchw can no longer be ignored, causing the equivalent depletion layer charge density to increase and the threshold voltage of the MOS transistor to rise. In some special cases, as the channel width W decreases, the threshold voltage also decreases.

[0047] When the channel length L is small, the influence of the partial charge Qchl at the source and drain ends needs to be considered to reduce the equivalent depletion layer charge density and the threshold voltage of the MOS tube.

[0048] Qchw is the additional charge in the transistor in addition to the charge Qch under the gate, which has an important influence on the charge density and threshold voltage of the depletion layer; Qchl is the partial charge close to the source and drain in the transistor, which is no longer directly controlled by the gate, but is controlled by the source and drain.

[0049] That is, the threshold voltage of a transistor can be changed by changing its channel width W and / or channel length L. When the width-to-length ratio is small, the channel width is small, and the space for electrons to move in the channel is limited, resulting in a higher current density and a stronger conduction capability. When the width-to-length ratio is large, the channel width is large, and the space for electrons to move in the channel is relatively large, resulting in a lower current density and a weaker conduction capability.

[0050] Based on the above scheme, some embodiments of the present application provide a reference circuit, which uses a temperature stabilization circuit to replace the first transistor and the second transistor. The temperature stabilization circuit has a smaller area, which can reduce the overall area of ​​the reference circuit and achieve the offset of positive and negative temperature coefficients. During the operation of the reference circuit, the impact of temperature increase will be further reduced, and by changing the width-to-length ratio of the transistor in the first current mirror circuit, the threshold voltage of the transistor can be changed, thereby changing the size of the first reference current.

[0051] like Figure 3 As shown, the temperature stabilization circuit 3 includes: a first transistor M1 and a second transistor M2.

[0052] The control terminal of the first transistor M1 is the first terminal 301 of the temperature stabilization circuit 3 , the first terminal of the first transistor M1 is electrically connected to the second terminal of the first transistor M1 , and the third terminal of the first transistor M1 is the third terminal of the temperature stabilization circuit.

[0053] The control terminal of the second transistor M2 is the second terminal 302 of the temperature stabilization circuit 3 , the first terminal of the second transistor M2 is electrically connected to the second terminal of the second transistor M2 , and the third terminal of the second transistor M2 is the third terminal 303 of the temperature stabilization circuit 3 .

[0054] That is, the first terminal 101 of the first current mirror circuit 1 is electrically connected to the first voltage terminal VDD, and the second terminal 102 of the first current mirror circuit 1 is electrically connected to the first terminal 201 of the impedance circuit 2 .

[0055] The control terminal of the first transistor M1 is electrically connected to the second terminal 102 of the impedance circuit 2 , the first terminal of the first transistor M1 is electrically connected to the second terminal of the first transistor M1 , and the third terminal of the first transistor M1 is electrically connected to the ground terminal VSS.

[0056] The control terminal of the second transistor M2 is electrically connected to the third terminal 103 of the first current mirror circuit 1 , the first terminal of the second transistor M2 is electrically connected to the second terminal of the second transistor M2 , and the third terminal of the second transistor M2 is electrically connected to the ground terminal VSS.

[0057] The first voltage terminal VDD is configured to output a first voltage U1 ; the ground terminal VSS outputs a ground voltage Ud.

[0058] The first current mirror circuit 1 and the impedance circuit 2 are configured to generate a first reference current I1 according to a first voltage U1 .

[0059] When the first current mirror circuit 1 is conducting, there is an impedance X1. Adding the impedance X2 of the impedance circuit itself, the first reference current I1 = (U1-Ud) / (X1+X2). The first current mirror circuit 1 then replicates the first reference current I1 and outputs it through the output terminal OUT of the first current mirror circuit 1.

[0060] The first transistor M1 and the second transistor M2 achieve positive and negative temperature coefficient cancellation, so that the generated first reference current I1 is approximately independent of temperature.

[0061] The first transistor M1 is connected in a parasitic BJT manner, so that the first reference current I1 generated by the first voltage U1 is independent of temperature.

[0062] In some embodiments, the control end of the first transistor M1 is the gate, the first end of the first transistor M1 is the drain, the second end of the first transistor M1 is the source, and the third end of the first transistor M1 is the substrate; similarly, the control end of the second transistor M2 is the gate, the first end of the second transistor M2 is the drain, the second end of the second transistor M2 is the source, and the third end of the second transistor M2 is the substrate.

[0063] The first end of the first transistor M1 is electrically connected to the second end of the first transistor M1, and the third end of the first transistor M1 is electrically connected to the ground end VSS, which is equivalent to being connected in a parasitic BJT manner; similarly, the first end of the second transistor M2 is electrically connected to the second end of the second transistor M2, and the third end of the second transistor M2 is electrically connected to the ground end VSS, which is equivalent to being connected in a parasitic BJT manner; thereby achieving the offset of positive and negative temperature coefficients.

[0064] Parasitic BJTs (parasitic bipolar transistors) are a common parasitic structure in integrated circuits. They are inadvertently formed within the device during the integrated circuit manufacturing process due to the interaction between different doping layers. The BJT itself is a bipolar current-steering device consisting of an emitter (E), a base (B), and a collector (C). Parasitic BJTs, on the other hand, are naturally formed NPN or PNP BJT structures in the CMOS process due to the presence of structures such as a P-type substrate, N-type source and drain regions, and a P-type well.

[0065] Based on the above scheme, some embodiments of the present application provide a reference circuit, which can reduce the overall area of ​​the reference circuit by using a first transistor and a second transistor to replace the first triode and the second triode, and at the same time change the connection method of the first transistor and the second transistor, so as to achieve the cancellation of positive and negative temperature coefficients; the impact caused by temperature increase during the operation of the reference circuit will be further reduced.

[0066] In some embodiments, as Figure 4 As shown, the impedance circuit 2 includes: a first resistor R1.

[0067] The first end of the first resistor R1 is the first end 201 of the impedance circuit 2 , and the second end of the first resistor R1 is the second end 202 of the impedance circuit 2 .

[0068] That is, the impedance of the first resistor R1 is X2, and the first reference current I1 = (U1-Ud) / (X1+X2). The first current mirror circuit 1 then copies the first reference current I1 and outputs it through the output terminal OUT of the first current mirror circuit 1.

[0069] The entire area of ​​the reference circuit can be reduced by using the first transistor M1 and the second transistor M2. Meanwhile, the connection method of the first transistor M1 and the second transistor M2 can offset the positive and negative temperature coefficients, thereby reducing the impact of temperature rise.

[0070] In some embodiments, as Figure 5As shown, the control terminal 20X of the impedance circuit 2 is electrically connected to the control terminal EN of the first current mirror circuit 1, the third terminal 203 of the impedance circuit 2 is electrically connected to the ground terminal VSS, the fourth terminal 204 of the impedance circuit 2 is electrically connected to the first voltage terminal VDD; the fifth terminal 205 of the impedance circuit 2 is electrically connected to the fourth terminal 104 of the first current mirror circuit 1.

[0071] The first current mirror circuit 1 is configured to generate a second voltage U2 according to the first voltage U1 , and output the second voltage U2 to the control terminal 20X of the impedance circuit 2 via the control terminal EN to change the impedance of the impedance circuit 2 .

[0072] That is, the first voltage U1 is divided by the first current mirror circuit to generate the second voltage U2 , and the impedance of the impedance circuit is changed by the second voltage U2 , thereby changing the magnitude of the first reference current I1 .

[0073] For example, the impedance of the impedance circuit is increased by the second voltage U2, that is, the impedance X2 is increased; for the first reference current I1 = (U1-Ud) / (X1+X2), when U1 and Ud remain unchanged, increasing the impedance X2 will reduce the first reference current I1, thereby reducing the power consumption of the reference circuit. For specific circuits, please refer to Figure 6 .

[0074] like Figure 6 As shown, the impedance circuit 2 includes: an impedance module 21 and a self-bias voltage module 22 .

[0075] The control end 22X of the self-bias voltage module 22 is the control end 20X of the impedance circuit 2, the first end 221 of the self-bias voltage module 22 is electrically connected to the first voltage end VDD, the second end 222 of the self-bias voltage module 22 is the fifth end 205 of the impedance circuit 2, the third end 223 of the self-bias voltage module 22 is the third end 203 of the impedance circuit 2, and the fourth end 224 of the self-bias voltage module 22 is electrically connected to the control end 21X of the impedance module 21.

[0076] The first end 211 of the impedance module 21 is the first end 201 of the impedance circuit 2 , and the second end 212 of the impedance module 21 is the second end 202 of the impedance circuit 2 .

[0077] The self-bias voltage module 22 is configured to receive the second voltage U2 and output a third voltage U3 to the impedance module 21 to change the impedance of the impedance module 21 .

[0078] That is, the first voltage U1 is divided by the first current mirror circuit 1 to generate the second voltage U2, and the second voltage U2 is transmitted to the control end 22X of the self-bias voltage module 22 through the control end EN of the first current mirror circuit 1. The self-bias voltage module 22 receives the second voltage U2 and outputs a third voltage U3, and transmits the third voltage U3 to the control end 21X of the impedance module 21 through the fourth end 224 of the self-bias voltage module 22; the impedance module 21 receives the voltage and thus changes the size of the impedance.

[0079] For example, the first voltage U1 is first converted into the second voltage U2, and then the second voltage U2 is converted into the third voltage U3. The impedance of the impedance module is increased by the third voltage U3, that is, the impedance X2 is increased. For the first reference current I1 = (U1-Ud) / (X1+X2), when U1 and Ud remain unchanged, increasing the impedance X2 will reduce the first reference current I1, thereby reducing the power consumption of the reference circuit.

[0080] like Figure 7 As shown, the self-bias voltage module 22 includes: a third transistor M3, a fourth transistor M4 and a fifth transistor M5.

[0081] The control end of the third transistor M3 is the second end 222 of the self-bias voltage module 22 , the first end of the third transistor M3 is the first end 221 of the self-bias voltage module 22 , and the second end of the third transistor M3 is electrically connected to the first end of the fourth transistor M4 .

[0082] The control end of the fourth transistor M4 is the control end of the self-bias voltage module 22, and the second end of the fourth transistor M4 is electrically connected to the first end of the fifth transistor M5; the control end of the fifth transistor M5 is electrically connected to the first end of the fifth transistor M5, and the control end of the fifth transistor M5 is the fourth end of the self-bias voltage module 22, and the second end of the fifth transistor M5 is the third end of the self-bias voltage module 22.

[0083] That is, the first voltage U1 is divided by the first current mirror circuit 1 to generate the second voltage U2, and the second voltage U2 is transmitted to the control terminal 22X of the self-bias voltage module 22 through the control terminal EN of the first current mirror circuit 1. The self-bias voltage module 22 receives the second voltage U2, and the control terminal voltage of the fourth transistor M4 is the second voltage U2, so that the fourth transistor M4 operates in the saturation region.

[0084] At the same time, the control terminal of the third transistor M3 receives the voltage provided by the first current mirror circuit 1 through the fourth terminal, so that the third transistor M3 also operates in the saturation region.

[0085] The third transistor M3, the fourth transistor M4 and the fifth transistor M5 operate in a suitable saturation region to generate a third voltage U3, and the third voltage U3 is output. The third voltage U3 is transmitted to the control terminal 21X of the impedance module 21 through the fourth terminal 224 of the self-bias voltage module 22; the impedance module 21 receives the voltage and thus changes the size of the impedance.

[0086] In some embodiments, reference Figure 7 , the self-bias voltage module 22 further includes: a sixth transistor M6.

[0087] The control end of the sixth transistor M6 is electrically connected to the second end of the fourth transistor M4 , the first end of the sixth transistor M6 is electrically connected to the second end of the sixth transistor M6 , and the third end of the sixth transistor M6 is the third end of the self-bias voltage module 22 .

[0088] The function of the connection mode of the sixth transistor M6 is the same as that of the first transistor M1 and the second transistor M2 , which can achieve the offset of positive and negative temperature coefficients, so that the current generated by the self-bias voltage module 22 is approximately independent of temperature.

[0089] like Figure 8 As shown, the impedance module 21 includes: a seventh transistor M7.

[0090] The control end of the seventh transistor M7 is the control end 21X of the impedance module 21 , the first end of the seventh transistor M7 is the first end 211 of the impedance module 21 , and the second end of the seventh transistor M7 is the second end 212 of the impedance module 21 .

[0091] The on-resistance of the seventh transistor M7 is determined by its size.

[0092] That is, the first current mirror circuit 1 divides the first voltage U1 to generate a second voltage U2, and transmits the second voltage U2 to the control terminal 22X of the self-bias voltage module 22 via the control terminal EN of the first current mirror circuit 1. The self-bias voltage module 22 receives the second voltage U2, and the control terminal voltage of the fourth transistor M4 is the second voltage U2, causing the fourth transistor M4 to operate in a saturation region. Simultaneously, the control terminal of the third transistor M3 receives the voltage provided by the first current mirror circuit 1 via the fourth terminal, causing the third transistor M3 to also operate in a saturation region.

[0093] The third transistor M3, the fourth transistor M4, and the fifth transistor M5 operate in a suitable saturation region to generate a third voltage U3, output the third voltage U3, and transmit the third voltage U3 to the control terminal 21X of the impedance module 21 through the fourth terminal 224 of the self-bias voltage module 22; the seventh transistor M7 operates in a linear region, which is equivalent to a large resistor. In this way, by changing the first voltage U1 and the characteristics of the third transistor M3, the fourth transistor M4, and the fifth transistor M5, the impedance of the seventh transistor M7 can be changed, thereby changing the size of the impedance X2.

[0094] For example, the first voltage U1 is first converted into the second voltage U2, and then the second voltage U2 is converted into the third voltage U3. The impedance of the impedance module is increased by the third voltage U3, that is, the impedance X2 is increased. For the first reference current I1 = (U1-Ud) / (X1+X2), when U1 and Ud remain unchanged, increasing the impedance X2 will reduce the first reference current I1, thereby reducing the power consumption of the reference circuit.

[0095] The overall circuit architecture area should be less than 20um*30um, and the overall circuit power consumption should be less than 10uA, which can be achieved through the above-mentioned benchmark circuit.

[0096] In some embodiments, reference Figure 8 The first current mirror circuit 1 includes an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16 and a seventeenth transistor M17.

[0097] The control end of the eighth transistor M8 is electrically connected to the control end of the ninth transistor M9, and is also electrically connected to the fourth end 104 of the first current mirror circuit 1, the second end of the tenth transistor M10, the control end of the twelfth transistor M12, and the first end of the fourteenth transistor M14. The first end of the eighth transistor M8 is electrically connected to the first voltage end VDD, and the second end of the eighth transistor M8 is electrically connected to the first end of the tenth transistor M10.

[0098] A first end of the ninth transistor M9 is electrically connected to the first voltage end VDD, and a second end of the ninth transistor M9 is electrically connected to a first end of the eleventh transistor M11 .

[0099] The control end of the tenth transistor M10 is electrically connected to the control end of the eleventh transistor M11 , and is also electrically connected to the control end EN of the first current mirror circuit 1 and the control end of the thirteenth transistor M13 .

[0100] The second end of the eleventh transistor M11 is electrically connected to the first end of the fifteenth transistor M15 , and is also electrically connected to the control end of the fifteenth transistor M15 and the control end of the fourteenth transistor M14 .

[0101] A first end of the twelfth transistor M12 is electrically connected to the first voltage end VDD, and a second end of the twelfth transistor M12 is electrically connected to a first end of the thirteenth transistor M13; a second end of the thirteenth transistor M13 is an output end OUT of the first current mirror circuit.

[0102] The second end of the fourteenth transistor M14 is the second end 102 of the first current mirror circuit 1 , and the second end of the fifteenth transistor M15 is the third end 103 of the first current mirror circuit 1 .

[0103] The control terminal of the sixteenth transistor M16 is electrically connected to the first voltage terminal VDD and also electrically connected to the first terminal of the sixteenth transistor M16 ; the second terminal of the sixteenth transistor M16 is electrically connected to the first terminal of the seventeenth transistor M17 .

[0104] A first end of the seventeenth transistor M17 is electrically connected to the control end of the fourth transistor M4 ; a second end of the seventeenth transistor M17 is electrically connected to the ground end VSS.

[0105] By providing a turn-on voltage to the control terminals of the sixteenth transistor M16 and the seventeenth transistor M17, the two transistors divide the first voltage U1 to generate the second voltage U2.

[0106] The second voltage U2 is transmitted to the control terminal 22X of the self-bias voltage module 22 via the control terminal EN of the first current mirror circuit 1. The self-bias voltage module 22 receives the second voltage U2, and the control terminal voltage of the fourth transistor M4 is the second voltage U2, causing the fourth transistor M4 to operate in the saturation region. Simultaneously, the control terminal of the third transistor M3 receives the voltage provided by the first current mirror circuit 1 via the fourth terminal, causing the third transistor M3 to also operate in the saturation region.

[0107] The third transistor M3, the fourth transistor M4, and the fifth transistor M5 operate in a suitable saturation region to generate a third voltage U3, output the third voltage U3, and transmit the third voltage U3 to the control terminal 21X of the impedance module 21 through the fourth terminal 224 of the self-bias voltage module 22; the seventh transistor M7 operates in a linear region, which is equivalent to a large resistor. In this way, by changing the first voltage U1 and the characteristics of the third transistor M3, the fourth transistor M4, and the fifth transistor M5, the impedance of the seventh transistor M7 can be changed, thereby changing the size of the impedance X2.

[0108] For example, the first voltage U1 is first converted to the second voltage U2, and then the second voltage U2 is converted to the third voltage U3. The third voltage U3 is used to increase the impedance of the impedance module, that is, to increase the impedance X2. For the first reference current I1 = (U1-Ud) / (X1+X2), the first impedance X1 refers to the impedance when the eighth transistor, the tenth transistor, and the fourteenth transistor are turned on. When U1 and Ud remain unchanged, increasing the impedance X2 will reduce the first reference current I1, thereby reducing the power consumption of the reference circuit.

[0109] It should be noted that the fourteenth transistor M14 and the fifteenth transistor M15 are NMOS transistor bias circuits, which can largely isolate the circuit from the influence of power supply changes.

[0110] In some embodiments, the eighth transistor M8 and the ninth transistor M9 have the same size, and the tenth transistor M10 and the eleventh transistor M11 have the same size.

[0111] Among them, the threshold voltages of the eighth transistor M8, the tenth transistor M10, and the fourteenth transistor M14 can be changed by changing the width-to-length ratio of the eighth transistor M8, the tenth transistor M10, and the fourteenth transistor M14. When the impedance of the seventh transistor M7 is a constant, the magnitude of the first reference current can be changed.

[0112] like Figure 9 As shown, some embodiments of the present application provide a driver chip, and the driver chip 200 includes the above-mentioned reference circuit 100, a second current mirror circuit 110 and a control circuit 120.

[0113] The input terminal 111 of the second current mirror circuit 110 is electrically connected to the output terminal OUT of the reference circuit 100, the control terminal 11X of the second current mirror circuit 110 is electrically connected to the output terminal 121 of the control circuit 120, and the output terminal of the second current mirror circuit 110 is electrically connected to the cathode of the light-emitting diode; the positive electrode of the light-emitting diode LED is electrically connected to the power supply terminal VCC.

[0114] The second current mirror circuit 110 is configured to convert the first reference current I1 into a second reference current I2 and transmit the second reference current I2 to the light emitting diode LED.

[0115] The first reference current I1 and the second reference current I2 are in proportional relationship.

[0116] The control circuit 120 is configured to control the number of bits of the second current mirror circuit 110 to control the magnitude of the second reference current I2 .

[0117] That is to say, the first reference current I1 can be copied in multiples through the control circuit, and the second reference current I2 can be the same as the first reference current I1 or a multiple of the first reference current I1.

[0118] like Figure 10 As shown, some embodiments of the present application provide a display device, and the display device 300 includes: a plurality of the above-mentioned driving chips 200 and a light board 210.

[0119] The light board 210 is provided with a plurality of light emitting diodes LED, and a plurality of driving chips 200 are correspondingly connected to the plurality of light emitting diodes LED.

[0120] The beneficial effects of the display device are the same as those of the above-mentioned reference circuit, and will not be described in detail here.

[0121] The above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited to this. Any changes or replacements within the technical scope disclosed in this utility model should be included in the scope of protection of the present utility model. Therefore, the scope of protection of the present utility model should be based on the scope of protection of the claims.

Claims

1. A reference circuit, characterized in that: include: Impedance circuit; a first current mirror circuit, wherein a first terminal of the first current mirror circuit is electrically connected to a first voltage terminal, and a second terminal of the first current mirror circuit is electrically connected to a first terminal of the impedance circuit; wherein the first voltage terminal is configured to output a first voltage; a temperature stabilization circuit, wherein a first end of the temperature stabilization circuit is electrically connected to the second end of the impedance circuit, a second end of the temperature stabilization circuit is electrically connected to the second end of the first current mirror circuit, and a third end of the temperature stabilization circuit is electrically connected to a ground end; The first current mirror circuit and the impedance circuit are configured to generate a first reference current according to the first voltage; the first reference current is related to an internal size of a transistor included in the first current mirror circuit; The temperature stabilization circuit is configured to cancel positive and negative temperature coefficients so that the generated first reference current is approximately independent of temperature.

2. The reference circuit according to claim 1, wherein: The temperature stabilization circuit comprises: a first transistor, wherein a control terminal of the first transistor is the first terminal of the temperature stabilization circuit, the first terminal of the first transistor is electrically connected to the second terminal of the first transistor, and the third terminal of the first transistor is the third terminal of the temperature stabilization circuit; a second transistor, wherein a control terminal of the second transistor is the second terminal of the temperature stabilization circuit, a first terminal of the second transistor is electrically connected to the second terminal of the second transistor, and a third terminal of the second transistor is the third terminal of the temperature stabilization circuit; The first transistor and the second transistor are configured to cancel positive and negative temperature coefficients so that the first reference current is approximately independent of temperature.

3. The reference circuit according to claim 1, wherein: The impedance circuit includes: a first resistor; The first end of the first resistor is the first end of the impedance circuit, and the second end of the first resistor is the second end of the impedance circuit.

4. The reference circuit according to claim 1, wherein: The control end of the impedance circuit is electrically connected to the control end of the first current mirror circuit, the third end of the impedance circuit is electrically connected to the ground end, the fourth end of the impedance circuit is electrically connected to the first voltage end; the fifth end of the impedance circuit is electrically connected to the fourth end of the first current mirror circuit; The first current mirror circuit is configured to generate a second voltage according to the first voltage, and output the second voltage to the impedance circuit via the control terminal to change the impedance of the impedance circuit.

5. The reference circuit according to claim 4, wherein: The impedance circuit includes: a self-bias voltage module and an impedance module; The control end of the self-bias voltage module is the control end of the impedance circuit, the first end of the self-bias voltage module is electrically connected to the first voltage end, the second end of the self-bias voltage module is the fifth end of the impedance circuit, the third end of the self-bias voltage module is the third end of the impedance circuit, and the fourth end of the self-bias voltage module is electrically connected to the control end of the impedance module; The first end of the impedance module is the first end of the impedance circuit, and the second end of the impedance module is the second end of the impedance circuit; The self-bias voltage module is configured to receive the second voltage and output a third voltage to the impedance module to change the impedance of the impedance module.

6. The reference circuit according to claim 5, wherein: The self-bias voltage module includes: a third transistor, a fourth transistor and a fifth transistor; The control end of the third transistor is the second end of the self-bias voltage module, the first end of the third transistor is the first end of the self-bias voltage module, and the second end of the third transistor is electrically connected to the first end of the fourth transistor; The control end of the fourth transistor is the control end of the self-bias voltage module, and the second end of the fourth transistor is electrically connected to the first end of the fifth transistor; The control end of the fifth transistor is electrically connected to the first end of the fifth transistor, the control end of the fifth transistor is the fourth end of the self-bias voltage module, and the second end of the fifth transistor is the third end of the self-bias voltage module.

7. The reference circuit according to claim 6, wherein: The self-bias voltage module further includes: a sixth transistor; The control end of the sixth transistor is electrically connected to the second end of the fourth transistor, the first end of the sixth transistor is electrically connected to the second end of the sixth transistor, and the third end of the sixth transistor is the third end of the self-bias voltage module.

8. The reference circuit according to claim 5, wherein: The impedance module includes: a seventh transistor; The control end of the seventh transistor is the control end of the impedance module, the first end of the seventh transistor is the first end of the impedance module, and the second end of the seventh transistor is the second end of the impedance module.

9. A driver chip, characterized in that: include: The reference circuit, the second current mirror circuit, and the control circuit according to any one of claims 1 to 8; The input end of the second current mirror circuit is electrically connected to the output end of the reference circuit, the control end of the second current mirror circuit is electrically connected to the output end of the control circuit, and the output end of the second current mirror circuit is electrically connected to the cathode of the light emitting diode; The positive electrode of the light emitting diode is electrically connected to the power supply terminal; The second current mirror circuit is configured to convert the first reference current into a second reference current and transmit the second reference current to the light emitting diode; Wherein, the first reference current and the second reference current are in proportional relationship; The control circuit is configured to control the number of bits of the second current mirror circuit to control the magnitude of the second reference current.

10. A display device, characterized in that: The display device includes: A plurality of driver chips as claimed in claim 9; The light board is provided with a plurality of light emitting diodes, and the plurality of driving chips are correspondingly connected to the plurality of light emitting diodes.

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