Multi-source power supply control circuit of electric energy meter

Abstract

The utility model discloses a multi-source power supply control circuit for an electric energy meter. The multi-source power supply control circuit comprises a control unit main power supply bus; the diode OR structure is arranged on a main power supply bus of the control unit; the double-layer energy storage structure is arranged on a main power supply bus of the control unit; the double-P-MOS control structure is connected in series with a main power supply bus of the control unit; the priority judgment network is connected with the grid electrode of the second P channel and comprises a plurality of diodes and resistors; the boost conversion circuit is connected to the battery domain, and the output end of the boost conversion circuit forms a power bus; and the battery interface circuit is arranged between the power supply bus and an external battery and comprises a diode and a current-limiting resistor which are in one-way conduction. The multi-source power supply control circuit of the electric energy meter has the characteristics that the structure is simple, a special control chip is not needed, and multi-power priority automatic management and long-time power-off protection can be realized.

Description

Technical Field

[0001] The utility model relates to a multi-source power supply control circuit for an electric energy meter. Background Art

[0002] Power reliability is crucial for the proper functioning of modern electronic devices, especially energy meters. Grid fluctuations, temporary power outages, or battery depletion can cause system reboots, data loss, or metering errors. Ensuring a continuous and stable power supply is crucial for the proper functioning of these devices.

[0003] There are mainly the following traditional power protection solutions: First, an uninterruptible power supply (UPS) is used to provide backup power for the entire system. Although it is highly reliable, it is bulky and costly, making it unsuitable for small devices with limited space. Second, a simple diode "OR" gate circuit is used to combine multiple power supplies. Although it has a simple structure, it cannot achieve priority control and is prone to circulating current and mutual interference. Third, a dedicated power management chip is used to implement power monitoring and switching. This type of solution has complete functions but is expensive, and its high integration leads to limited flexibility. Fourth, a simple capacitor backup solution has a simple structure but a short maintenance time, usually only maintaining power supply for a few hundred milliseconds.

[0004] Traditional designs for power outage protection often rely on a single type of energy storage element, such as electrolytic capacitors or supercapacitors. Electrolytic capacitors offer fast response times but low energy storage density, while supercapacitors offer high energy storage density but require specialized charge management circuitry. These advantages make it difficult to combine fast response times and long-term performance in a single design. Furthermore, existing multi-power supply systems often lack effective priority management mechanisms, making it impossible to automatically adjust power supply strategies based on the status of each power source. This can lead to interference between power sources, circulating currents, and energy waste.

[0005] Therefore, there is an urgent need for a multi-source power supply control circuit for an electricity meter with a simple structure, low cost, high reliability and easy maintenance, which can not only realize seamless switching and priority management of multiple power sources, but also provide a sufficiently long power-off protection time without introducing complex dedicated chips or control logic. Utility Model Content

[0006] The utility model aims to provide a multi-source power supply control circuit for an electric energy meter, which has the characteristics of simple structure, no need for a dedicated control chip, and can realize automatic management of multiple power supply priorities and long-term power failure protection.

[0007] The above technical objectives of the present invention are achieved through the following technical solutions:

[0008] A multi-source power supply control circuit for an electric energy meter comprises: a control unit main power supply bus (VCU); a diode OR structure provided on the control unit main power supply bus (VCU), comprising a plurality of diodes (D35, D33, D36) connected in parallel; a double-layer energy storage structure provided on the control unit main power supply bus (VCU), comprising a directly connected electrolytic capacitor (C36) and a supercapacitor (C60) connected via a current-limiting resistor (R90); a dual P-MOS control structure connected in series with the control unit main power supply bus (VCU), comprising a first P channel (Q17) and a second P A P-channel (Q18), the source of the first P-channel (Q17) is connected to the main power supply bus (VCU) of the control unit; a priority judgment network connected to the gate of the second P-channel (Q18), including multiple diodes (D30, D31, D32) and resistors (R75, R76); a boost converter circuit (U4) connected to the battery domain (B3V6), the output end of which forms a power bus (B6V); a battery interface circuit arranged between the power bus (B6V) and an external battery (BAT2), including a unidirectional conducting diode (D37) and a current limiting resistor (R111).

[0009] The utility model is further configured such that: the gate of the first P channel (Q17) is connected to a soft start network, including a resistor (R82) and a capacitor (C38), for controlling the inrush current during power-on.

[0010] The utility model is further configured as follows: the priority judgment network includes: a first diode (D30), connected to the battery domain (B3V6); a second diode (D32), connected to the power bus (B6V); and a clamping diode (D31), connected to the ground.

[0011] The utility model is further configured such that: the supercapacitor (C60) is connected via a test interface (TEST3), so that the supercapacitor (C60) can be disassembled and replaced.

[0012] The utility model is further configured as follows: the external battery (BAT2) is connected via a test interface (TEST2), and the current limiting resistor (R111) and the diode (D37) are arranged in parallel.

[0013] The utility model is further configured to include an undervoltage detection circuit, which includes a voltage-dividing resistor network (R77, R78, R79), a filter capacitor (C37) and a two-stage transistor comparator (Q15, Q16), and is used to output an undervoltage detection signal (LVDIN0).

[0014] The utility model is further configured as follows: the capacitance of the electrolytic capacitor (C36) is 1000 μF, the capacitance of the supercapacitor (C60) is 0.22 F, and the capacitance ratio between the two is 1:220.

[0015] The utility model is further configured such that the input end and the output end of the boost conversion circuit (U4) are respectively connected to decoupling capacitors (C39, C40) to minimize the current loop area.

[0016] The present invention is further configured as follows: multiple independent reference grounds (GND, GND2, G485, B6V-) are provided to form a star connection topology.

[0017] In summary, the present invention has the following beneficial effects:

[0018] 1. Multi-source seamless switching structure: Through a diode OR structure and dual P-MOS control structure, automatic switching is achieved between three power sources: the control unit's main power bus (VCU), the boosted power bus (B6V) from the battery domain (B3V6), and the external battery (BAT2). If any power source fails, the other power sources automatically take over without the need for complex control circuits, significantly improving system power supply reliability. The diode OR structure uses a physical arrangement of multiple parallel diodes to ensure that the power input channels do not interfere with each other or reverse power, enhancing the system's electrical isolation performance.

[0019] 2. Dual-Level Power-Off Protection: A dual-layer energy storage structure consisting of a directly connected electrolytic capacitor (C36) and a supercapacitor (C60) connected via a current-limiting resistor (R90) achieves power-off protection on both millisecond and second timescales. The cylindrical electrolytic capacitor is directly mounted on the control unit's main power bus, providing immediate response; the supercapacitor is connected to the main power bus via a current-limiting resistor, providing long-term holdover. The design with a capacitance ratio of 1:220 extends the power-off holdover time from the traditional hundreds of milliseconds to tens of seconds, significantly improving the system's stability during grid fluctuations.

[0020] 3. Automatic Priority Management: The priority determination network connected to the gate of the second P-channel (Q18) automatically detects the voltage status of the battery domain (B3V6) and the power bus (B6V) through physical connection, and controls the conduction state of the second P-channel accordingly, achieving automatic management of power supply priority. When a low-priority power supply (VCU) and a high-priority power supply (B3V6 or B6V) are simultaneously active, the system automatically uses the high-priority power supply, avoiding mutual interference and circulating current between the power supplies and extending the supercapacitor's backup time.

[0021] 4. Soft start and surge suppression: The gate of the first P-channel (Q17) is connected to a soft start network consisting of a resistor (R82) and a capacitor (C38). This structure controls the conduction speed, significantly reducing the peak surge current during power-up, and protecting the subsequent circuits and power supply system. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 This is a circuit diagram of the utility model.

[0023] Reference numerals:

[0024] 1-Control unit main power supply bus (VCU); 2-Diode (D35); 3-Diode (D33); 4-Diode (D36); 5-Electrolytic capacitor (C36); 6-Current limiting resistor (R90); 7-Supercapacitor (C60); 8-First P-channel (Q17); 9-Second P-channel (Q18); 10-First diode (D30); 11-Second diode (D32); 12-Clamping diode (D31); 13-Resistor (R75); 14-Resistor (R76); 15-Boost converter circuit (U4); 16-Battery domain (B3V6); 17 -Power bus (B6V); 18-Diode (D37); 19-Current limiting resistor (R111); 20-External battery (BAT2); 21-Test interface (TEST3); 22-Test interface (TEST2); 23-Resistor (R82); 24-Capacitor (C38); 25-Decoupling capacitor (C39); 26-Decoupling capacitor (C40); 27-Voltage divider resistor (R77); 28-Voltage divider resistor (R78); 29-Voltage divider resistor (R79); 30-Filter capacitor (C37); 31-Transistor (Q15); 32-Transistor (Q16). DETAILED DESCRIPTION

[0025] The present invention will be described in further detail below with reference to the accompanying drawings.

[0026] like Figure 1 As shown, the utility model provides a multi-source power supply control circuit for an electric energy meter. The circuit as a whole adopts a regionalized partitioning design layout and is mainly divided into three independent functional areas: a control unit main power supply domain, a boost circuit domain, and an external battery interface domain.

[0027] The control unit main power bus (VCU) 1 is located in the center left of the circuit board and runs horizontally. A diode OR structure is provided on the control unit main power bus (VCU) 1, consisting of three parallel-connected diodes: diode (D35) 2, diode (D33) 3, and diode (D36) 4. These three diodes are small surface-mount packages, with their cathodes connected to the control unit main power bus (VCU) 1, forming a power convergence point. The anode of diode (D35) 2 is connected to the +4V input, the anode of diode (D33) 3 is connected to the VCM input, and the anode of diode (D36) 4 is connected to the standby input. The spacing between the three diodes is approximately 5 mm, ensuring proper heat dissipation and preventing interference.

[0028] A double-layer energy storage structure is also provided on the control unit main power supply bus (VCU) 1, including a directly connected electrolytic capacitor (C36) 5 and a supercapacitor (C60) 7 connected via a current-limiting resistor (R90) 6. The electrolytic capacitor (C36) 5 is cylindrical and vertically mounted, with a capacitance of 1000μF and is connected to the ground. The supercapacitor (C60) 7 has a capacitance of 0.22F and is connected to the test interface (TEST3) 21 (TEST3) via two wires approximately 30mm long. The current-limiting resistor (R90) 6 has a resistance of 5.1Ω, one end of which is welded to the control unit main power supply bus (VCU) 1, and the other end is connected to the test interface (TEST3) 21 via a wiring.

[0029] The control unit's main power bus (VCU) 1 is connected to the right-hand circuitry via a dual P-MOS control structure. This dual P-MOS control structure consists of a first P-channel (Q17) 8 and a second P-channel (Q18) 9, arranged in series. Both the first P-channel (Q17) 8 and the second P-channel (Q18) 9 utilize SOT-23 packages, with three pins arranged in a triangle. The source of the first P-channel (Q17) 8 is connected to the control unit's main power bus (VCU) 1 via a short, approximately 5 mm trace. The drain of the first P-channel (Q17) 8 is connected to the source of the second P-channel (Q18) 9. The drain of the second P-channel (Q18) 9 is connected to the right-hand power rail.

[0030] The gate of the first P-channel transistor (Q17) 8 is connected to a soft-start network consisting of a resistor (R82) 23 and a capacitor (C38) 24. Resistor (R82) 23 is a 1kΩ chip resistor, and capacitor (C38) 24 is a 0.01μF ceramic chip capacitor. One end of resistor (R82) 23 is connected to the gate of the first P-channel transistor (Q17) 8, and the other end is connected to one end of capacitor (C38) 24. The other end of capacitor (C38) 24 is grounded. This soft-start network is placed in close proximity to the first P-channel transistor (Q17) 8, no more than 5mm away, to minimize inductance and capacitance.

[0031] The gate of second P-channel transistor (Q18) 9 is connected to a priority determination network comprising a first diode (D30) 10, a second diode (D32) 11, a clamping diode (D31) 12, a resistor (R75) 13, and a resistor (R76) 14. First diode (D30) 10, second diode (D32) 11, and clamping diode (D31) 12 are all 1N4148 models and are packaged in an SOD-123. The anode of the first diode (D30) 10 is connected to the battery bus (B3V6) 16, and its cathode is connected to the gate of the second P-channel (Q18) 9 via resistor (R75) 13. The anode of the second diode (D32) 11 is connected to the power bus (B6V) 17, and its cathode is also connected to the gate of the second P-channel (Q18) 9 via resistor (R75) 13. The cathode of the clamping diode (D31) 12 is connected to the junction of resistor (R75) 13 and the gate of the second P-channel (Q18) 9, and its anode is grounded. The three diodes are arranged in a triangular configuration on the circuit board, with the center point connected to the gate of the second P-channel (Q18) 9 via resistor (R75) 13. Resistor (R75) 13 is a 1kΩ chip resistor. Resistor (R76) 14 is also a 5.1MΩ chip resistor, with one end connected to the gate of the second P-channel (Q18) 9 and the other end grounded, providing a high-impedance bias.

[0032] The circuit also includes a boost converter circuit (U4) 15 connected to the battery domain (B3V6) 16. The boost converter circuit (U4) 15 is an S-1206B36-U3T1G chip packaged in a SOT-23-5 package. Five pins are arranged along the bottom of the package. The input of the boost converter circuit (U4) 15 is connected to the battery domain (B3V6) 16 via a short trace, and the output forms a power bus (B6V) 17. Decoupling capacitors (C39) 25 and (C40) 26 are connected to the input and output of the boost converter circuit (U4) 15, respectively. The decoupling capacitor (C39) 25 has a capacitance of 1 μF, and the decoupling capacitor (C40) 26 has a capacitance of 0.1 μF. Both are chip ceramic capacitors and are placed close to the input and output pins of the boost converter circuit (U4) 15 to minimize the current loop area.

[0033] A battery interface circuit is provided between the power bus (B6V) 17 and the external battery (BAT2) 20, including a unidirectionally conducting diode (D37) 18 and a current-limiting resistor (R111) 19. Diode (D37) 18 is an SS12 Schottky diode in an SMA package, with its cathode connected to the power bus (B6V) 17 and its anode connected via a trace to the test interface (TEST2) 22. Current-limiting resistor (R111) 19 is a chip resistor with a resistance of 5.1Ω and a power rating of 1 / 4W. It is provided in parallel with diode (D37) 18, with one end connected to the power bus (B6V) 17 and the other end connected to the test interface (TEST2) 22. Test interface (TEST2) 22 is used to connect to the external battery (BAT2) 20.

[0034] The circuit also includes an undervoltage detection circuit, located in the lower left corner of the circuit board. This circuit comprises a voltage divider resistor (R77) 27, a voltage divider resistor (R78) 28, a voltage divider resistor (R79) 29, a filter capacitor (C37) 30, and a two-stage transistor comparator, comprised of a transistor (Q15) 31 and a transistor (Q16) 32. The voltage divider resistor (R77) 27 has a resistance of 47kΩ, the voltage divider resistor (R78) 28 has a resistance of 3.6kΩ, and the voltage divider resistor (R79) 29 has a resistance of 10kΩ. These three resistors are arranged in a triangle with a spacing of approximately 5mm, forming a voltage divider network. The filter capacitor (C37) 30 has a capacitance of 0.01μF and is connected in parallel with the voltage divider network. Transistors (Q15) 31 and (Q16) 32 are both 2N2222 models and housed in a TO-92 package. They are arranged in series to form a two-stage amplifier and comparator circuit, outputting an undervoltage detection signal, LVDIN0.

[0035] The entire circuit board is rectangular and divided into three main areas: the control unit's main power supply domain, the boost circuit domain, and the external battery interface domain. The circuit board adopts a star-connected topology with multiple independent reference grounds (GND, GND2, G485, and B6V-). These areas are physically partitioned and interconnected at specific points to reduce ground loop interference. Diodes (D35) 2, (D33) 3, and (D36) 4 are radially arranged near the control unit's main power bus (VCU) 1. Electrolytic capacitors (C36) 5 are installed directly next to the control unit's main power bus (VCU) 1. Supercapacitors (C60) 7 are connected via test interface (TEST3) 21 and are located at the edge of the circuit board. A first P-channel (Q17) 8 and a second P-channel (Q17) 9 are arranged in series between the control unit's main power bus (VCU) 1 and the right power rail, forming a power control channel. The boost converter circuit (U4) 15 and its input and output capacitors form a compact layout and are located on the right half of the circuit board. The diode (D37) 18 and the current limiting resistor (R111) 19 are arranged near the test interface (TEST2) 22 and are located at the right edge of the circuit board.

[0036] The working process of this utility model is as follows:

[0037] When the external power supply is normal, power is supplied to the control unit main power bus (VCU) 1 via a diode OR structure. The control unit main power bus (VCU) 1 directly supplies power to the left circuit and, through a dual P-MOS control structure, to the right circuit. Simultaneously, the electrolytic capacitor (C36) 5 is directly charged, and the supercapacitor (C60) 7 is slowly charged through the current-limiting resistor (R90) 6. When the battery domain (B3V6) 16 is charged, the boost converter circuit (U4) 15 raises its voltage to approximately 6V, forming the power bus (B6V) 17. The power bus (B6V) 17 supplies power to the right circuit and, through the diode (D37) 18 and current-limiting resistor (R111) 19, charges the external battery (BAT2) 20.

[0038] When the external power supply, battery domain (B3V6) 16, and power bus (B6V) 17 are all valid, the priority judgment network causes the second P-channel (Q18) 9 to be cut off or conduction-limited, preventing the control unit's main power bus (VCU) 1 from supplying power to the right-hand circuit. This prevents mutual interference and circulating current between power sources and extends the backup time of supercapacitor (C60) 7. When the external power supply fails, the electrolytic capacitor (C36) 5 and supercapacitor (C60) 7 sequentially discharge into the control unit's main power bus (VCU) 1, maintaining operation of the left-hand circuit. When the battery domain (B3V6) 16 or external battery (BAT2) 20 is valid, the right-hand circuit can still operate normally. When all power supplies fail, the undervoltage detection circuit outputs the LVDIN0 signal, notifying the main controller to perform a safe shutdown.

[0039] This new system utilizes a dual P-MOS control structure, a double-layer energy storage structure, and a priority judgment network to achieve seamless switching of multiple power sources and automatic priority management, significantly extending the power-off hold time and improving system reliability and stability. It also reduces electromagnetic interference and improves the system's electromagnetic compatibility.

[0040] In addition, the test interface makes maintenance more convenient and extends the service life of the system. The overall design does not require a complex control chip and achieves highly reliable multi-source power supply control through pure hardware logic.

[0041] The utility model verifies the technical effects of the multi-source power supply control circuit of the electric energy meter through the following experiments: power-off retention capability, multi-source seamless switching performance, power supply priority management capability and surge current suppression effect.

[0042] 1. Using a comparative test method, the present circuit was compared with a traditional single-electrolytic capacitor solution, a diode OR gate circuit, and a dedicated power management chip solution. The test environment temperature was 25±2°C and the humidity was 45±5%. Each test was repeated three times and the average value was taken to ensure data reliability. A high-precision digital oscilloscope (1GS / s sampling rate), a precision electronic load, and a controllable power simulator were used as the primary test equipment.

[0043] 2. Technical Effect Comparison Table

[0044]

[0045] 3. Verification methods and results

[0046] Power-off retention testing: A conventional single-electrolytic capacitor solution and the dual-layer energy storage structure of our new invention were constructed. The input power was disconnected under a constant load, and the time the output voltage remained above 4.5V was measured. The results showed that the new design maintained this voltage for over 20 seconds, while the conventional solution only lasted 0.5 seconds, consistent with expectations.

[0047] Multi-source switching performance testing: Simulating a scenario where three power supplies (VCU, B3V6, and BAT2) fail sequentially, the voltage waveforms at the moment of switching are recorded. The circuit exhibits a smooth voltage waveform with a voltage fluctuation of no more than 20mV during switching, while a traditional diode OR gate solution exhibits fluctuations of 150-300mV and significant oscillations during switching.

[0048] Inrush current suppression test: Using a large capacitive load (1000μF), the current waveform at power-up was measured. A conventional direct-connect solution generates a 2.5A current peak; the soft-start network in this utility model limits the peak to less than 0.6A, and the current rise curve is gentle, effectively protecting downstream circuits.

[0049] Priority management verification: Power was supplied to the VCU and B3V6 / B6V simultaneously, and the current distribution across each channel was measured. The results showed that the priority determination network in this utility model automatically cuts off the power supply from the VCU to the right circuit, and the current is primarily provided by the high-priority B6V. This achieves the expected priority management function and significantly suppresses circulating current.

[0050] 4. Verify the conclusion

[0051] Experimental verification results show that this new technology offers significant advantages over traditional technologies: power-off holdover time is extended 40 times, transient fluctuations in power switching are reduced by 92%, power-on inrush current is reduced by 76%, power isolation is improved by 35dB, and system maintenance time is reduced by 83%. These improvements address power-off protection and power management issues in electricity meters.

[0052] More importantly, the present invention uses pure hardware logic to achieve automatic management of multi-source power supplies, without the need for a dedicated control chip, thus reducing cost and complexity while improving reliability, and has broad application prospects.

Claims

1. A multi-source power supply control circuit for an electric energy meter, characterized in that: include: Control unit main power supply bus (VCU); A diode OR structure provided on the control unit main power supply bus (VCU), comprising a plurality of diodes (D35, D33, D36) connected in parallel; A double-layer energy storage structure provided on the main power supply bus (VCU) of the control unit, comprising a directly connected electrolytic capacitor (C36) and a supercapacitor (C60) connected via a current-limiting resistor (R90); a dual P-MOS control structure connected in series with the control unit main power bus (VCU), comprising a first P-channel (Q17) and a second P-channel (Q18), wherein the source of the first P-channel (Q17) is connected to the control unit main power bus (VCU); a priority determination network connected to the gate of the second P-channel (Q18), comprising a plurality of diodes (D30, D31, D32) and resistors (R75, R76); A boost converter circuit (U4) connected to the battery domain (B3V6), whose output terminal forms a power bus (B6V); A battery interface circuit is provided between the power bus (B6V) and the external battery (BAT2), comprising a unidirectional conducting diode (D37) and a current limiting resistor (R111).

2. The multi-source power supply control circuit of the electric energy meter according to claim 1, characterized in that: The gate of the first P-channel (Q17) is connected to a soft start network, including a resistor (R82) and a capacitor (C38), for controlling the inrush current during power-on.

3. The multi-source power supply control circuit of the electric energy meter according to claim 1, characterized in that: The priority determination network includes: a first diode (D30) connected to the battery domain (B3V6); a second diode (D32) connected to the power bus (B6V); and a clamping diode (D31) connected to the ground.

4. The multi-source power supply control circuit of an electric energy meter according to claim 1, characterized in that: The supercapacitor (C60) is connected via a test interface (TEST3), so that the supercapacitor (C60) can be disassembled and replaced.

5. The multi-source power supply control circuit of the electric energy meter according to claim 1, characterized in that: The external battery (BAT2) is connected via a test interface (TEST2), and the current limiting resistor (R111) and the diode (D37) are arranged in parallel.

6. The multi-source power supply control circuit of an electric energy meter according to claim 1, characterized in that: The device also includes an undervoltage detection circuit, which includes a voltage-dividing resistor network (R77, R78, R79), a filter capacitor (C37) and a two-stage transistor comparator (Q15, Q16), and is used to output an undervoltage detection signal (LVDIN0).

7. The multi-source power supply control circuit of an electric energy meter according to claim 1, characterized in that: The capacitance of the electrolytic capacitor (C36) is 1000 μF, the capacitance of the supercapacitor (C60) is 0.22 F, and the capacitance ratio between the two is 1:

220.

8. The multi-source power supply control circuit of an electric energy meter according to claim 1, characterized in that: The input end and the output end of the boost conversion circuit (U4) are respectively connected to decoupling capacitors (C39, C40) to minimize the current loop area.

9. The multi-source power supply control circuit of an electric energy meter according to claim 1, characterized in that: Multiple independent reference grounds (GND, GND2, G485, B6V-) are set to form a star connection topology.

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