Gallium nitride power device

Abstract

The utility model provides a gallium nitride power device. The gallium nitride power device comprises a gallium nitride substrate, a first dielectric layer, a dielectric laminated layer and an insulating layer. The first dielectric layer is arranged on the gallium nitride substrate; the first dielectric layer is provided with source ohmic metal and drain ohmic metal; titanium nitride metal layers are arranged on the upper layer surfaces of the source electrode ohmic metal and the drain electrode ohmic metal. A dielectric stack is arranged on the first dielectric layer, the dielectric stack is provided with gate metal, and a gate field plate is arranged around the gate metal; an insulating layer is disposed on the dielectric stack and the gate field plate. The titanium nitride metal layer is arranged on the top of the ohmic metal and serves as an anti-reflection layer in the process of forming the drain electrode ohmic metal and the source electrode ohmic metal through etching, the etching precision can be improved, the accuracy of the drain electrode ohmic metal contour and the accuracy of the source electrode ohmic metal contour are improved, and the smaller device size can be achieved. The number of devices of a single wafer is increased; and the cost is reduced.

Description

Technical Field

[0001] The utility model relates to the field of semiconductor devices, in particular to a gallium nitride power device. Background Art

[0002] Gallium nitride high electron mobility transistors (GaN-HEMTs) offer superior device performance and broad application prospects in high-frequency and high-power applications. Currently, the typical structures of power GaN products are mainly divided into depletion-mode and enhancement-mode devices. The simple structure of depletion-mode GaN devices maximizes the high electron concentration and high electron mobility of GaN heterojunction HEMTs, while also providing a highly reliable gate. Further optimizing the process flow of depletion-mode GaN devices to improve their electrical properties and reliability is of great significance.

[0003] The current GaN technology platform, ohmic metal stack structure, and RTP annealing process all significantly impact ohmic contact resistance. Existing technology typically uses ohmic metal etching to form an ohmic electrode, followed by annealing. However, this process and structure can lead to a decrease in ohmic contact resistance (Rc). To achieve lower device on-resistance, device size must be increased, resulting in a reduction in the number of devices on a single wafer and increased costs. Utility Model Content

[0004] The utility model provides a gallium nitride power device, which improves the accuracy of ohmic metal profile and facilitates the realization of a smaller device size.

[0005] The present invention provides a gallium nitride power device, comprising:

[0006] GaN substrate;

[0007] a first dielectric layer disposed on the gallium nitride substrate, the first dielectric layer comprising a source setting hole and a drain setting hole, wherein a source ohmic metal is disposed in the source setting hole, and a drain ohmic metal is disposed in the drain setting hole; and a titanium nitride metal layer is disposed on upper surfaces of the source ohmic metal and the drain ohmic metal;

[0008] a dielectric stack disposed on the first dielectric layer, wherein the dielectric stack is provided with a source contact through-hole in the region of the source setting hole and a drain contact through-hole in the region of the drain setting hole; the dielectric stack is provided with a gate setting hole, a gate metal is disposed in the gate setting hole, and a gate field plate is disposed around the gate metal; and

[0009] An insulating layer is provided on the dielectric stack and the gate field plate, wherein the insulating layer is provided with a source through hole in the region where the source is provided, a drain through hole in the region where the drain is provided, and a gate contact through hole in the region where the gate is provided.

[0010] The source ohmic metal is T-shaped, with its top two sides located between the dielectric stack and the first dielectric layer, and a diffusion barrier layer is provided between its top two sides and the first dielectric layer; the drain ohmic metal is T-shaped, with its top two sides located between the dielectric stack and the first dielectric layer, and a diffusion barrier layer is provided between its top two sides and the first dielectric layer.

[0011] The gallium nitride substrate includes a silicon substrate, a gallium nitride layer, an aluminum gallium nitride layer, and a silicon nitride layer arranged in sequence; the first dielectric layer is deposited on the gallium nitride substrate on a side away from the silicon substrate; the gallium nitride substrate is provided with a source setting blind hole in the region of the source setting hole, and a drain setting blind hole in the region of the drain setting hole; the depths of both the source setting blind hole and the drain setting blind hole reach the aluminum gallium nitride layer.

[0012] The dielectric stack includes a second dielectric layer, a first barrier layer and a third dielectric layer arranged in sequence from bottom to top; the gate setting hole passes through the second dielectric layer and the first dielectric layer, and the gate metal is in contact with the silicon nitride layer; the gate field plate includes a first field plate and a second field plate; the first field plate is located between the second dielectric layer and the insulating layer, and the second field plate is located between the third dielectric layer and the insulating layer.

[0013] The dielectric stack further includes a second barrier layer and a fourth dielectric layer sequentially arranged on the third dielectric layer; the gate field plate further includes a third field plate, and the third field plate is located between the fourth dielectric layer and the insulating layer.

[0014] The gate metal and the gate field plate are connected; or the gate metal and the gate field plate are separated.

[0015] The diffusion barrier layer is aluminum nitride or aluminum oxide deposited by atomic vapor deposition or physical vapor deposition, or silicon oxide, silicon nitride, or silicon oxynitride with high density deposited by chemical vapor deposition.

[0016] Wherein, the source ohmic metal and the drain ohmic metal are both titanium and aluminum metal stacks.

[0017] Wherein, the top surface of the insulating layer is flat.

[0018] The gallium nitride power devices include but are not limited to MIS-HEMT devices, P-GaN HEMT devices and SBD-Gate HEMT devices.

[0019] In the gallium nitride power device provided by the present invention, a titanium nitride metal layer is provided on top of the ohmic metal. The titanium nitride metal layer serves as an anti-reflection layer during the process of forming the drain and source ohmic metals by etching, thereby improving etching precision and thus improving the accuracy of the drain and source ohmic metal contours, thereby facilitating smaller device size, increasing the number of devices on a single wafer, and reducing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 This is a schematic structural diagram of the gallium nitride power device provided in Example 1 of the present utility model.

[0021] Figure 2A-2L This is a schematic diagram of the manufacturing process of the gallium nitride power device provided in Example 1 of the present invention. DETAILED DESCRIPTION

[0022] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative efforts shall fall within the scope of protection of the present invention.

[0023] Example 1

[0024] like Figure 1 As shown, the GaN power device provided in this embodiment is a D-type GaN high electron mobility transistor, which can be used as a switching device or amplifier device for high-power applications. Here, the GaN power device of this embodiment includes, but is not limited to, a MIS-HEMT device, a P-GaN HEMT device, and an SBD-Gate HEMT device.

[0025] The gallium nitride power device includes a gallium nitride substrate 1, a first dielectric layer 21, a dielectric stack 2, and an insulating layer 7. The gallium nitride substrate 1, the first dielectric layer 21, the dielectric stack 2, and the insulating layer 7 are stacked in sequence.

[0026] The first dielectric layer 21 is disposed on the gallium nitride substrate 1. The first dielectric layer 21 includes a source hole 411 and a drain hole 412. A source ohmic metal 421 is disposed in the source hole 411, and a drain ohmic metal 422 is disposed in the drain hole 412. A titanium nitride metal layer 5 is disposed on the upper surfaces of the source ohmic metal 421 and the drain ohmic metal 422.

[0027] The dielectric stack 2 is disposed on the first dielectric layer 21. The dielectric stack 2 is provided with a source contact through-hole 201 in the region of the source setting hole 411 and a drain contact through-hole 202 in the region of the drain setting hole 412. The dielectric stack 2 is provided with a gate setting hole 206, in which a gate metal 61 is disposed. A gate field plate 62 is disposed around the gate metal 61.

[0028] The insulating layer 7 is provided on the dielectric stack 2 and the gate field plate 62. The insulating layer 7 is provided with a source through hole 701 in the region of the source hole 411, a drain through hole 702 in the region of the drain hole 412, and a gate contact through hole 703 in the region of the gate hole.

[0029] The upper surfaces of the source ohmic metal 421 and the drain ohmic metal 422 are both provided with a titanium nitride metal layer 5. The titanium nitride metal layer 5 serves as an anti-reflection layer in the process of forming the source ohmic metal 421 and the drain ohmic metal 422 by etching, which can improve the etching accuracy, thereby improving the accuracy of the contours of the source ohmic metal 421 and the drain ohmic metal 422, which is conducive to achieving a smaller device size, increasing the number of devices on a single wafer and reducing costs; the titanium nitride metal layer 5 can also serve as an etching stop layer for preparing the source contact through hole 201 and the drain contact through hole 202, to ensure the accuracy of the source and drain.

[0030] The ohmic metal layer used to prepare the source ohmic metal 421 and the drain ohmic metal 422 does not need to be annealed simultaneously with the titanium nitride metal layer 5 , thereby effectively solving the problem of deterioration of ohmic contact resistance.

[0031] The source ohmic metal 421 is T-shaped, with its top edges located between the dielectric stack 2 and the first dielectric layer 21, and a diffusion barrier layer 3 disposed between the source and drain ohmic metal 422. The drain ohmic metal 422 is T-shaped, with its top edges located between the dielectric stack 2 and the first dielectric layer 21, and a diffusion barrier layer 3 disposed between the drain and drain ohmic metal 422. Diffusion barrier layers 3 are disposed between the top edges of both the source and drain ohmic metals 421 and the first dielectric layer 21, preventing the ohmic metal from diffusing into the first dielectric layer 21 during annealing, effectively improving chip reliability.

[0032] In this embodiment, the gallium nitride substrate 1 includes a silicon substrate 11, a gallium nitride (GaN) layer 12, an aluminum gallium nitride (ALGaN) layer 13, and a silicon nitride (SiN) layer 14. The first dielectric layer 21 is located on a side of the gallium nitride substrate 1 away from the silicon substrate 11.

[0033] The gallium nitride substrate is provided with a source blind hole 101 in the region of the source hole 411, and a drain blind hole 102 in the region of the drain hole 412. The depth of both the source blind hole 101 and the drain blind hole 102 reaches the aluminum gallium nitride layer 13, so that the fabricated source ohmic metal 421 and drain ohmic metal 422 can contact the aluminum gallium nitride layer 13.

[0034] The source ohmic metal 421 and the drain ohmic metal 422 are preferably a stack of titanium and aluminum metals. Titanium has strong adhesion to the gallium nitride substrate, which can ensure the mechanical stability of the ohmic metal contact; aluminum can naturally form an ohmic contact with the gallium nitride substrate. Of course, here, in other embodiments, the source ohmic metal 421 and the drain ohmic metal 422 can also be a multilayer structure formed by different combinations of metals such as titanium, aluminum, nickel, and gold. The dielectric stack 2 includes a second dielectric layer 22, a first barrier layer 25, a third dielectric layer 23, a second barrier layer 26, and a fourth dielectric layer 24, which are arranged in sequence from bottom to top. Among them, the first barrier layer 25 can serve as an etch stop layer when etching the third dielectric layer 23, and the second barrier layer 26 can serve as an etch stop layer when etching the fourth dielectric layer 24.

[0035] The gate setting hole 206 penetrates the second dielectric layer 22 and the first dielectric layer 21. After the gate metal 61 is set in the gate setting hole 206, it contacts the silicon nitride layer 14 on the surface of the gallium nitride substrate 1, thereby being insulated from the source ohmic metal 421 and the drain ohmic metal 422 by the silicon nitride layer 14.

[0036] The gate field plate 62 includes a first field plate 621, a second field plate 622, and a third field plate 623. The first field plate 621 is located between the second dielectric layer 22 and the insulating layer 7, the second field plate 622 is located between the third dielectric layer 23 and the insulating layer 7, and the third field plate 623 is located between the fourth dielectric layer 24 and the insulating layer 7. The dielectric stack 2 allows the gate field plate 62 to have a multi-layer structure, thereby controlling the electric field distribution.

[0037] In this embodiment, the gate metal 61 is connected to the gate field plate 62 for ease of fabrication. Of course, in other embodiments, the gate metal 61 can also be separated from the gate field plate to avoid stress caused by connecting large pieces of metal and thus improve device reliability.

[0038] The top surface of the insulating layer 7 is flat, so that the upper surface of the GaN power device is relatively flat, which is beneficial for subsequent processing and reduces the overall volume of the GaN power device.

[0039] The manufacturing process of the gallium nitride power device with an ohmic metal barrier layer provided by the present invention is as follows.

[0040] Step S10 : providing a gallium nitride substrate 1 , and depositing a first dielectric layer 21 on the gallium nitride substrate 1 .

[0041] In this step, if Figure 2A As shown, the gallium nitride substrate 1 includes a silicon substrate 11, a gallium nitride (GaN) layer 12, an aluminum gallium nitride (ALGaN) layer 13, and a silicon nitride (SiN) layer 14. A first dielectric layer 21 is deposited on the side of the gallium nitride substrate 1 away from the silicon substrate 11.

[0042] Step S20: depositing a diffusion barrier layer 3 on the first dielectric layer 21. Figure 2B FIG. 1 is a schematic diagram of the structure after the diffusion barrier layer 3 is deposited.

[0043] The diffusion barrier layer 3 can prevent the ohmic metal from diffusing into the first dielectric layer 21 in subsequent steps.

[0044] The diffusion barrier layer 3 is aluminum nitride or aluminum oxide deposited by atomic vapor deposition or physical vapor deposition, or silicon oxide, silicon nitride, or silicon oxynitride deposited by chemical vapor deposition. In this embodiment, the diffusion barrier layer 3 is an aluminum nitride layer.

[0045] The diffusion barrier layer 3 is a dielectric layer with good density, which is used to prevent the ohmic metal layer from diffusing into the first dielectric layer 21 below during the annealing process, thereby improving the reliability of the device.

[0046] Step S30, as Figure 2C As shown, the diffusion barrier layer 3, first dielectric layer 21, and gallium nitride substrate 1 in the source and drain regions are etched. After the first dielectric layer 21 is etched through, source and drain holes 411 and 412 are formed. Source hole 411 is located in the source region, and drain hole 412 is located in the drain region. Etching the gallium nitride substrate 1 also forms source and drain blind holes 101 and 102. Source blind hole 101 is located in the source region and communicates with source hole 411. Drain blind hole 102 is located in the drain region and communicates with drain hole 412.

[0047] The depths of the source blind hole 101 and the drain blind hole 102 reach the aluminum gallium nitride layer 13 , so that the fabricated source ohmic metal and drain ohmic metal can contact the aluminum gallium nitride layer 13 .

[0048] Step S40 , depositing an ohmic metal layer 4 , and performing annealing treatment on the ohmic metal layer 4 .

[0049] like Figure 2D FIG. 4 is a schematic diagram of the structure after depositing and annealing the ohmic metal layer 4. Annealing can ensure that a good contact resistance is obtained.

[0050] In this step, the ohmic metal layer 4 covers the diffusion barrier layer 3 and fills the drain blind hole 102, drain hole 412, source blind hole 101, and source hole 411. The ohmic metal layer 4 is preferably a stack of titanium and aluminum. Titanium has strong adhesion to the gallium nitride substrate, ensuring the mechanical stability of the ohmic metal contact; aluminum naturally forms an ohmic contact with the gallium nitride substrate. Of course, in other embodiments, the ohmic metal layer 4 can also be a multilayer structure formed by various combinations of metals, such as titanium, aluminum, nickel, and gold.

[0051] In this step, the ohmic metal layer may be annealed using an RTP (Rapid Thermal Processing) annealing process to repair lattice defects, eliminate stress, and optimize the conductive properties of the material.

[0052] Because the diffusion barrier layer 3 is added to protect the first dielectric layer 21 before depositing the ohmic metal layer, the ohmic metal can be prevented from diffusing into the first dielectric layer 21 during the RTP annealing process, thereby effectively improving chip reliability.

[0053] Step S50 , depositing a titanium nitride metal layer 5 on the ohmic metal layer 4 .

[0054] The titanium nitride metal layer 5 covers the ohmic metal layer 4. Figure 2E FIG. 1 is a schematic diagram of the structure after the titanium nitride metal layer 5 is deposited.

[0055] The ohmic metal layer 4 is annealed before the titanium nitride metal layer 5 is deposited, so that the titanium nitride metal layer and the ohmic metal layer are not annealed at the same time to avoid affecting the performance of the contact resistance.

[0056] Step S60, etching the titanium nitride metal layer 5, the ohmic metal layer 4 and the diffusion barrier layer 3 outside the source region and the drain region to form a source ohmic metal 421 and a drain ohmic metal 422. Figure 2F , which is a schematic structural diagram after the source ohmic metal 421 and the drain ohmic metal 422 are formed.

[0057] When etching the ohmic metal layer 4, the titanium nitride metal layer 5 acts as an anti-reflection layer, which can improve the etching accuracy, thereby improving the accuracy of the ohmic metal profile, which is conducive to achieving smaller device size, increasing the number of devices on a single wafer and reducing costs; the subsequent titanium nitride metal layer 5 can also serve as an etching stop layer for the through holes at the source and drain to ensure the accuracy of the source and drain.

[0058] Step S70, as Figure 2G As shown, a dielectric stack 2 is deposited on the source ohmic metal 421 , the drain ohmic metal 422 and the first dielectric layer 21 .

[0059] Step S80 , etching the dielectric stack 2 in the gate region and the field plate region to form the gate setting hole 106 and the field plate region.

[0060] In this embodiment, Figure 2G As shown, the dielectric stack 2 includes a second dielectric layer 22, a first barrier layer 25, a third dielectric layer 23, a second barrier layer 26, and a fourth dielectric layer 24, which are deposited in sequence. The first barrier layer 25 can serve as an etch stop layer when etching the third dielectric layer 23, and the second barrier layer 26 can serve as an etch stop layer when etching the fourth dielectric layer 24. The field plate region includes a first field plate region, a second field plate region, and a third field plate region.

[0061] In step S80 , the fourth dielectric layer 24 , the second barrier layer 26 , the third dielectric layer 23 , the first barrier layer 25 , the second dielectric layer 22 and the first dielectric layer 21 are sequentially etched to expose the silicon nitride layer 14 to form a gate region and a field plate region.

[0062] The gate region has a depth reaching the silicon nitride layer 14 so that the gate metal can contact the silicon nitride layer 14 ;

[0063] Step S80 specifically includes the following sub-steps.

[0064] Step S81, as Figure 2H As shown, the fourth dielectric layer 24 and the second barrier layer 26 are etched through to form a third field plate region on the fourth dielectric layer 24 .

[0065] Step S82, as Figure 2I As shown, the third dielectric layer 23 and the first barrier layer are etched through at the gate region and on both sides thereof to form a first field plate region on the second dielectric layer 22 and a second field plate region on the third dielectric layer 23 .

[0066] Step S83, as Figure 2J As shown, the second dielectric layer 22 and the first dielectric layer 21 are etched through at the gate region to expose the silicon nitride layer 14 to form the gate region.

[0067] In the gate metal step S9, a metal layer is deposited and the metal outside the gate region and the field plate region is etched to form a gate metal 61 and a gate field plate 62. Figure 2K , which is a schematic diagram of the structure after the gate metal 61 and gate field plate 62 are prepared and formed. The gate metal 61 is located in the gate region, and the gate field plate 62 is located in the field plate region. It includes a first field plate 621, a second field plate 622, and a third field plate 623. The first field plate 621 is located in the first field plate region, i.e., on the second dielectric layer 22; the second field plate 622 is located in the second field plate region, i.e., on the third dielectric layer 23; and the third field plate 623 is located in the third field plate region, i.e., on the fourth dielectric layer 24.

[0068] In this embodiment, the gate setting hole, the first field plate region, the second field plate region, and the third field plate region are sequentially arranged adjacent to each other, so that the prepared gate metal 61 is connected to the gate field plate 62. Here, in other embodiments, the gate setting hole, the first field plate region, the second field plate region, and the third field plate region may not be connected to each other, so that the prepared gate metal and the gate field plate are separated; or, the tertiary region is connected to the field plate region, but when preparing the gate metal and the gate field plate, the gate metal and the gate field plate are separated by etching so that the two are not connected, that is, separated, to avoid stress caused by the connection of large pieces of metal and thus damage to the device, thereby improving device reliability.

[0069] In step S100 , an insulating layer 7 is deposited on the dielectric stack 2 , the gate metal 61 and the gate field plate 62 and planarized.

[0070] In this embodiment, the insulating layer 7 is an interlayer dielectric (ILD) layer.

[0071] In this step, the surface of the insulating layer 7 can be polished by chemical mechanical polishing to make the upper surface of the insulating layer 7 a flat surface. Figure 2L FIG. 1 is a schematic diagram of the structure after step S100 is completed.

[0072] Step S110, as Figure 1 As shown, the insulating layer 7 in the gate region is etched to form a gate contact through hole 703; at the same time, the insulating layer 7, the dielectric stack 2 and the titanium nitride metal layer 5 in the source and drain regions are etched. After the insulating layer 7 is etched in the source region, a source through hole 701 is formed, and after the insulating layer 7 is etched in the drain region, a drain through hole 702 is formed. After the dielectric stack 2 is etched in the source region, a source contact through hole 201 is formed, and after the dielectric stack 2 is etched in the drain region, a drain contact through hole 202 is formed.

[0073] In the gate metal step S120, a metal layer is deposited on the insulating layer 7, and the metal layer other than the gate contact hole, the source contact hole and the drain contact hole is etched. The metal layer contacts the source ohmic metal through the source contact through-hole and the source through-hole to form a source. The metal layer contacts the drain ohmic metal through the drain contact through-hole and the drain through-hole to form a drain. The metal layer contacts the gate metal through the gate contact through-hole to form a gate.

[0074] The gallium nitride power device provided by the utility model performs an annealing treatment before depositing a titanium nitride metal layer on the ohmic metal layer to ensure the overall shape of the ohmic metal layer, effectively solving the problem of ohmic contact resistance degradation. After the ohmic metal layer is annealed, a titanium nitride metal layer is deposited, and then the titanium nitride metal layer and the ohmic metal layer are etched. In this process, the titanium nitride metal layer acts as an anti-reflection layer, which can improve etching precision, thereby improving the accuracy of the source and drain ohmic metal profiles, facilitating smaller device size, increasing the number of devices per single wafer, and reducing costs. The subsequent titanium nitride metal layer can serve as an etch stop layer for the through holes at the source and drain electrodes, ensuring the accuracy of the source and drain electrodes. A diffusion barrier layer is provided between the top sides of the source and drain ohmic metal and the first dielectric layer to prevent the ohmic metal from diffusing into the first dielectric layer during the annealing process, effectively improving chip reliability.

[0075] Example 2

[0076] In this embodiment, the dielectric stack includes a second dielectric layer, a first barrier layer, and a third dielectric layer deposited sequentially; wherein the first barrier layer can serve as an etch stop layer when etching the third dielectric layer. The field plate region includes a first field plate region and a second field plate region. The gate field plate includes a first field plate and a second field plate, wherein the first field plate is located between the second dielectric layer and the insulating layer, and the second field plate is located between the third dielectric layer and the insulating layer. Compared with Example 1, the number of dielectric layers in the dielectric stack and the number of gate field plates are reduced. The other structures of Example 2 are the same as those of Example 1 and are not further described here.

[0077] The manufacturing process of Example 2 differs from that of Example 1 in step S80, which is specifically as follows.

[0078] In step S80 , the third dielectric layer, the first barrier layer, the second dielectric layer, and the first dielectric layer are sequentially etched through to expose the silicon nitride layer, thereby forming a gate region and a field plate region.

[0079] Specifically, step S80 includes the following sub-steps.

[0080] Step S81 , etching through the third dielectric layer and the first barrier layer at the gate region and on both sides thereof to form a first field plate region on the second dielectric layer and a second field plate region on the third dielectric layer.

[0081] In step S82 , the second dielectric layer and the first dielectric layer are etched through at the gate region to expose the silicon nitride layer 14 , thereby forming a gate region.

[0082] At this point, step S80 of another embodiment is completed.

[0083] As can be seen from the above, the second barrier layer and the fourth dielectric layer may not be provided in the dielectric stack. Therefore, the number of dielectric layers and barrier layers may be determined according to the structural requirements of the gate field plate.

[0084] The present invention also provides a gallium nitride power device with an ohmic metal barrier layer. The structure of the device differs from that of Example 1 in that the device does not have a fourth dielectric layer or a second barrier layer. Accordingly, the gate field plate does not include a third field plate. The other structural parts are the same as those of the first embodiment and will not be described in detail here.

[0085] In summary, although the present invention has been disclosed above with reference to preferred embodiments, the above preferred embodiments are not intended to limit the present invention. A person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope defined by the claims.

Claims

1. A gallium nitride power device, characterized in that: include: GaN substrate; a first dielectric layer disposed on the gallium nitride substrate, the first dielectric layer comprising a source setting hole and a drain setting hole, wherein a source ohmic metal is disposed in the source setting hole, and a drain ohmic metal is disposed in the drain setting hole; and a titanium nitride metal layer is disposed on upper surfaces of the source ohmic metal and the drain ohmic metal; a dielectric stack, disposed on the first dielectric layer, wherein the dielectric stack is provided with a source contact through-hole in the region where the source hole is provided, and a drain contact through-hole in the region where the drain hole is provided; The dielectric stack is provided with a gate setting hole, a gate metal is provided in the gate setting hole, and a gate field plate is provided around the gate metal; and An insulating layer is provided on the dielectric stack and the gate field plate, wherein the insulating layer is provided with a source through hole in the region where the source is provided, a drain through hole in the region where the drain is provided, and a gate contact through hole in the region where the gate is provided.

2. The gallium nitride power device according to claim 1, characterized in that: The source ohmic metal is T-shaped, with its top two sides located between the dielectric stack and the first dielectric layer, and a diffusion barrier layer is provided between its top two sides and the first dielectric layer; the drain ohmic metal is T-shaped, with its top two sides located between the dielectric stack and the first dielectric layer, and a diffusion barrier layer is provided between its top two sides and the first dielectric layer.

3. The gallium nitride power device according to claim 2, characterized in that: The gallium nitride substrate includes a silicon substrate, a gallium nitride layer, an aluminum gallium nitride layer, and a silicon nitride layer arranged in sequence; the first dielectric layer is deposited on the gallium nitride substrate on a side away from the silicon substrate; the gallium nitride substrate is provided with a source setting blind hole in the region of the source setting hole, and a drain setting blind hole in the region of the drain setting hole; the depths of both the source setting blind hole and the drain setting blind hole reach the aluminum gallium nitride layer.

4. The gallium nitride power device according to claim 3, characterized in that: The dielectric stack includes a second dielectric layer, a first barrier layer and a third dielectric layer arranged in sequence from bottom to top; the gate setting hole penetrates the second dielectric layer and the first dielectric layer, and the gate metal contacts the silicon nitride layer; the gate field plate includes a first field plate and a second field plate; the first field plate is located between the second dielectric layer and the insulating layer, and the second field plate is located between the third dielectric layer and the insulating layer.

5. The gallium nitride power device according to claim 2, characterized in that: The dielectric stack further includes a second barrier layer and a fourth dielectric layer sequentially arranged on the third dielectric layer; the gate field plate further includes a third field plate, and the third field plate is located between the fourth dielectric layer and the insulating layer.

6. The gallium nitride power device according to claim 1, characterized in that: The gate metal and the gate field plate are connected; or, the gate metal and the gate field plate are separated.

7. The gallium nitride power device according to claim 2, characterized in that: The diffusion barrier layer is aluminum nitride or aluminum oxide deposited by atomic vapor deposition or physical vapor deposition, or silicon oxide, silicon nitride, or silicon oxynitride with high density deposited by chemical vapor deposition.

8. The gallium nitride power device according to claim 1, characterized in that: The source ohmic metal and the drain ohmic metal are both titanium and aluminum metal stacks.

9. The gallium nitride power device according to claim 1, characterized in that: The top surface of the insulating layer is flat.

10. The gallium nitride power device according to claim 1, characterized in that: The gallium nitride power devices include but are not limited to MIS-HEMT devices, P-GaN HEMT devices and SBD-Gate HEMT devices.

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