Display substrate and display device

Abstract

The embodiment of the utility model provides a display substrate and a display device. The display substrate comprises a plurality of repetitive units, at least one repetitive unit comprises a display unit and a light-transmitting unit, at least one display unit comprises a plurality of sub-pixels, at least one sub-pixel comprises a pixel driving circuit and a compensation signal line, and the compensation signal line is configured to provide a compensation signal for the pixel driving circuit; in the direction perpendicular to the display substrate, the display substrate comprises a plurality of conducting layers arranged on a substrate, one conducting layer is internally provided with a compensation block and a compensation signal line, the compensation block is connected with the compensation signal line, at least another conducting layer is internally provided with an electrode block, and the electrode block is connected with the compensation signal line. The orthographic projection of the compensation block on the substrate and the orthographic projection of the electrode block on the substrate are at least partially overlapped, and the compensation block and the electrode block form a parasitic capacitor.

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) are active light-emitting display devices. They offer advantages such as active illumination, ultra-thinness, wide viewing angles, high brightness, high contrast, low power consumption, extremely fast response times, lightweight design, customizable form factors, and flexible displays. They are becoming a highly promising next-generation display technology. Active Matrix (AM) OLEDs are current-driven devices that use independent thin film transistors (TFTs) to control each sub-pixel, allowing each sub-pixel to emit light continuously and independently.

[0003] Currently, existing display devices have problems such as low pixel anti-interference capability. Utility Model Content

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] The technical problem to be solved by the embodiments of the present disclosure is to provide a display substrate and a display device to solve the problems of low pixel anti-interference ability in existing display devices.

[0006] On the one hand, an embodiment of the present disclosure provides a display substrate, comprising a plurality of repeating units, at least one repeating unit comprising a display unit and a light-transmitting unit located on at least one side of the display unit, the display unit being configured to display an image, and the light-transmitting unit being configured to transmit light; the display unit comprising a plurality of sub-pixels, at least one sub-pixel comprising a pixel driving circuit and a compensation signal line, the compensation signal line being configured to provide a compensation signal to the pixel driving circuit; in a direction perpendicular to the display substrate, the display substrate comprising a plurality of conductive layers arranged on a base, a compensation block and the compensation signal line being provided in one conductive layer, the compensation block being connected to the compensation signal line, an electrode block being provided in at least another conductive layer, the orthographic projection of the compensation block on the base being at least partially overlapped with the orthographic projection of the electrode block on the base, and the compensation block and the electrode block forming a parasitic capacitor.

[0007] In an exemplary embodiment, the pixel driving circuit includes at least a first transistor, a gate electrode of the first transistor is connected to a first scanning signal line, and a first electrode of the first transistor is connected to a data signal line; the first scanning signal line is in the shape of a straight line or a broken line extending along a first direction, and the compensation signal line is in the shape of a straight line or a broken line extending along a second direction, and the first direction and the second direction intersect; in at least one repeating unit, a first electrode block is provided on the first scanning signal line, and the first electrode block and the first scanning signal line are an integrated structure connected to each other; a first compensation block is provided on the compensation signal line, and the first compensation block and the compensation signal line are an integrated structure connected to each other, and the orthographic projection of the first compensation block on the substrate at least partially overlaps with the orthographic projection of the first electrode block on the substrate, and the first compensation block and the first electrode block form a first parasitic capacitor.

[0008] In an exemplary embodiment, the data signal line is in the shape of a straight line or a broken line extending along the second direction, and the compensation signal line is arranged between two adjacent data signal lines in the first direction; in at least one repeating unit, the spacing between the compensation signal line and the adjacent data signal line is greater than the spacing between the first compensation block and the adjacent data signal line.

[0009] In an exemplary embodiment, the compensation signal line has a signal line width, the first compensation block has a first compensation width, and a ratio of the first compensation width to the signal line width is 1.5 to 2.5; the signal line width and the first compensation width are dimensions in the first direction.

[0010] In an exemplary embodiment, the plurality of sub-pixels include a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel, the second sub-pixel being arranged on one side of the first sub-pixel in a first direction, the fourth sub-pixel being arranged on one side of the third sub-pixel in the first direction, the third sub-pixel being arranged on one side of the first sub-pixel in a second direction, and the fourth sub-pixel being arranged on one side of the second sub-pixel in the second direction; the first scan signal line being connected to the gate electrode of the first transistor in the third sub-pixel and the gate electrode of the first transistor in the fourth sub-pixel; and at least one repeating unit further comprising a first scan auxiliary line and a first scan connection line, the first scan auxiliary line being connected to the gate electrode of the first transistor in the third sub-pixel and the gate electrode of the first transistor in the fourth sub-pixel. The first scanning auxiliary line is connected to the first scanning signal line through the first scanning connection line, and the first scanning auxiliary line is connected to the gate electrode of the first transistor in the first sub-pixel and the gate electrode of the first transistor in the second sub-pixel; a third electrode block is provided on the first scanning auxiliary line, and the third electrode block and the first scanning auxiliary line are an integrated structure connected to each other; a third compensation block is provided on the compensation signal line, and the third compensation block and the compensation signal line are an integrated structure connected to each other, the positive projection of the third compensation block on the substrate at least partially overlaps with the positive projection of the third electrode block on the substrate, and the third compensation block and the third electrode block form a third parasitic capacitor.

[0011] In an exemplary embodiment, the data signal line is in the shape of a straight line or a broken line extending along the second direction, and the compensation signal line is arranged between two adjacent data signal lines in the first direction; in at least one repeating unit, the spacing between the compensation signal line and the adjacent data signal line is greater than the spacing between the third compensation block and the adjacent data signal line.

[0012] In an exemplary embodiment, the compensation signal line has a signal line width, the third compensation block has a third compensation width, and a ratio of the third compensation width to the signal line width is 1.5 to 2.5; the signal line width and the third compensation width are dimensions in the first direction.

[0013] In an exemplary embodiment, the first scan signal line and the first scan auxiliary line are disposed in the same conductive layer, and the first scan connection line is disposed in another conductive layer.

[0014] In an exemplary embodiment, the pixel driving circuit includes at least a third transistor, a gate electrode of the third transistor is connected to a second scanning signal line, and a first electrode of the third transistor is connected to the compensation signal line; the second scanning signal line is in the shape of a straight line or a broken line extending along a first direction, and the compensation signal line is in the shape of a straight line or a broken line extending along a second direction, and the first direction and the second direction intersect; in at least one repeating unit, a second electrode block is provided on the second scanning signal line, the second electrode block and the second scanning signal line are an integrated structure connected to each other, and a second compensation block is provided on the compensation signal line, the second compensation block and the compensation signal line are an integrated structure connected to each other, the orthographic projection of the second compensation block on the substrate at least partially overlaps with the orthographic projection of the second electrode block on the substrate, and the second compensation block and the second electrode block form a second parasitic capacitor.

[0015] In an exemplary embodiment, the sub-pixel further includes a data signal line, which is configured to provide a data signal to the pixel driving circuit, and the data signal line and the compensation signal line are in the shape of a straight line or a broken line extending along the second direction, and the compensation signal line is arranged between two adjacent data signal lines in the first direction, and the first direction and the second direction intersect; in at least one repeating unit, the spacing between the compensation signal line and the adjacent data signal line is greater than the spacing between the second compensation block and the adjacent data signal line.

[0016] In an exemplary embodiment, the compensation signal line has a signal line width, the second compensation block has a second compensation width, and a ratio of the second compensation width to the signal line width is 1.5 to 2.5; the signal line width and the second compensation width are dimensions in the first direction.

[0017] In an exemplary embodiment, the plurality of sub-pixels include a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel, the second sub-pixel is arranged on one side of the first sub-pixel in a first direction, the fourth sub-pixel is arranged on one side of the third sub-pixel in the first direction, the third sub-pixel is arranged on one side of the first sub-pixel in a second direction, and the fourth sub-pixel is arranged on one side of the second sub-pixel in the second direction, and the first direction and the second direction intersect; the second scan signal line is connected to the gate electrode of the third transistor in the third sub-pixel and the gate electrode of the third transistor in the fourth sub-pixel; at least one repeating unit further includes a second scan auxiliary line and a second scan connection line, and the The second scanning auxiliary line is connected to the second scanning signal line through the second scanning connection line, and the second scanning auxiliary line is connected to the gate electrode of the third transistor in the first sub-pixel and the gate electrode of the third transistor in the second sub-pixel; a fourth electrode block is provided on the second scanning auxiliary line, and the fourth electrode block and the second scanning auxiliary line are an integrated structure connected to each other; a fourth compensation block is provided on the compensation signal line, and the fourth compensation block and the compensation signal line are an integrated structure connected to each other, and the orthographic projection of the fourth compensation block on the substrate at least partially overlaps with the orthographic projection of the fourth electrode block on the substrate, and the fourth compensation block and the fourth electrode block form a fourth parasitic capacitor.

[0018] In an exemplary embodiment, the sub-pixel further includes a data signal line, which is configured to provide a data signal to the pixel driving circuit, and the data signal line and the compensation signal line are in the shape of a straight line or a broken line extending along the second direction, and the compensation signal line is arranged between two adjacent data signal lines in the first direction, and the first direction and the second direction intersect; in at least one repeating unit, the spacing between the compensation signal line and the adjacent data signal line is greater than the spacing between the fourth compensation block and the adjacent data signal line.

[0019] In an exemplary embodiment, the compensation signal line has a signal line width, the fourth compensation block has a fourth compensation width, and a ratio of the fourth compensation width to the signal line width is 1.5 to 2.5; the signal line width and the fourth compensation width are dimensions in the first direction.

[0020] In an exemplary embodiment, the second scan signal line, the second scan auxiliary line, and the second scan connection line are provided in the same conductive layer and are interconnected in an integrated structure.

[0021] In an exemplary embodiment, the pixel driving circuit further includes a second transistor, a gate electrode of the second transistor being connected to the second electrode of the first transistor, a first electrode of the second transistor being connected to the first power line via a power connection electrode, and a second electrode of the second transistor being connected to the second electrode of the third transistor; at least one repeating unit further includes a fifth electrode block, the fifth electrode block being arranged between the power connection electrodes of two adjacent sub-pixels and connected to the two power connection electrodes; at least one fifth compensation block is arranged on the compensation signal line, an orthographic projection of the fifth compensation block on the display substrate plane at least partially overlaps with an orthographic projection of the fifth electrode block on the display substrate plane, and the fifth compensation block and the fifth electrode block form a fifth parasitic capacitor.

[0022] In an exemplary embodiment, the sub-pixel further includes a data signal line, which is configured to provide a data signal to the pixel driving circuit, and the data signal line and the compensation signal line are in the shape of a straight line or a broken line extending along the second direction, and the compensation signal line is arranged between two adjacent data signal lines in the first direction, and the first direction and the second direction intersect; in at least one repeating unit, the spacing between the compensation signal line and the adjacent data signal line is greater than the spacing between the fifth compensation block and the adjacent data signal line.

[0023] In an exemplary embodiment, the compensation signal line has a signal line width, the fifth compensation block has a fifth compensation width, and a ratio of the fifth compensation width to the signal line width is 1.5 to 2.5; the signal line width and the fifth compensation width are dimensions in the first direction.

[0024] On the other hand, an embodiment of the present disclosure further provides a display device, comprising the aforementioned display substrate.

[0025] The embodiments of the present disclosure provide a display substrate and a display device. By setting electrode blocks and compensation blocks, the electrode blocks and the compensation blocks form parasitic capacitance, which effectively increases the parasitic capacitance of the compensation signal line, effectively increases the anti-interference ability of the compensation signal line, reduces the interference of the compensation signal by external factors, improves the accuracy of the pixel compensation value, and ensures the display effect and display quality.

[0026] Other aspects will become apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0028] Figure 1 is a structural schematic diagram of a display device;

[0029] Figure 2 Schematic diagram of a planar structure of a transparent display substrate;

[0030] Figure 3 A schematic diagram of the arrangement of sub-pixels in a repeating unit according to an exemplary embodiment of the present disclosure;

[0031] Figure 4 An equivalent circuit diagram of a pixel driving circuit in a display unit according to an exemplary embodiment of the present disclosure;

[0032] Figure 5 This is a schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0033] Figure 6 This is a schematic diagram after forming a first conductive layer pattern according to an embodiment of the present disclosure;

[0034] Figure 7A and Figure 7B A schematic diagram of a semiconductor layer pattern formed according to an embodiment of the present disclosure;

[0035] Figure 8A and Figure 8B This is a schematic diagram after forming a second conductive layer pattern according to an embodiment of the present disclosure;

[0036] Figure 9 This is a schematic diagram of an embodiment of the present disclosure after forming a third insulating layer pattern;

[0037] Figure 10A and Figure 10B This is a schematic diagram of an embodiment of the present disclosure after forming a third conductive layer pattern;

[0038] Figure 10C for Figure 10A Enlarged view of area A in the middle;

[0039] Figure 10D for Figure 10A Enlarged view of area B in the middle;

[0040] Figure 11 This is a schematic diagram of the embodiment of the present disclosure after forming patterns of a planar layer and a fourth insulating layer;

[0041] Figure 12A and Figure 12B This is a schematic diagram of an embodiment of the present disclosure after forming a fourth conductive layer pattern;

[0042] Figure 13A and Figure 13B This is a schematic diagram of the embodiment of the present disclosure after forming the fifth conductive layer pattern.

[0043] Description of the accompanying drawings:

[0044] 11—first electrode plate; 12—second electrode plate; 13—third electrode plate;

[0045] 14—board-level connection electrode; 21—first active layer; 22—second active layer;

[0046] 23—third active layer; 24—second gate electrode; 25—power connection electrode;

[0047] 31—first scanning signal line; 32—second scanning signal line; 33—first scanning auxiliary line;

[0048] 34—Second scanning auxiliary line; 35—First scanning connecting line; 36—Second scanning connecting line;

[0049] 41—First power supply auxiliary line; 42—Second power supply auxiliary line; 43—Power supply connection bar;

[0050] 44—compensation connection line; 51—first connection electrode; 52—second connection electrode;

[0051] 53—third connecting electrode; 54—fourth connecting electrode; 55—fifth connecting electrode;

[0052] 56—anode connection electrode; 61—first power line; 62—second power line;

[0053] 63—data signal line; 64—compensation signal line; 71—first electrode;

[0054] 71-1—first sub-electrode; 71-2—second sub-electrode; 71-3—sub-connecting electrode;

[0055] 72—second electrode; 72-1—third sub-electrode; 72-2—fourth sub-electrode;

[0056] 81—first electrode block; 82—second electrode block; 83—third electrode block;

[0057] 84—fourth electrode block; 85—fifth electrode block; 91—first compensation block;

[0058] 92—second compensation block; 93—third compensation block; 94—fourth compensation block;

[0059] 95—fifth compensation block; 100—repeating unit; 110—display unit;

[0060] 120—Light-transmitting unit. DETAILED DESCRIPTION

[0061] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0062] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0063] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0064] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0065] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0066] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0067] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" can be interchanged, and "source terminal" and "drain terminal" can be interchanged.

[0068] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0069] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0070] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0071] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0072] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0073] Figure 1 FIG. 1 is a schematic diagram of the structure of a display device. Figure 1As shown, an OLED display device may include a timing controller, a data driver, a scan driver, and a pixel array. The timing controller is respectively connected to the data driver and the scan driver. The data driver is respectively connected to a plurality of data signal lines (D1 to Dn). The scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm). The pixel array may include a plurality of sub-pixels Pxij. Each sub-pixel Pxij may be connected to a corresponding data signal line and a corresponding scan signal line. i and j may be natural numbers. At least one sub-pixel Pxij may include at least a circuit unit and a display unit. The circuit unit may include at least a pixel driving circuit. The pixel driving circuit is respectively connected to the scan signal line and the data signal line. The display unit may include at least a light-emitting device. The light-emitting device is connected to the pixel driving circuit of the circuit unit. Sub-pixel Pxij may refer to a sub-pixel whose pixel driving circuit is connected to the i-th scan signal line and the j-th data signal line. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, and may provide a clock signal, a scan start signal, etc. suitable for the specifications of the scan driver to the scan driver. The data driver can generate data voltages to be provided to data signal lines D1, D2, D3, ... and Dn using the grayscale values ​​and control signals received from the timing controller, where n can be a natural number. For example, the data driver can sample the grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to the data signal lines D1 to Dn in units of pixel rows. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ... and Sm by receiving a clock signal, a scan start signal, etc. from the timing controller, where m can be a natural number. For example, the scan driver can be constructed in the form of a shift register and can generate scan signals by sequentially transmitting the scan start signal provided in the form of a conduction level pulse to the next level circuit under the control of the clock signal. In an exemplary embodiment, the pixel array can be provided on a display substrate.

[0074] With the continuous development of display technology, OLED technology is increasingly used in transparent displays. Transparent display is an important personalized display field of display technology. It refers to the display of images in a transparent state. Viewers can not only see the image in the display device, but also the scene behind the display device, which can realize virtual reality (VR) and augmented reality (AR) and 3D display functions. Transparent display devices using OLED technology usually divide each sub-pixel into a display area and a light-transmitting area. The display area is equipped with a pixel driving circuit and a light-emitting device to realize image display, and the light-transmitting area realizes light transmission.

[0075] Figure 2FIG. 1 is a schematic diagram of a planar structure of a transparent display substrate. Figure 2 As shown, in an exemplary embodiment, the display substrate may include a plurality of regularly arranged repeating units 100. The repeating unit 100 is the basic unit constituting the display substrate. The display substrate is formed by repeating and continuously arranging the repeating unit 100 along at least one direction. That is, the display substrate is composed of a plurality of repeating units. In an exemplary embodiment, at least one repeating unit 100 may include a display unit 110 and a light-transmitting unit 120. The display unit 110 may include a plurality of sub-pixels. At least one sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit. The light-emitting unit may include at least a light-emitting device. The light-emitting device of the light-emitting unit is connected to the pixel driving circuit of the corresponding circuit unit. The display unit 110 is configured to display an image. The light-transmitting unit 120 may be located on at least one side of the display unit 110 in the repeating unit 100. The light-transmitting unit 120 is configured to transmit light, so that the repeating unit 100 can display an image in a transparent state, that is, transparent display.

[0076] An exemplary embodiment of the present disclosure provides a display substrate, comprising a plurality of repeating units, at least one of which comprises a display unit and a light-transmitting unit located on at least one side of the display unit, the display unit being configured to display an image, and the light-transmitting unit being configured to transmit light; the display unit comprising a plurality of sub-pixels, at least one of which comprises a pixel driving circuit and a compensation signal line, the compensation signal line being configured to provide a compensation signal to the pixel driving circuit; in a direction perpendicular to the display substrate, the display substrate comprises a plurality of conductive layers arranged on a base, a compensation block and the compensation signal line being provided in one conductive layer, the compensation block being connected to the compensation signal line, an electrode block being provided in at least another conductive layer, the orthographic projection of the compensation block on the base being at least partially overlapped with the orthographic projection of the electrode block on the base, and the compensation block and the electrode block forming a parasitic capacitor.

[0077] In an exemplary embodiment, the pixel driving circuit includes at least a first transistor, a gate electrode of the first transistor is connected to a first scanning signal line, and a first electrode of the first transistor is connected to a data signal line; the first scanning signal line is in the shape of a straight line or a broken line extending along a first direction, and the compensation signal line is in the shape of a straight line or a broken line extending along a second direction, and the first direction and the second direction intersect; in at least one repeating unit, a first electrode block is provided on the first scanning signal line, and the first electrode block and the first scanning signal line are an integrated structure connected to each other; a first compensation block is provided on the compensation signal line, and the first compensation block and the compensation signal line are an integrated structure connected to each other, and the orthographic projection of the first compensation block on the substrate at least partially overlaps with the orthographic projection of the first electrode block on the substrate, and the first compensation block and the first electrode block form a first parasitic capacitor.

[0078] In an exemplary embodiment, the plurality of sub-pixels include a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel, the second sub-pixel being arranged on one side of the first sub-pixel in a first direction, the fourth sub-pixel being arranged on one side of the third sub-pixel in the first direction, the third sub-pixel being arranged on one side of the first sub-pixel in a second direction, and the fourth sub-pixel being arranged on one side of the second sub-pixel in the second direction; the first scan signal line being connected to the gate electrode of the first transistor in the third sub-pixel and the gate electrode of the first transistor in the fourth sub-pixel; and at least one repeating unit further comprising a first scan auxiliary line and a first scan connection line, the first scan auxiliary line being connected to the gate electrode of the first transistor in the third sub-pixel and the gate electrode of the first transistor in the fourth sub-pixel. The first scanning auxiliary line is connected to the first scanning signal line through the first scanning connection line, and the first scanning auxiliary line is connected to the gate electrode of the first transistor in the first sub-pixel and the gate electrode of the first transistor in the second sub-pixel; a third electrode block is provided on the first scanning auxiliary line, and the third electrode block and the first scanning auxiliary line are an integrated structure connected to each other; a third compensation block is provided on the compensation signal line, and the third compensation block and the compensation signal line are an integrated structure connected to each other, the positive projection of the third compensation block on the substrate at least partially overlaps with the positive projection of the third electrode block on the substrate, and the third compensation block and the third electrode block form a third parasitic capacitor.

[0079] In an exemplary embodiment, the pixel driving circuit includes at least a third transistor, a gate electrode of the third transistor is connected to a second scanning signal line, and a first electrode of the third transistor is connected to the compensation signal line; the second scanning signal line is in the shape of a straight line or a broken line extending along a first direction, and the compensation signal line is in the shape of a straight line or a broken line extending along a second direction, and the first direction and the second direction intersect; in at least one repeating unit, a second electrode block is provided on the second scanning signal line, the second electrode block and the second scanning signal line are an integrated structure connected to each other, and a second compensation block is provided on the compensation signal line, the second compensation block and the compensation signal line are an integrated structure connected to each other, the orthographic projection of the second compensation block on the substrate at least partially overlaps with the orthographic projection of the second electrode block on the substrate, and the second compensation block and the second electrode block form a second parasitic capacitor.

[0080] In an exemplary embodiment, the plurality of sub-pixels include a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel, the second sub-pixel is arranged on one side of the first sub-pixel in a first direction, the fourth sub-pixel is arranged on one side of the third sub-pixel in the first direction, the third sub-pixel is arranged on one side of the first sub-pixel in a second direction, and the fourth sub-pixel is arranged on one side of the second sub-pixel in the second direction, and the first direction and the second direction intersect; the second scan signal line is connected to the gate electrode of the third transistor in the third sub-pixel and the gate electrode of the third transistor in the fourth sub-pixel; at least one repeating unit further includes a second scan auxiliary line and a second scan connection line, and the The second scanning auxiliary line is connected to the second scanning signal line through the second scanning connection line, and the second scanning auxiliary line is connected to the gate electrode of the third transistor in the first sub-pixel and the gate electrode of the third transistor in the second sub-pixel; a fourth electrode block is provided on the second scanning auxiliary line, and the fourth electrode block and the second scanning auxiliary line are an integrated structure connected to each other; a fourth compensation block is provided on the compensation signal line, and the fourth compensation block and the compensation signal line are an integrated structure connected to each other, and the orthographic projection of the fourth compensation block on the substrate at least partially overlaps with the orthographic projection of the fourth electrode block on the substrate, and the fourth compensation block and the fourth electrode block form a fourth parasitic capacitor.

[0081] In an exemplary embodiment, the pixel driving circuit further includes a second transistor, a gate electrode of the second transistor being connected to the second electrode of the first transistor, a first electrode of the second transistor being connected to the first power line via a power connection electrode, and a second electrode of the second transistor being connected to the second electrode of the third transistor; at least one repeating unit further includes a fifth electrode block, the fifth electrode block being arranged between the power connection electrodes of two adjacent sub-pixels and connected to the two power connection electrodes; at least one fifth compensation block is arranged on the compensation signal line, an orthographic projection of the fifth compensation block on the display substrate plane at least partially overlaps with an orthographic projection of the fifth electrode block on the display substrate plane, and the fifth compensation block and the fifth electrode block form a fifth parasitic capacitor.

[0082] The display substrate of the present disclosure is described below by way of some exemplary embodiments.

[0083] In an exemplary embodiment, the display substrate may include a plurality of regularly arranged repeating units parallel to the display substrate, at least one of which may include a display unit and a light-transmitting unit. The display unit is configured to display an image, and the light-transmitting unit is configured to transmit light, thereby achieving a transparent display. In a direction perpendicular to the display substrate, the display substrate may include at least a driving circuit layer disposed on a base and a light-emitting structure layer disposed on a side of the driving circuit layer away from the base. In at least one of the repeating units, the driving circuit layer of the display unit may include a plurality of circuit units, and the light-emitting structure layer of the display unit may include a plurality of light-emitting units. The circuit units may include at least pixel driving circuits, and the light-emitting units may include at least light-emitting devices, which are connected to the pixel driving circuits of corresponding circuit units.

[0084] In exemplary embodiments, the circuit unit referred to in this disclosure refers to a region divided according to the pixel driving circuit, and the light-emitting unit referred to in this disclosure refers to a region divided according to the light-emitting device. In exemplary embodiments, the position of the orthographic projection of the light-emitting unit on the substrate may correspond to the position of the orthographic projection of the circuit unit on the substrate, or the position of the orthographic projection of the light-emitting unit on the substrate may not correspond to the position of the orthographic projection of the circuit unit on the substrate.

[0085] In the exemplary embodiment of the present disclosure, the position of the circuit unit's orthographic projection on the substrate and the position of the light-emitting unit's orthographic projection on the substrate can basically correspond one to one. The circuit unit and the light-emitting unit constitute a sub-pixel. Therefore, in the following content, sub-pixels are uniformly used to refer to the circuit unit and the light-emitting unit.

[0086] Figure 3 FIG. 1 is a schematic diagram of the arrangement of sub-pixels in a repeating unit according to an exemplary embodiment of the present disclosure. Figure 3As shown, at least one repeating unit may include a display unit 110 and a light-transmitting unit 120, and the display unit 110 may be located on one side of the light-transmitting unit 120 in the first direction X. In an exemplary embodiment, the display unit 110 may include four sub-pixels, namely a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4. The four sub-pixels may be arranged in a square to effectively increase the aperture ratio and the area of ​​the light-transmitting region.

[0087] In an exemplary embodiment, the second subpixel P2 may be disposed on one side of the first subpixel P1 in the first direction X, the fourth subpixel P4 may be disposed on one side of the third subpixel P3 in the first direction X, the third subpixel P3 may be disposed on one side of the first subpixel P1 in the second direction Y, and the fourth subpixel P4 may be disposed on one side of the second subpixel P2 in the second direction Y. A plurality of subpixels sequentially disposed along the first direction X may be referred to as a pixel row, and a plurality of subpixels sequentially disposed along the second direction Y may be referred to as a pixel column. The first direction X intersects the second direction Y.

[0088] In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) that emits red light, the second subpixel P2 may be a blue subpixel (B) that emits blue light, the third subpixel P3 may be a white subpixel (W) that emits white light, and the fourth subpixel P4 may be a green subpixel (G) that emits green light. In some possible embodiments, the arrangement of the RBWGs may be adjusted according to actual needs and is not specifically limited in this disclosure.

[0089] In an exemplary embodiment, each sub-pixel may include a circuit unit and a light-emitting unit arranged on a side of the circuit unit away from the substrate, the circuit unit may include at least a pixel driving circuit, the light-emitting unit may include at least a light-emitting device, and the light-emitting device of the light-emitting unit is connected to the pixel driving circuit of the corresponding circuit unit.

[0090] Figure 4 FIG. 1 is an equivalent circuit diagram of a pixel driving circuit in a display unit according to an exemplary embodiment of the present disclosure. Figure 4 As shown, at least one display unit may include four pixel driving circuits, the four pixel driving circuits may be arranged in a square manner, and the pixel driving circuit may be a 3T1C structure.

[0091] In an exemplary embodiment, at least one pixel driving circuit may include three transistors (a first transistor T1, a second transistor T2, and a third transistor T3) and a storage capacitor C, and the pixel driving circuit is respectively connected to the first scanning signal line 31, the second scanning signal line 32, the first power line 61, the data signal line 63, and the compensation signal line 64.

[0092] In an exemplary embodiment, the pixel driving circuit may include a first node N1 and a second node N2. The first node N1 is connected to the second electrode of the first transistor T1, the gate electrode of the second transistor T2, and the first end of the storage capacitor C, respectively. The second node N2 is connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the second end of the storage capacitor C, respectively.

[0093] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first node N1 , a second end of the storage capacitor C is connected to the second node N2 , and the storage capacitor C is used to store the potential of the gate electrode of the second transistor T2 .

[0094] In an exemplary embodiment, the first transistor T1 may function as a data writing transistor, a gate electrode of the first transistor T1 being connected to the first scan signal line 31 , a first electrode of the first transistor T1 being connected to the data signal line 63 , and a second electrode of the first transistor T1 being connected to the first node N1 .

[0095] In an exemplary embodiment, the second transistor T2 may function as a driving transistor, a gate electrode of the second transistor T2 is connected to the first node N1 , a first electrode of the second transistor T2 is connected to the first power line 61 , and a second electrode of the second transistor T2 is connected to the second node N2 .

[0096] In an exemplary embodiment, the third transistor T3 may serve as a compensation transistor, a gate electrode of the third transistor T3 is connected to the second scan signal line 32 , a first electrode of the third transistor T3 is connected to the compensation signal line 64 , and a second electrode of the third transistor T3 is connected to the second node N2 .

[0097] In an exemplary embodiment, in two pixel driving circuits of at least one pixel row, gate electrodes of two first transistors T1 are connected to the same first scan signal line 31 , and gate electrodes of two third transistors T3 are connected to the same second scan signal line 32 .

[0098] In an exemplary embodiment, in the four pixel driving circuits of at least one repeating unit, the gate electrodes of the four first transistors T1 are connected to the same first scan signal line 31 , and the gate electrodes of the four third transistors T3 are connected to the same second scan signal line 32 .

[0099] In an exemplary embodiment, the light-emitting device EL may be an OLED, including a stacked first electrode, an organic light-emitting layer, and a second electrode, or a QLED, including a stacked first electrode, a quantum dot light-emitting layer, and a second electrode. The first electrode of the light-emitting device EL is connected to the second node N2, and the second electrode of the light-emitting device EL is connected to the second power line 62. The light-emitting device EL emits light of a corresponding brightness in response to the current of the second transistor T2. In an exemplary embodiment, the first electrode may be an anode, and the second electrode may be a cathode; alternatively, the first electrode may be a cathode, and the second electrode may be an anode.

[0100] In an exemplary embodiment, the signal of the first power line 61 is a continuously provided high-level signal, and the signal of the second power line 62 is a continuously provided low-level signal.

[0101] In an exemplary embodiment, the first to third transistors T1 to T3 may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first to third transistors T1 to T3 may include P-type transistors and N-type transistors.

[0102] In an exemplary embodiment, the first transistor T1 to the third transistor T3 may be low-temperature polysilicon thin-film transistors, or oxide thin-film transistors, or both. The active layer of the low-temperature polysilicon thin-film transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor is made of oxide semiconductor (Oxide). Low-temperature polysilicon thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display substrate, i.e., an LTPS+Oxide (LTPO) display substrate, can leverage the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0103] Figure 5 FIG. 1 is a schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure, illustrating a structure of a repeating unit. Figure 5As shown, the display substrate may include a plurality of regularly arranged repeating units, at least one of which may include a display unit 110 and a light-transmitting unit 120 located on at least one side of the display unit 110. The display unit 110 is configured to display an image, and the light-transmitting unit 120 is configured to transmit light. The display unit 110 may include a first subpixel P1, a second subpixel P2, a third subpixel P3, and a fourth subpixel P4 arranged in a square. The second subpixel P2 may be located on one side of the first subpixel P1 in the first direction X, the fourth subpixel P4 may be located on one side of the third subpixel P3 in the first direction X, the third subpixel P3 may be located on one side of the first subpixel P1 in the second direction Y, and the fourth subpixel P4 may be located on one side of the second subpixel P2 in the second direction Y. At least one subpixel may include a pixel driving circuit and a light-emitting device. The light-emitting device is connected to the pixel driving circuit and is configured to emit light of corresponding brightness in response to a current output by the pixel driving circuit.

[0104] In an exemplary embodiment, in at least one sub-pixel, the pixel driving circuit may be connected to the first scan signal line 31, the second scan signal line 32, the first power line 61, the data signal line 63, and the compensation signal line 64, respectively, and the light-emitting device is connected to the second power line 62. The first scan signal line 31 and the second scan signal line 32 are configured to provide the first scan signal and the second scan signal, respectively, to the pixel driving circuit, the first power line 61 is configured to provide the first power signal to the pixel driving circuit, the data signal line 63 is configured to provide the data signal to the pixel driving circuit, the compensation signal line 64 is configured to provide the compensation signal to the pixel driving circuit, and the second power line 62 is configured to provide the second power signal to the light-emitting device.

[0105] In an exemplary embodiment, at least one repeating unit may include a first scan signal line 31, a second scan signal line 32, a first power line 61, a second power line 62, a compensation signal line 64 and four data signal lines 63. The shapes of the first scan signal line 31 and the second scan signal line 32 can be straight lines or broken lines with the main parts extending along the first direction X. The shapes of the first power line 61, the second power line 62, the data signal line 63 and the compensation signal line 64 can be straight lines or broken lines with the main parts extending along the second direction Y.

[0106] In an exemplary embodiment, in at least one repeating unit, the first scanning signal line 31 may define a first pixel row including a first sub-pixel P1 and a second sub-pixel P2, the second scanning signal line 32 may define a second pixel row including a third sub-pixel P3 and a fourth sub-pixel P4, the first power line 61 and the compensation signal line 64 may define a first pixel column including the first sub-pixel P1 and the third sub-pixel P3, and the second power line 62 and the compensation signal line 64 may define a second pixel column including the second sub-pixel P2 and the fourth sub-pixel P4.

[0107] In an exemplary embodiment, in at least one repeating unit, the first power line 61, the two data signal lines 63, the compensation signal line 64, the two data signal lines 63, and the second power line 62 may be sequentially arranged along the first direction X. The first power line 61 may be located on one side of the display unit 110 in the opposite direction of the first direction X, the second power line 62 may be located on one side of the display unit 110 in the first direction X, the compensation signal line 64 may be located between the first power line 61 and the second power line 62, two of the four data signal lines 63 may be located between the first power line 61 and the compensation signal line 64, and the other two of the four data signal lines 63 may be located between the second power line 62 and the compensation signal line 64, that is, the compensation signal line 64 may be located between two adjacent data signal lines 63.

[0108] In an exemplary embodiment, in at least one repeating unit, the orthographic projection of the compensation signal line 64 on the plane of the display substrate at least partially overlaps with the orthographic projection of the vertical reference line on the plane of the display substrate, the positions of the first power line 61 and the second power line 62 can be substantially mirror-symmetrical with respect to the compensation signal line 64, and the positions of the two data signal lines 63 located on the opposite side of the first direction X of the compensation signal line 64 and the two data signal lines 63 located on the side of the compensation signal line 64 in the first direction X can be substantially mirror-symmetrical with respect to the compensation signal line 64.

[0109] In an exemplary embodiment, in at least one sub-pixel, the pixel driving circuit may include at least a storage capacitor, a first transistor T1 as a data writing transistor, a second transistor T2 as a driving transistor, and a third transistor T3 as a compensation transistor.

[0110] In an exemplary embodiment, in at least one sub-pixel, the storage capacitor may include at least a first plate 11, a second plate 12, and a third plate 13. The orthographic projection of the second plate 12 on the display substrate plane at least partially overlaps with the orthographic projection of the first plate 11 on the display substrate plane. The first plate 11 and the second plate 12 form a first sub-capacitor. The orthographic projection of the third plate 13 on the display substrate plane at least partially overlaps with the orthographic projection of the second plate 12 on the display substrate plane. The third plate 13 and the second plate 12 form a second sub-capacitor. The first sub-capacitor and the second sub-capacitor connected in parallel constitute the storage capacitor of the pixel driving circuit.

[0111] In an exemplary embodiment, in at least one sub-pixel, a first electrode of the first transistor T1 is connected to the data signal line 63, a second electrode of the first transistor T1 is connected to the second electrode plate 12 and the gate electrode of the second transistor T2, a first electrode of the second transistor T2 is connected to the first power line 61, a second electrode of the second transistor T2 is connected to the second electrode of the third transistor T3, and a first electrode of the third transistor T3 is connected to the compensation signal line 64.

[0112] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may include at least a plurality of conductive layers arranged on a base, a compensation block is provided in one conductive layer, the compensation block is connected to the compensation signal line, and an electrode block is provided in another conductive layer, the orthographic projection of the compensation block on the substrate at least partially overlaps with the orthographic projection of the electrode block on the substrate, and the compensation block and the electrode block form a parasitic capacitance that increases the load and anti-interference capability of the compensation signal line.

[0113] In an exemplary embodiment, at least one repeating unit may be provided with any one or more of the following electrode blocks: a first electrode block 81 , a second electrode block 82 , a third electrode block 83 , a fourth electrode block 84 and a fifth electrode block 85 .

[0114] In an exemplary embodiment, in at least one repeating unit, any one or more of the following compensation blocks may be provided on the compensation signal line 64 : a first compensation block 91 , a second compensation block 92 , a third compensation block 93 , a fourth compensation block 94 , and a fifth compensation block 95 .

[0115] In an exemplary embodiment, in at least one repeating unit, any one or more of the following parasitic capacitors may be formed: a first parasitic capacitor formed by the first electrode block 81 and the first compensation block 91, a second parasitic capacitor formed by the second electrode block 82 and the second compensation block 92, a third parasitic capacitor formed by the third electrode block 83 and the third compensation block 93, a fourth parasitic capacitor formed by the fourth electrode block 84 and the fourth compensation block 94, and a fifth parasitic capacitor formed by the fifth electrode block 85 and the fifth compensation block 95.

[0116] In an exemplary embodiment, the compensation signal line 64 and the first compensation block 91 , the second compensation block 92 , the third compensation block 93 , the fourth compensation block 94 , and the fifth compensation block 95 may be disposed on the same layer and are interconnected as an integral structure.

[0117] In an exemplary embodiment, in at least one repeating unit, a first electrode block 81 may be provided on the first scanning signal line 31, the first scanning signal line 31 and the first electrode block 81 may be an integral structure connected to each other, the orthographic projection of the first compensation block 91 on the substrate at least partially overlaps with the orthographic projection of the first electrode block 81 on the substrate, and the first compensation block 91 and the first electrode block 81 form a first parasitic capacitor.

[0118] In an exemplary embodiment, in at least one repetition unit, a distance between the compensation signal line 64 and an adjacent data signal line 63 is greater than a distance between the first compensation block 91 and an adjacent data signal line 63 .

[0119] In an exemplary embodiment, at least one repeating unit further includes a first scan auxiliary line 33 and a first scan connection line 35. The first scan auxiliary line 33 is connected to the first scan signal line 31 via the first scan connection line 35. The first scan signal line 31 is connected to the gate electrodes of the first transistor T1 in the third subpixel P3 and the fourth subpixel P4, and the first scan auxiliary line 33 is connected to the gate electrodes of the first transistor T1 in the first subpixel P1 and the second subpixel P2. A third electrode block 83 is disposed on the first scan auxiliary line 33. The orthographic projection of the third compensation block 93 on the substrate at least partially overlaps with the orthographic projection of the third electrode block 83 on the substrate. The third compensation block 93 and the third electrode block 83 form a third parasitic capacitor.

[0120] In an exemplary embodiment, in at least one repetition unit, a spacing between the compensation signal line 64 and an adjacent data signal line 63 is greater than a spacing between the third compensation block 93 and an adjacent data signal line 63 .

[0121] In an exemplary embodiment, the first scan signal line 31 and the first scan auxiliary line 33 may be disposed in the same one conductive layer, and the first scan connection line 35 may be disposed in another conductive layer.

[0122] In an exemplary embodiment, in at least one repeating unit, a second electrode block 82 may be provided on the second scanning signal line 32, the second scanning signal line 32 and the second electrode block 82 may be an integral structure connected to each other, the orthographic projection of the second compensation block 92 on the substrate at least partially overlaps with the orthographic projection of the second electrode block 82 on the substrate, and the second compensation block 92 and the second electrode block 82 form a second parasitic capacitor.

[0123] In an exemplary embodiment, in at least one repetition unit, a distance between the compensation signal line 64 and an adjacent data signal line 63 is greater than a distance between the second compensation block 92 and an adjacent data signal line 63 .

[0124] In an exemplary embodiment, at least one repeating unit further includes a second scan auxiliary line 34 and a second scan connection line 36. The second scan auxiliary line 34 is connected to the second scan signal line 32 via the second scan connection line 36. The second scan signal line 32 is connected to the gate electrodes of the third transistor T3 in the third subpixel P3 and the fourth subpixel P4, and the second scan auxiliary line 34 is connected to the gate electrodes of the third transistor T3 in the first subpixel P1 and the second subpixel P2. A fourth electrode block 84 is disposed on the second scan auxiliary line 34. The orthographic projection of the fourth compensation block 94 on the substrate at least partially overlaps with the orthographic projection of the fourth electrode block 84 on the substrate. The fourth compensation block 94 and the fourth electrode block 84 form a fourth parasitic capacitor.

[0125] In an exemplary embodiment, in at least one repetition unit, a distance between the compensation signal line 64 and an adjacent data signal line 63 is greater than a distance between the fourth compensation block 94 and an adjacent data signal line 63 .

[0126] In an exemplary embodiment, the second scan signal line 32 , the second scan auxiliary line 34 , and the second scan connection line 36 may be disposed in the same conductive layer and be an integrated structure connected to each other.

[0127] In an exemplary embodiment, in at least one sub-pixel, the first electrode of the second transistor T2 is connected to the first power line 61 via at least the power connection electrode 25. At least one repeating unit may further include a fifth electrode block 85. The fifth electrode block 85 may be disposed between the power connection electrodes 25 of two adjacent sub-pixels and connected to both power connection electrodes 25. The orthographic projection of the fifth compensation block 95 on the substrate at least partially overlaps with the orthographic projection of the fifth electrode block 85 on the substrate. The fifth compensation block 95 and the fifth electrode block 85 form a fifth parasitic capacitor.

[0128] In an exemplary embodiment, in at least one repetition unit, a distance between the compensation signal line 64 and an adjacent data signal line 63 is greater than a distance between the fifth electrode block 85 and an adjacent data signal line 63 .

[0129] In an exemplary embodiment, the pixel driving circuits in the first subpixel P1 and the third subpixel P3 may be substantially mirror-symmetrical with respect to a horizontal reference line, the pixel driving circuits in the second subpixel P2 and the fourth subpixel P4 may be substantially mirror-symmetrical with respect to the horizontal reference line, the pixel driving circuits in the first subpixel P1 and the second subpixel P2 may be substantially mirror-symmetrical with respect to a vertical reference line, and the pixel driving circuits in the third subpixel P3 and the fourth subpixel P4 may be substantially mirror-symmetrical with respect to the vertical reference line. The horizontal reference line may be a straight line that bisects the display unit in the second direction Y and extends along the first direction X, and the vertical reference line may be a straight line that bisects the display unit in the first direction X and extends along the second direction Y.

[0130] In an exemplary embodiment, the multiple conductive layers of the display substrate may include at least a first conductive layer arranged on the substrate, a second conductive layer arranged on a side of the first conductive layer away from the substrate, and a third conductive layer arranged on a side of the second conductive layer away from the substrate. The first electrode 11 may be arranged in the first conductive layer, the second electrode 12, the first scanning signal line 31 and the second scanning signal line 32 may be arranged in the second conductive layer, and the third electrode 13, the first power line 61, the second power line 62, the data signal line 63 and the compensation signal line 64 may be arranged in the third conductive layer.

[0131] The following is an illustrative explanation of the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as depositing a film layer, coating a photoresist, mask exposure, development, etching, and stripping the photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating an organic material, mask exposure, and development for organic materials. Deposition can be achieved by any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be achieved by any one or more of spraying, spin coating, and inkjet printing; and etching can be achieved by any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a thin film made by depositing, coating, or other processes on a substrate using a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer." If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0132] In an exemplary embodiment, taking four sub-pixels (first sub-pixel P1, second sub-pixel P2, third sub-pixel P3 and fourth sub-pixel P4) of a repeating unit as an example, the preparation process of the display substrate of the exemplary embodiment of the present disclosure may include the following operations.

[0133] (1) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern includes: depositing a first conductive film on a substrate, patterning the first conductive film through a patterning process, and forming the first conductive layer pattern on the substrate, such as Figure 6 In an exemplary embodiment, the first conductive layer may be referred to as a light shielding layer (SHL).

[0134] In an exemplary embodiment, the first conductive layer of each sub-pixel in the display substrate may include at least a first electrode plate 11 and a board-level connection electrode 14 .

[0135] In an exemplary embodiment, the first electrode plate 11 may be in a block shape (e.g., a rectangle), and the corners of the block shape may be chamfered, protruded, or recessed, and may be provided in each sub-pixel of the display unit 110. The first electrode plate 11 may serve as the lower electrode plate (the second end of the storage capacitor) of the storage capacitor, and the first electrode plate 11 is configured to form a first sub-capacitor of the storage capacitor with the subsequently formed second electrode plate.

[0136] In an exemplary embodiment, the first electrode plate 11 is further configured to shield the second transistor from light, reduce the intensity of light irradiating the second transistor, reduce leakage current of the second transistor, and thereby reduce the effect of light on the characteristics of the second transistor.

[0137] In an exemplary embodiment, the board-level connection electrode 14 may be in the shape of a strip extending along the first direction X, and may be provided across the display unit 110 and the light-transmitting unit 120. A first end of the board-level connection electrode 14 is connected to the first electrode plate 11, and a second end of the board-level connection electrode 14 extends to the light-transmitting unit 120 along the first direction X or a direction opposite to the first direction X. The board-level connection electrode 14 is configured to be connected to a subsequently formed anode connection electrode.

[0138] In an exemplary embodiment, in at least one sub-pixel, the first electrode plate 11 and the panel-level connection electrode 14 may be an integrated structure connected to each other.

[0139] In an exemplary embodiment, in at least one repeating unit, the first conductive layer may further include a compensation connection line 44. The compensation connection line 44 may be in the shape of a strip extending along the first direction X and may be disposed in the central region of the display unit 110. In the first direction X, the compensation connection line 44 may span the first pixel column and the second pixel column, and in the second direction Y, the compensation connection line 44 may span the first pixel row and the second pixel row. In an exemplary embodiment, the compensation connection line 44 is configured to connect to a fourth connection electrode and a compensation signal line, respectively, which are subsequently formed.

[0140] In an exemplary embodiment, the positions and shapes of the first conductive layers in the first subpixel P1 and the third subpixel P3 may be substantially mirror-symmetrical with respect to a horizontal reference line, the positions and shapes of the first conductive layers in the second subpixel P2 and the fourth subpixel P4 may be substantially mirror-symmetrical with respect to the horizontal reference line, the positions and shapes of the first conductive layers in the first subpixel P1 and the second subpixel P2 may be substantially mirror-symmetrical with respect to a vertical reference line, and the positions and shapes of the first conductive layers in the third subpixel P3 and the fourth subpixel P4 may be substantially mirror-symmetrical with respect to the vertical reference line. The horizontal reference line may be a straight line that bisects the display unit in the second direction Y and extends along the first direction X, and the vertical reference line may be a straight line that bisects the display unit in the first direction X and extends along the second direction Y.

[0141] (2) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: depositing a first insulating film and a semiconductor film in sequence on the substrate on which the aforementioned pattern is formed, patterning the semiconductor film through a patterning process to form a first insulating layer covering the first conductive layer, and a semiconductor layer disposed on the first insulating layer, such as Figure 7A and Figure 7B As shown, Figure 7B for Figure 7A Schematic diagram of the semiconductor layer.

[0142] In an exemplary embodiment, the semiconductor layer of each sub-pixel in the display substrate may include at least a first active layer 21, a second active layer 22, and a third active layer 23. The first active layer 21 may serve as an active layer of the first transistor T1, the second active layer 22 may serve as an active layer of the second transistor T2, and the third active layer 23 may serve as an active layer of the third transistor T3.

[0143] In an exemplary embodiment, for the first subpixel P1 and the second subpixel P2, the first active layer 21 and the third active layer 23 can be disposed on one side of the first electrode plate 11 of the subpixel in the second direction Y, and the second active layer 22 can be disposed in an end region of the first electrode plate 11 of the subpixel away from the first active layer 21 and the third active layer 23. The orthographic projection of the second active layer 22 on the substrate is within the range of the orthographic projection of the first electrode plate 11 of the subpixel on the substrate. This allows the first electrode plate 11, acting as a shielding layer, to shield the channel region of the second transistor T2, preventing light from affecting the channel and ensuring the electrical performance of the second transistor T2. The third active layer 23 of the first subpixel P1 can be disposed on one side of the first active layer 21 of the subpixel in the first direction X, and the third active layer 23 of the second subpixel P2 can be disposed on a side of the first active layer 21 of the subpixel opposite to the first direction X.

[0144] In an exemplary embodiment, for the third subpixel P3 and the fourth subpixel P4, the first active layer 21 and the third active layer 23 can be disposed on the side of the first electrode plate 11 of the subpixel opposite to the second direction Y, and the second active layer 22 can be disposed in the end region of the first electrode plate 11 of the subpixel away from the first active layer 21 and the third active layer 23. The orthographic projection of the second active layer 22 on the substrate is within the orthographic projection of the first electrode plate 11 of the subpixel on the substrate. This allows the first electrode plate 11, acting as a shielding layer, to shield the channel region of the second transistor T2, preventing light from affecting the channel and ensuring the electrical performance of the second transistor T2. The third active layer 23 of the third subpixel P3 can be disposed on the side of the first active layer 21 of the subpixel opposite to the first direction X, and the third active layer 23 of the fourth subpixel P4 can be disposed on the side of the first active layer 21 of the subpixel in the first direction X.

[0145] In an exemplary embodiment, the third active layer 23 of the first subpixel P1 and the third active layer 23 of the third subpixel P3 may be interconnected as a single unitary structure, and the third active layer 23 of the second subpixel P2 and the third active layer 23 of the fourth subpixel P4 may be interconnected as a single unitary structure. That is, the third active layers 23 of two adjacent subpixels in a pixel column are interconnected as a single unitary structure. By providing a shared first electrode for the second transistors of two adjacent subpixels in a pixel column, the present disclosure not only saves space but also reduces the number of via connection structures, simplifying the manufacturing process.

[0146] In an exemplary embodiment, the first active layer 21 and the third active layer 23 may be in the shape of strips extending along the second direction Y, and the second active layer 22 may be in the shape of a block (e.g., a rectangle). The corners of the block may be chamfered, protruded, or recessed. For example, the second active layer 22 in the first subpixel P1 and the third subpixel P3 may be in the shape of an "H," the second active layer 22 in the second subpixel P2 may be in the shape of a "C" (concave), and the second active layer 22 in the fourth subpixel P4 may be in the shape of an inverted "C" (concave).

[0147] In an exemplary embodiment, in at least one subpixel, the orthographic projections of the first active layer 21 and the third active layer 23 on the substrate do not overlap with the orthographic projection of the first electrode plate 11 on the substrate. By providing a non-overlapping region between the first active layer 21 and the first electrode plate 11, and between the third active layer 23 and the first electrode plate 11, the present disclosure facilitates designing the channel width-to-length ratios of the first transistor T1 and the third transistor T3 according to relevant requirements.

[0148] In example embodiments, the active layer of each transistor may include a first region, a second region, and a channel region between the first region and the second region.

[0149] In an exemplary embodiment, the positions of the semiconductor layers in the first and second subpixels P1 and P2 may be substantially mirror-symmetrical with respect to a vertical reference line, and the positions of the semiconductor layers in the third and fourth subpixels P3 and P4 may be substantially mirror-symmetrical with respect to the vertical reference line.

[0150] In exemplary embodiments, the semiconductor layer may be formed of a metal oxide, such as an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon, indium, and tin, an oxide containing indium, gallium, and zinc, etc. The semiconductor layer may be a single layer, a double layer, or a multilayer.

[0151] (3) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: depositing a second conductive film on the substrate having the aforementioned pattern formed thereon, patterning the second conductive film through a patterning process, and forming the second conductive layer pattern on the second insulating layer, such as Figure 8A and Figure 8B As shown, Figure 8B for Figure 8A In an exemplary embodiment, the second conductive layer may be referred to as a gate metal layer (GATE).

[0152] In an exemplary embodiment, the second conductive layer of each sub-pixel in the display substrate may include at least a second electrode 12 , a second gate electrode 24 , and a power connection electrode 25 .

[0153] In an exemplary embodiment, the shape of the second electrode plate 12 can be a block (such as a rectangle), and the corners of the rectangle can be provided with chamfers, protrusions or grooves. It can be provided in the display unit 110 of each sub-pixel. The orthographic projection of the second electrode plate 12 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 11 on the substrate. The second electrode plate 12 can serve as the middle electrode plate of the storage capacitor (the first end of the storage capacitor), and the first electrode plate 11 and the second electrode plate 12 form the first sub-capacitor of the storage capacitor in the pixel driving circuit.

[0154] In an exemplary embodiment, the second gate electrode 24 may be in the shape of a strip extending along the second direction Y, and may be located on a side of the second electrode plate 12 close to the second active layer 22. A first end of the second gate electrode 24 is connected to the second electrode plate 12 of the sub-pixel, and a second end of the second gate electrode 24 extends in a direction close to the second active layer 22. The orthographic projection of the second gate electrode 24 on the substrate at least partially overlaps with the orthographic projection of the second active layer 22 on the substrate. The second gate electrode 24 may serve as the gate electrode of the second transistor T2 and may control the conduction or disconnection of the second transistor T2.

[0155] In an exemplary embodiment, the second plate 12 and the second gate electrode 24 in each sub-pixel may be an integral structure connected to each other.

[0156] In an exemplary embodiment, the power connection electrode 25 may be in the shape of a block (e.g., a rectangle) or an annular shape and may be disposed on a side of the second gate electrode 24 away from the second electrode plate 12. The power connection electrode 25 is configured to connect to a subsequently formed fifth connection electrode. By providing the power connection electrode with an annular structure, the present disclosure can reduce the overlap area between the power connection electrode and a subsequently formed data signal line, thereby reducing the parasitic capacitance of the data signal line.

[0157] In an exemplary embodiment, a fifth electrode block 85 may be provided between the power connection electrode 25 in the first subpixel P1 and the power connection electrode 25 in the second subpixel P2, and the power connection electrodes 25 of the two subpixels are connected to each other via the fifth electrode block 85. A fifth electrode block 85 may be provided between the power connection electrode 25 in the third subpixel P3 and the power connection electrode 25 in the fourth subpixel P4, and the power connection electrodes 25 of the two subpixels are connected to each other via the fifth electrode block 85. The fifth electrode block 85 is configured to form a fifth parasitic capacitance with a compensation signal line formed subsequently to increase the parasitic capacitance of the compensation signal line.

[0158] In an exemplary embodiment, the power connection electrode 25 in the first subpixel P1, the power connection electrode 25 in the second subpixel P2, and the fifth electrode block 85 located between the two power connection electrodes 25 may be connected to each other as an integral structure. The power connection electrode 25 in the third subpixel P3, the power connection electrode 25 in the fourth subpixel P4, and the fifth electrode block 85 located between the two power connection electrodes 25 may be connected to each other as an integral structure.

[0159] In an exemplary embodiment, the second conductive layer in at least one repeating unit may further include a first scan signal line 31 , a second scan signal line 32 , a first scan auxiliary line 33 , a second scan auxiliary line 34 , and a second scan connection line 36 .

[0160] In an exemplary embodiment, the first scan signal line 31 may be in the shape of a straight line or a zigzag line extending along the first direction X. It may be continuously arranged in multiple repeating units, i.e., extending from the light-transmitting unit 120 of the current repeating unit to the display unit 110 of the current repeating unit, and from the display unit 110 of the current repeating unit to the light-transmitting unit 120 of the adjacent repeating unit. The region where the first scan signal line 31 overlaps with the first active layer in the third subpixel P3 and the fourth subpixel P4 may serve as the gate electrode of the first transistor T1. That is, the first scan signal line 31 is connected to the gate electrodes of the first transistor T1 in the third subpixel P3 and the fourth subpixel P4, so that the first scan signal line 31 can control the conduction or disconnection of the first transistor T1 in the third subpixel P3 and the fourth subpixel P4.

[0161] In an exemplary embodiment, a first scan connection ring 31-1 may be provided on the first scan signal line 31. The first scan connection ring 31-1 may be in a ring shape (e.g., a rectangular ring), may be provided in the third sub-pixel P3 and the fourth sub-pixel P4, and may be connected to the first scan signal line 31, respectively. The first scan connection ring 31-1 is configured to be connected to a first scan connection line formed subsequently, so that the first scan signal line 31 is connected to the first scan auxiliary line 33 via the first scan connection line.

[0162] In an exemplary embodiment, in at least one repeating unit, the first scan signal line 31 and the two first scan connection rings 31 - 1 may be an integrated structure connected to each other.

[0163] In an exemplary embodiment, in at least one repeating unit, a first electrode block 81 may be disposed on the first scan signal line 31. The first electrode block 81 may be block-shaped (e.g., rectangular). In the first direction X, the first electrode block 81 may be disposed at the interface between the first pixel column and the second pixel column and connected to the first scan signal line 31. The first electrode block 81 is configured to form a first parasitic capacitor with a subsequently formed first compensation block to increase the parasitic capacitance of the compensation signal line.

[0164] In an exemplary embodiment, the first scanning auxiliary line 33 may be in the shape of a straight line or a broken line extending along the first direction X, and may be provided in the display unit 110 of each repeating unit. The region where the first scanning auxiliary line 33 overlaps with the first active layer in the first sub-pixel P1 and the second sub-pixel P2 may serve as the gate electrode of the first transistor T1. That is, the first scanning auxiliary line 33 is connected to the gate electrode of the first transistor T1 in the first sub-pixel P1 and the second sub-pixel P2, so that the first scanning auxiliary line 33 can control the conduction or disconnection of the first transistor T1 in the first sub-pixel P1 and the second sub-pixel P2.

[0165] In an exemplary embodiment, a first auxiliary connection block 33-1 may be provided on the first scan auxiliary line 33. The first auxiliary connection block 33-1 may be in a block shape (e.g., a rectangle) and may be provided in the first sub-pixel P1 and the second sub-pixel P2, respectively, and connected to the first scan auxiliary line 33. The first auxiliary connection block 33-1 is configured to be connected to a first scan connection line formed later, so that the first scan auxiliary line 33 is connected to the first scan signal line 31 via the first scan connection line.

[0166] In an exemplary embodiment, in at least one repeating unit, the first scan auxiliary line 33 and the two first auxiliary connection blocks 33 - 1 may be an integral structure connected to each other.

[0167] In an exemplary embodiment, a third electrode block 83 may be disposed on the first scanning auxiliary line 33 in at least one repeating unit. The third electrode block 83 may be block-shaped (e.g., rectangular). In the first direction X, the third electrode block 83 may be disposed at the interface between the first pixel column and the second pixel column and connected to the first scanning auxiliary line 33. The third electrode block 83 is configured to form a third parasitic capacitor with a subsequently formed third compensation block to increase the parasitic capacitance of the compensation signal line.

[0168] In an exemplary embodiment, the second scan signal line 32 may be in the shape of a straight line or a zigzag line extending along the first direction X. It may be continuously arranged in multiple repeating units, i.e., extending from the light-transmitting unit 120 of the current repeating unit to the display unit 110 of the current repeating unit, and from the display unit 110 of the current repeating unit to the light-transmitting unit 120 of the adjacent repeating unit. The region where the second scan signal line 32 overlaps with the third active layer in the third subpixel P3 and the fourth subpixel P4 may serve as the gate electrode of the third transistor T3. That is, the second scan signal line 32 is connected to the gate electrode of the third transistor T3 in the third subpixel P3 and the fourth subpixel P4, so that the second scan signal line 32 can control the conduction or disconnection of the third transistor T3 in the third subpixel P3 and the fourth subpixel P4.

[0169] In an exemplary embodiment, in at least one repeating unit, a second electrode block 82 may be disposed on the second scan signal line 32. The second electrode block 82 may be block-shaped (e.g., rectangular). In the first direction X, the second electrode block 82 may be disposed at the interface between the first pixel column and the second pixel column and connected to the second scan signal line 32. The second electrode block 82 is configured to form a second parasitic capacitor with a subsequently formed second compensation block to increase the parasitic capacitance of the compensation signal line.

[0170] In an exemplary embodiment, the second scanning auxiliary line 34 may be in the shape of a straight line or a folded line extending along the first direction X. The main portion of the second scanning auxiliary line 34 may be disposed in the display unit 110 of each repeating unit, and both ends may be disposed in the light-transmitting unit 120. The region where the second scanning auxiliary line 34 overlaps with the third active layer in the first sub-pixel P1 and the second sub-pixel P2 may serve as the gate electrode of the third transistor T3. That is, the second scanning auxiliary line 34 is connected to the gate electrode of the third transistor T3 in the first sub-pixel P1 and the second sub-pixel P2, so that the second scanning auxiliary line 34 can control the conduction or disconnection of the third transistor T3 in the first sub-pixel P1 and the second sub-pixel P2.

[0171] In an exemplary embodiment, a fourth electrode block 84 may be disposed on the second scanning auxiliary line 34 in at least one repeating unit. The fourth electrode block 84 may be block-shaped (e.g., rectangular). In the first direction X, the fourth electrode block 84 may be disposed at the interface between the first pixel column and the second pixel column and connected to the second scanning auxiliary line 34. The fourth electrode block 84 is configured to form a fourth parasitic capacitor with a subsequently formed fourth compensation block to increase the parasitic capacitance of the compensation signal line.

[0172] In an exemplary embodiment, the second scan connection line 36 may be in the shape of a strip extending along the second direction Y and may be provided in the light-transmitting unit 120 of each repeating unit. Two second scan connection lines 36 may be provided in at least one repeating unit, one second scan connection line 36 may be connected to one end of the second scan signal line 32 and the second scan auxiliary line 34, and the other second scan connection line 36 may be connected to the other end of the second scan signal line 32 and the second scan auxiliary line 34, forming a ring-shaped second scan signal line structure.

[0173] In an exemplary embodiment, in at least one repeating unit, the second scan signal line 32 , the second scan auxiliary line 34 , and the two second scan connection lines 36 may be an integrated structure connected to each other.

[0174] In an exemplary embodiment, the second scan signal line 32 and the second scan auxiliary line 34 in the display unit 110 form a ring-shaped second scan signal line structure with the two second scan connection lines 36, so that the second scan signal line in the display unit 110 is a ring-shaped structure, and the second scan signal line in the light-transmitting unit 120 is a single-line structure.

[0175] In an exemplary embodiment, the ring-shaped second scanning signal line structure has a repair capability. When a short circuit occurs at a certain location on the second scanning signal line, the signal lines on both sides of the short circuit point can be cut off by laser cutting to repair the short circuit.

[0176] In an exemplary embodiment, the second conductive layer in at least one repeating unit may further include a first power auxiliary line 41 , a second power auxiliary line 42 , and a power connection bar 43 .

[0177] In an exemplary embodiment, the first auxiliary power supply line 41 may be in the form of a strip extending along the second direction Y. It may be disposed in each of the first subpixel P1 and the third subpixel P3, and located on a side of the second electrode plate 12 opposite to the first direction X. The first auxiliary power supply line 41 is configured to connect to a subsequently formed first power supply line. In an exemplary embodiment, there may be multiple first auxiliary power supply lines 41 in the first subpixel P1 and the third subpixel P3, and the multiple first auxiliary power supply lines 41 may be spaced apart along the second direction Y.

[0178] In an exemplary embodiment, the second auxiliary power supply line 42 may be in the shape of a strip extending along the second direction Y. It may be disposed in each of the second subpixel P2 and the fourth subpixel P4, and located on one side of the second electrode plate 12 in the first direction X. The second auxiliary power supply line 42 is configured to connect to a subsequently formed second power supply line. In an exemplary embodiment, there may be multiple second auxiliary power supply lines 42 in the second subpixel P2 and the fourth subpixel P4, and the multiple second auxiliary power supply lines 42 may be spaced apart along the second direction Y.

[0179] In an exemplary embodiment, the power connection bar 43 may be in the shape of a bar extending along the first direction X. It may be provided in each of the first subpixel P1 and the third subpixel P3, and may be located on a side of the second gate electrode 24 away from the second electrode plate 12. In the first subpixel P1, a first end of the power connection bar 43 is connected to the first auxiliary power line 41 in the first subpixel P1, and a second end of the power connection bar 43 extends along the first direction X and is connected to the power connection electrode 25 in the first subpixel P1. In the third subpixel P3, a first end of the power connection bar 43 is connected to the first auxiliary power line 41 in the third subpixel P3, and a second end of the power connection bar 43 extends along the first direction X and is connected to the power connection electrode 25 in the third subpixel P3.

[0180] In an exemplary embodiment, the power connection electrode 25, the power connection bar 43 and the at least one first power auxiliary line 41 in the first sub-pixel P1 can be an integrated structure connected to each other, and the power connection electrode 25, the power connection bar 43 and the at least one first power auxiliary line 41 in the third sub-pixel P3 can be an integrated structure connected to each other.

[0181] In an exemplary embodiment, the position and shape of the second conductive layer (excluding the power connection bar 43) in the first sub-pixel P1 and the second sub-pixel P2 can be substantially mirror-symmetrical with respect to the vertical reference line, and the position of the second conductive layer (excluding the power connection bar 43) in the third sub-pixel P3 and the fourth sub-pixel P4 can be substantially mirror-symmetrical with respect to the vertical reference line.

[0182] (4) Forming a third insulating layer pattern. In an exemplary embodiment, forming the third insulating layer pattern may include: depositing a third insulating film on the substrate on which the aforementioned pattern is formed, patterning the third insulating film through a patterning process to form a third insulating layer pattern covering the second conductive layer, wherein a plurality of via holes are provided on the third insulating layer, such as Figure 9 shown.

[0183] In an exemplary embodiment, the multiple via holes of each sub-pixel in the display substrate may include at least: a first via hole V1, a second via hole V2, a third via hole V3, a fourth via hole V4, a fifth via hole V5, a sixth via hole V6, a seventh via hole V7, an eighth via hole V8, a ninth via hole V9 and a tenth via hole V10.

[0184] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the first region of the first active layer on the substrate, the third insulating layer and the second insulating layer in the first via hole V1 are etched away to expose the surface of the first region of the first active layer, and the first via hole V1 is configured to connect a subsequently formed data signal line to the first region of the first active layer through the via hole.

[0185] In an exemplary embodiment, the orthographic projection of the second via hole V2 on the substrate is located within the range of the orthographic projection of the second region of the first active layer on the substrate, the third insulating layer and the second insulating layer in the second via hole V2 are etched away to expose the surface of the second region of the first active layer, and the second via hole V2 is configured to connect a subsequently formed first connecting electrode to the second region of the first active layer through the via hole.

[0186] In an exemplary embodiment, the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the first region of the second active layer on the substrate, the third insulating layer and the second insulating layer within the third via hole V3 are etched away to expose the surface of the first region of the second active layer, and the third via hole V3 is configured to connect a subsequently formed fifth connecting electrode to the first region of the second active layer through the via hole.

[0187] In an exemplary embodiment, the orthographic projection of the fourth via V4 on the substrate is located within the orthographic projection of the second region of the second active layer on the substrate. The third insulating layer and the second insulating layer within the fourth via V4 are etched away, exposing the surface of the second region of the second active layer. The fourth via V4 is configured to connect a subsequently formed second connection electrode to the second region of the second active layer through the via. In an exemplary embodiment, multiple fourth vias V4 may be provided to increase connection reliability.

[0188] In an exemplary embodiment, the orthographic projection of the fifth via hole V5 on the substrate lies within the orthographic projection of the first region of the third active layer on the substrate. The fifth via hole V5 is a transfer via hole, comprising a shallow half-hole and a deep half-hole. The third and second insulating layers within the shallow half-hole are etched away, exposing the surface of the first region of the third active layer. The third, second, and first insulating layers within the deep half-hole are etched away, exposing the surface of the compensation connection line 44. The fifth via hole V5 is configured to allow a subsequently formed fourth connection electrode to be simultaneously connected to the first region of the third active layer and the compensation connection line 44 through this via hole. In an exemplary embodiment, since the third active layers 23 of two adjacent sub-pixels in a pixel column form an interconnected, integrated structure, the two sub-pixels share the first region of the third active layer, and thus, the two sub-pixels share one fifth via hole V5.

[0189] In an exemplary embodiment, the orthographic projection of the sixth via hole V6 on the substrate is located within the range of the orthographic projection of the second region of the third active layer on the substrate, the third insulating layer and the second insulating layer within the sixth via hole V6 are etched away to expose the surface of the second region of the third active layer, and the sixth via hole V6 is configured to connect a subsequently formed third connecting electrode to the second region of the third active layer through the via hole.

[0190] In an exemplary embodiment, the orthographic projection of the seventh via V7 on the substrate is located within the range of the orthographic projection of the first electrode plate 11 on the substrate, and is arranged in the end area of ​​the first electrode plate 11 away from the second active layer 22. The third insulating layer, the second insulating layer and the first insulating layer in the seventh via V7 are etched away to expose the surface of the first electrode plate 11. The seventh via V7 is configured to connect the subsequently formed third electrode plate to the first electrode plate 11 through the via.

[0191] In an exemplary embodiment, the orthographic projection of the eighth via V8 on the substrate is located within the range of the orthographic projection of the second electrode plate 12 on the substrate, and is arranged in the end area of ​​the second electrode plate 12 away from the second active layer 22. The third insulating layer, the second insulating layer and the first insulating layer in the eighth via V8 are etched away to expose the surface of the second electrode plate 12. The eighth via V8 is configured to connect the subsequently formed first connecting electrode to the second electrode plate 12 through the via hole.

[0192] In an exemplary embodiment, the orthographic projection of the ninth via hole V9 on the substrate is located within the range of the orthographic projection of the power connection electrode 25 on the substrate, the third insulating layer in the ninth via hole V9 is etched away to expose the surface of the power connection electrode 25, and the ninth via hole V9 is configured to connect the subsequently formed fifth connection electrode to the power connection electrode 25 through the via hole.

[0193] In an exemplary embodiment, the tenth via hole V10 may be located at an end of the board-level connecting electrode 14 away from the first electrode plate 11. The orthographic projection of the tenth via hole V10 on the substrate is within the range of the orthographic projection of the board-level connecting electrode 14 on the substrate. The third insulating layer, the second insulating layer, and the first insulating layer within the tenth via hole V10 are etched away, exposing the surface of the board-level connecting electrode 14. The tenth via hole V10 is configured to connect a subsequently formed sixth connecting electrode to the board-level connecting electrode 14 through the via hole. In an exemplary embodiment, the tenth via hole V10 may be provided in the light-transmitting unit 120.

[0194] In an exemplary embodiment, the at least one repeating unit may further include at least two eleventh via holes V11 , at least two twelfth via holes V12 , a plurality of thirteenth via holes V13 , a plurality of fourteenth via holes V14 , and at least one fifteenth via hole V15 .

[0195] In an exemplary embodiment, two eleventh via holes V11 can be respectively arranged in the third sub-pixel P3 and the fourth sub-pixel P4, and the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the first scan connection ring 31-1 of the first scan signal line 31 on the substrate, and the third insulating layer in the eleventh via hole V11 is etched away to expose the surface of the first scan connection ring 31-1, and the eleventh via hole V11 is configured to connect the subsequently formed first scan connection line to the first scan connection ring 31-1 through the via hole.

[0196] In an exemplary embodiment, two twelfth via holes V12 can be respectively arranged in the first sub-pixel P1 and the second sub-pixel P2, and the orthographic projection of the twelfth via hole V12 on the substrate is located within the range of the orthographic projection of the first auxiliary connection block 33-1 of the first scanning auxiliary line 33 on the substrate. The third insulating layer in the twelfth via hole V12 is etched away to expose the surface of the first auxiliary connection block 33-1. The twelfth via hole V12 is configured to connect the subsequently formed first scanning connection line to the first auxiliary connection block 33-1 through the via hole.

[0197] In an exemplary embodiment, multiple thirteenth via holes V13 may be respectively provided in the first subpixel P1 and the third subpixel P3. The orthographic projection of the thirteenth via hole V13 on the substrate is located within the range of the orthographic projection of the first auxiliary power supply line 41 on the substrate. The third insulating layer within the thirteenth via hole V13 is etched away, exposing the surface of the first auxiliary power supply line 41. The thirteenth via hole V13 is configured to connect a subsequently formed first power supply line to the first auxiliary power supply line 41 through the via hole. In an exemplary embodiment, there may be multiple thirteenth via holes V13, and the multiple thirteenth via holes V13 may be arranged sequentially along the second direction Y to increase connection reliability.

[0198] In an exemplary embodiment, a plurality of fourteenth via holes V14 may be respectively disposed in the second subpixel P2 and the fourth subpixel P4. The orthographic projection of the fourteenth via hole V14 on the substrate is located within the range of the orthographic projection of the second auxiliary power supply line 42 on the substrate. The third insulating layer within the fourteenth via hole V14 is etched away, exposing the surface of the second auxiliary power supply line 42. The fourteenth via hole V14 is configured to connect a subsequently formed second power supply line to the second auxiliary power supply line 42 through the via hole. In an exemplary embodiment, there may be multiple fourteenth via holes V14, and the multiple fourteenth via holes V14 may be sequentially disposed along the second direction Y to increase connection reliability.

[0199] In an exemplary embodiment, the orthographic projection of the fifteenth via V15 on the substrate is located within the range of the orthographic projection of the compensation connection line 44 on the substrate, the third insulating layer, the second insulating layer and the first insulating layer in the fifteenth via V15 are etched away to expose the surface of the compensation connection line 44, and the fifteenth via V15 is configured to connect a subsequently formed compensation signal line to the compensation connection line 44 through the via.

[0200] (5) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern may include: depositing a third conductive film on the substrate on which the aforementioned pattern is formed, patterning the third conductive film through a patterning process, and forming the third conductive layer pattern on the third insulating layer, such as Figure 10A and Figure 10B As shown, Figure 10B for Figure 10A In an exemplary embodiment, the third conductive layer may be referred to as a source-drain metal layer (SD).

[0201] In an exemplary embodiment, the third conductive layer of each subpixel in the display substrate may include at least a third plate 13 , a first connection electrode 51 , a second connection electrode 52 , a third connection electrode 53 , a fourth connection electrode 54 , a fifth connection electrode 55 and an anode connection electrode 56 .

[0202] In an exemplary embodiment, the third plate 13 may be in the shape of a block (e.g., a rectangle), and the corners of the block may be chamfered, protruded, or recessed. The third plate 13 may be disposed in each sub-pixel of the display unit 110. The orthographic projection of the third plate 13 on the substrate at least partially overlaps the orthographic projection of the second plate 12 on the substrate, and the third plate 13 is connected to the first plate 11 via a seventh via hole V7. The third plate 13 may serve as the upper plate (the second end of the storage capacitor) of the storage capacitor, with the second plate 12 and the third plate 13 forming a second sub-capacitor of the storage capacitor in the pixel driving circuit.

[0203] In an exemplary embodiment, the first connection electrode 51 may be in the shape of a strip extending along the second direction Y. A first end of the first connection electrode 51 is connected to the second region of the first active layer via a second via hole V2, and a second end of the first connection electrode 51 is connected to the second electrode plate 12 via an eighth via hole V8. In an exemplary embodiment, since the second electrode plate 12 is connected to the second gate electrode 24, the first connection electrode 51 connects the second electrode of the first transistor T1, the gate electrode of the second transistor T2, and the second electrode plate 12 of the storage capacitor, forming a first node N1 of the pixel driving circuit. As a result, the second electrode plate 12 has the potential of the first node N1.

[0204] In an exemplary embodiment, the second connection electrode 52 may be in the shape of a strip extending along the second direction Y, a first end of the second connection electrode 52 is connected to the second region of the second active layer through the fourth via hole V4, and a second end of the second connection electrode 52 is connected to the third electrode plate 13.

[0205] In an exemplary embodiment, in at least one sub-pixel, the second connection electrode 52 and the third electrode plate 13 may be an integrated structure connected to each other.

[0206] In an exemplary embodiment, the third connection electrode 53 may be in the shape of a strip extending along the second direction Y, a first end of the third connection electrode 53 is connected to the second region of the third active layer through the sixth via hole V6, and a second end of the third connection electrode 53 is connected to the third electrode plate 13.

[0207] In an exemplary embodiment, in at least one sub-pixel, the third connection electrode 53 and the third electrode plate 13 may be an integral structure connected to each other.

[0208] In the exemplary embodiment, the second connection electrode 52 and the third connection electrode 53 connect the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the third plate 13 of the storage capacitor, forming a second node N2 of the pixel driving circuit. Because the third plate 13 is connected to the first plate 11 through a via, the first plate 11 and the third plate 13 have the potential of the second node N2.

[0209] In an exemplary embodiment, the first plate 11 and the third plate 13 have a potential of the second node N2, and the second plate 12 has a potential of the first node N1, so that the first plate 11 and the second plate 12 form a first sub-capacitor, and the second plate 12 and the third plate 13 form a second sub-capacitor. The first sub-capacitor and the second sub-capacitor connected in parallel constitute a storage capacitor of the pixel driving circuit.

[0210] In an exemplary embodiment, the fourth connection electrode 54 may be in a block shape (eg, rectangular) and is connected to both the first region of the third active layer and the compensation connection line 44 through the fifth via hole V5 .

[0211] In an exemplary embodiment, since two adjacent sub-pixels in one pixel column share the first region of the third active layer and the fifth via hole V5 , the two sub-pixels share one fourth connection electrode 54 .

[0212] In an exemplary embodiment, the shape of the fifth connection electrode 55 can be a strip shape extending along the second direction Y, the first end of the fifth connection electrode 55 is connected to the first region of the second active layer through the third via hole V3, and the second end of the fifth connection electrode 55 is connected to the power connection electrode 25 through the ninth via hole V9.

[0213] In an exemplary embodiment, the anode connection electrode 56 may be block-shaped (e.g., rectangular) and connected to the board-level connection electrode 14 through the tenth via V10. Since the board-level connection electrode 14 is connected to the first electrode plate 11, the anode connection electrode 56 has the potential of the second node N2.

[0214] In an exemplary embodiment, the anode connecting electrode 56 can be arranged in the light-transmitting unit 120 to change the light-transmitting area into an irregular shape. When the light passes through the irregularly shaped light-transmitting area, the positions and directions of the diffraction stripes are different. Therefore, the diffraction stripes generated by the light will not diffuse in one direction, but will diffuse in multiple directions, thereby greatly weakening the diffraction effect, avoiding the blurring of objects behind the screen, and improving the transparent display effect.

[0215] In an exemplary embodiment, the third conductive layer of each repeating unit in the display substrate may further include a first scan connection line 35 .

[0216] In an exemplary embodiment, two first scan connection lines 35 may be provided in at least one repeating unit. The first scan connection line 35 may be in the shape of a strip extending along the second direction Y. The first end of the first scan connection line 35 is connected to the first scan connection ring 31-1 via the eleventh via V11, and the second end of the first scan connection line 35 is connected to the first auxiliary connection block 33-1 via the twelfth via V12. Since the first scan connection ring 31-1 is connected to the first scan signal line 31, and the first auxiliary connection block 33-1 is connected to the first scan auxiliary line 33, the first scan signal line 31 and the first scan auxiliary line 33 are connected, thereby forming a ring-shaped first scan signal line structure.

[0217] In an exemplary embodiment, the first scan signal line 31 and the first scan auxiliary line 33 in the display unit 110 form a ring-shaped first scan signal line structure with the two first scan connection lines 35, so that the first scan signal line in the display unit 110 is a ring-shaped structure, and the first scan signal line in the light-transmitting unit 120 is a single-line structure.

[0218] In an exemplary embodiment, the ring-shaped first scanning signal line structure has a repair capability. When a short circuit occurs at a certain location on the first scanning signal line, the signal lines on both sides of the short circuit point can be cut off by laser cutting to repair the short circuit.

[0219] In an exemplary embodiment, the third conductive layer of each repeating unit in the display substrate may further include one first power line 61 , one second power line 62 , four data signal lines 63 , and one compensation signal line 64 .

[0220] In an exemplary embodiment, the shapes of the first power line 61, the second power line 62, the data signal line 63 and the compensation signal line 64 can be straight lines or broken lines with the main portion extending along the second direction Y. The first power line 61 can be located on the side of the display unit 110 in the opposite direction of the first direction X, the second power line 62 can be located on the side of the display unit 110 in the first direction X, the compensation signal line 64 can be located between the two first power lines 61, the first data signal line 63 of the four data signal lines 63 can be located on the side of the first power line 61 close to the compensation signal line 64, the second data signal line 63 of the four data signal lines 63 can be located on the side of the compensation signal line 64 close to the first power line 61, the third data signal line 63 of the four data signal lines 63 can be located on the side of the compensation signal line 64 close to the second power line 62, and the fourth data signal line 63 of the four data signal lines 63 can be located on the side of the second power line 62 close to the compensation signal line 64.

[0221] In an exemplary embodiment, the first power supply line 61 and the compensation signal line 64 may define a first pixel column including a first sub-pixel P1 and a third sub-pixel P3, and the first data signal line 63 and the second data signal line 63 may be disposed in the first pixel column and located on both sides of the third electrode plate 13 in the first direction X. The second power supply line 62 and the compensation signal line 64 may define a second pixel column including a second sub-pixel P2 and a fourth sub-pixel P4, and the third data signal line 63 and the fourth data signal line 63 may be disposed in the second pixel column and located on both sides of the first electrode plate 11 in the first direction X.

[0222] In an exemplary embodiment, the orthographic projection of the compensation signal line 64 on the substrate at least partially overlaps with the orthographic projection of the vertical reference line on the substrate, the positions of the first power line 61 and the second power line 62 can be substantially mirror-symmetrical with respect to the compensation signal line 64, and the positions of the two data signal lines 63 located on the side of the compensation signal line 64 close to the first power line 61 and the positions of the two data signal lines 63 located on the side of the compensation signal line 64 close to the second power line 62 can be substantially mirror-symmetrical with respect to the compensation signal line 64.

[0223] In an exemplary embodiment, in an exemplary embodiment, the first power line 61, the second power line 62, the data signal line 63 and the compensation signal line 64 can be straight lines or broken lines of equal width, or straight lines or broken lines of unequal width. The use of straight lines or broken lines of variable width can not only facilitate the layout of the pixel structure, but also reduce parasitic capacitance.

[0224] In an exemplary embodiment, the first power line 61 can be connected to the first power auxiliary line 41 through a plurality of thirteenth vias V13. Since the first power auxiliary line 41 is connected to the power connection electrode 25 through the power connection bar 43, the power connection electrode 25 is connected to the first region of the second active layer through the fifth connection electrode 55, and the power connection electrodes 25 in the first pixel column and the second pixel column are connected to each other through the fifth electrode block 85, it is possible to achieve that one first power line 61 can write the first power signal to the first electrodes of the four second transistors T2 in the repeating unit.

[0225] In an exemplary embodiment, the first power auxiliary line 41 and the first power line 61 form a double-layer routing structure, which not only ensures the reliability of the first power signal transmission, but also effectively reduces the resistance of the first power line, effectively reduces the voltage drop of the first power signal, and improves the display effect.

[0226] In an exemplary embodiment, the one-to-four structure of the first power line in a repeating unit effectively saves the number of signal lines, reduces the occupied space, has a simple structure, a reasonable layout, fully utilizes the layout space, improves space utilization, and is conducive to improving resolution and transparency.

[0227] In an exemplary embodiment, the second power line 62 can be configured through multiple fourteenth vias V14 so that the subsequently formed second power line is connected to the second power auxiliary line 42 through the via. The second power auxiliary line 42 and the second power line 62 form a double-layer routing structure, which not only ensures the reliability of power signal transmission, but also effectively reduces the resistance of the second power line, effectively reduces the voltage drop of the second power signal, and improves the display effect.

[0228] In an exemplary embodiment, the four data signal lines 63 may include a first data signal line, a second data signal line, a third data signal line, and a fourth data signal line. The first data signal line may be located on one side of the first power line 61 in the first direction X and may be connected to the first region of the first active layer in the first subpixel P1 via a first via hole V1, thereby enabling the data signal line 63 to write a data signal into the first electrode of the first transistor T1 in the first subpixel P1. The second data signal line may be located on the other side of the compensation signal line 64 in the opposite direction of the first direction X and may be connected to the first region of the first active layer in the third subpixel P3 via a first via hole V1, thereby enabling the data signal line 63 to write a data signal into the first electrode of the first transistor T1 in the third subpixel P3. The third data signal line may be located on one side of the compensation signal line 64 in the first direction X and may be connected to the first region of the first active layer in the fourth subpixel P4 via a first via hole V1, thereby enabling the data signal line 63 to write a data signal into the first electrode of the first transistor T1 in the fourth subpixel P4. The fourth data signal line can be located on the side opposite to the first direction X of the second power line 62, and can be connected to the first area of ​​the first active layer in the second sub-pixel P2 through the first via hole V1, so that the data signal line 63 writes the data signal into the first electrode of the first transistor T1 in the second sub-pixel P2.

[0229] In an exemplary embodiment, the compensation signal line 64 can be connected to the compensation connection line 44 through the fifteenth via hole V15. Since both ends of the compensation connection line 44 are connected to the first region of the third active layer through the fourth connection electrode 54, a single compensation signal line 64 can write a compensation signal into the first electrodes of the four third transistors T3 in the repeating unit.

[0230] In an exemplary embodiment, the one-to-four structure of compensation signal lines in a repeating unit effectively saves the number of signal lines, reduces the occupied space, has a simple structure, a reasonable layout, fully utilizes the layout space, improves space utilization, and is conducive to improving resolution and transparency.

[0231] In an exemplary embodiment, since the compensation signal line 64 is arranged between the first pixel column and the second pixel column, the compensation signal line 64 is connected to the third transistors T3 in the first pixel column and the second pixel column through the compensation connection line 44 and the fourth connection electrode 54, respectively. The third transistor T3 of the first pixel column and the third transistor T3 of the second pixel column are basically symmetrically arranged with respect to the compensation signal line 64. Therefore, this symmetrical structure can ensure that the RC delay of the compensation signal written into the third transistor T3 is basically the same, thereby ensuring display uniformity.

[0232] Figure 10C for Figure 10A A magnified image of area A in the middle. Figure 10D for Figure 10A A magnified view of area B in the middle. Figure 10C and Figure 10D As shown, at least one compensation block can be provided on the compensation signal line 64, and the compensation block is configured to increase the parasitic capacitance of the compensation signal line, thereby increasing the anti-interference ability of the compensation signal line, reducing the interference of the compensation signal by external factors, improving the accuracy of the pixel compensation value, and ensuring the display effect and display quality.

[0233] In an exemplary embodiment, the compensation blocks disposed on the compensation signal line 64 may include any one or more of a first compensation block 91 , a second compensation block 92 , a third compensation block 93 , a fourth compensation block 94 , and a fifth compensation block 95 .

[0234] In an exemplary embodiment, in at least one repeating unit, a first compensation block 91 may be disposed on the compensation signal line 64. The first compensation block 91 may be block-shaped (e.g., rectangular) and may be disposed at the interface between the first pixel column and the second pixel column. The compensation block 91 is connected to the compensation signal line 64. The orthographic projection of the first compensation block 91 on the substrate at least partially overlaps with the orthographic projection of the first electrode block 81 on the substrate. The first electrode block 81 and the first compensation block 91 form a first parasitic capacitor, thereby increasing the parasitic capacitance of the compensation signal line.

[0235] In an exemplary embodiment, the compensation signal line 64 may have a signal line width L, the first compensation block 91 may have a first compensation width L1, and a ratio of the first compensation width L1 to the signal line width L may be approximately 1.5 to 2.5. The signal line width L may be an average width of the compensation signal line 64 (excluding the compensation block), the first compensation width L1 may be a maximum width of the first compensation block 91, and the signal line width L and the first compensation width L1 may be dimensions in the first direction X.

[0236] In an exemplary embodiment, the spacing between the first compensation block 91 and the adjacent data signal line 63 may be smaller than the spacing between the compensation signal line 64 and the adjacent data signal line 63 , and the spacing may be a dimension in the first direction X. Taking the data signal line 63 located in the second pixel column as an example, the spacing between the edge of the first compensation block 91 on the side close to the data signal line 63 and the edge of the data signal line 63 on the side close to the first compensation block 91 may be smaller than the spacing between the edge of the compensation signal line 64 on the side close to the data signal line 63 and the edge of the data signal line 63 on the side close to the compensation signal line 64 .

[0237] In an exemplary embodiment, in at least one repeating unit, a second compensation block 92 may be disposed on the compensation signal line 64. The second compensation block 92 may be block-shaped (e.g., rectangular) and may be disposed at the interface between the first pixel column and the second pixel column. The second compensation block 92 is connected to the compensation signal line 64. The orthographic projection of the second compensation block 92 on the substrate at least partially overlaps with the orthographic projection of the second electrode block 82 on the substrate. The second electrode block 82 and the second compensation block 92 form a second parasitic capacitor, thereby increasing the parasitic capacitance of the compensation signal line.

[0238] In an exemplary embodiment, the second compensation block 92 may have a second compensation width L2, and a ratio of the second compensation width L2 to the signal line width L may be approximately 1.5 to 2.5. The second compensation width L2 may be a maximum width of the second compensation block 92, and may be a dimension in the first direction X.

[0239] In an exemplary embodiment, the spacing between the second compensation block 92 and an adjacent data signal line 63 is smaller than the spacing between the compensation signal line 64 and an adjacent data signal line 63 , and the spacing may be a dimension in the first direction X. Taking the data signal line 63 located in the second pixel column as an example, the spacing between an edge of the second compensation block 92 close to the data signal line 63 and an edge of the data signal line 63 close to the second compensation block 92 may be smaller than the spacing between an edge of the compensation signal line 64 close to the data signal line 63 and an edge of the data signal line 63 close to the compensation signal line 64 .

[0240] In an exemplary embodiment, in at least one repeating unit, a third compensation block 93 may be disposed on the compensation signal line 64. The third compensation block 93 may be block-shaped (e.g., rectangular) and may be disposed at the interface between the first pixel column and the second pixel column. The third compensation block 93 is connected to the compensation signal line 64. The orthographic projection of the third compensation block 93 on the substrate at least partially overlaps with the orthographic projection of the third electrode block 83 on the substrate. The third electrode block 83 and the third compensation block 93 form a third parasitic capacitor, thereby increasing the parasitic capacitance of the compensation signal line.

[0241] In an exemplary embodiment, the third compensation block 93 may have a third compensation width L3, and a ratio of the third compensation width L3 to the signal line width L may be approximately 1.5 to 2.5. The third compensation width L3 may be a maximum width of the third compensation block 93 and may be a dimension in the first direction X.

[0242] In an exemplary embodiment, a distance between the third compensation block 93 and an adjacent data signal line 63 is smaller than a distance between the compensation signal line 64 and an adjacent data signal line 63 , and the distance may be a dimension in the first direction X. Taking the data signal line 63 located in the second pixel column as an example, a distance between an edge of the third compensation block 93 close to the data signal line 63 and an edge of the data signal line 63 close to the third compensation block 93 may be smaller than a distance between an edge of the compensation signal line 64 close to the data signal line 63 and an edge of the data signal line 63 close to the compensation signal line 64 .

[0243] In an exemplary embodiment, in at least one repeating unit, a fourth compensation block 94 may be disposed on the compensation signal line 64. The fourth compensation block 94 may be block-shaped (e.g., rectangular) and may be disposed at the boundary region between the first pixel column and the second pixel column, and may be connected to the compensation signal line 64. The orthographic projection of the fourth compensation block 94 on the substrate at least partially overlaps with the orthographic projection of the fourth electrode block 84 on the substrate. The fourth electrode block 84 and the fourth compensation block 94 form a fourth parasitic capacitor, thereby increasing the parasitic capacitance of the compensation signal line.

[0244] In an exemplary embodiment, the fourth compensation block 94 may have a fourth compensation width L4, and a ratio of the fourth compensation width L4 to the signal line width L may be approximately 1.5 to 2.5. The fourth compensation width L4 may be a maximum width of the fourth compensation block 94 and may be a dimension in the first direction X.

[0245] In an exemplary embodiment, a distance between the fourth compensation block 94 and an adjacent data signal line 63 is smaller than a distance between the compensation signal line 64 and an adjacent data signal line 63 , and the distance may be a dimension in the first direction X. Taking the data signal line 63 located in the second pixel column as an example, a distance between an edge of the fourth compensation block 94 close to the data signal line 63 and an edge of the data signal line 63 close to the fourth compensation block 94 may be smaller than a distance between an edge of the compensation signal line 64 close to the data signal line 63 and an edge of the data signal line 63 close to the compensation signal line 64 .

[0246] In an exemplary embodiment, in at least one repeating unit, a fifth compensation block 95 may be disposed on the compensation signal line 64. The fifth compensation block 95 may be block-shaped (e.g., rectangular) and may be disposed at the interface between the first pixel column and the second pixel column. The fifth compensation block 95 is connected to the compensation signal line 64. The orthographic projection of the fifth compensation block 95 on the substrate at least partially overlaps with the orthographic projection of the fifth electrode block 85 on the substrate. The fifth electrode block 85 and the fifth compensation block 95 form a fifth parasitic capacitor, thereby increasing the parasitic capacitance of the compensation signal line.

[0247] In an exemplary embodiment, the fifth compensation block 95 may have a fifth compensation width L5 , and a ratio of the fifth compensation width L5 to the signal line width L may be approximately 1.5 to 2.5. The fifth compensation width L5 may be a maximum width of the fifth compensation block 95 , and may be a dimension in the first direction X.

[0248] In an exemplary embodiment, a distance between the fifth compensation block 95 and an adjacent data signal line 63 is smaller than a distance between the compensation signal line 64 and an adjacent data signal line 63 , and the distance may be a dimension in the first direction X. Taking the data signal line 63 located in the second pixel column as an example, a distance between an edge of the fifth compensation block 95 close to the data signal line 63 and an edge of the data signal line 63 close to the fifth compensation block 95 may be smaller than a distance between an edge of the compensation signal line 64 close to the data signal line 63 and an edge of the data signal line 63 close to the compensation signal line 64 .

[0249] In an exemplary embodiment, the overlapping positions of the compensation signal line 64 and the second conductive layer can be differentially designed with increased width, thereby increasing the parasitic capacitance between the compensation signal line 64 and the second conductive layer, while a narrow width design is adopted in the non-overlapping area to reduce the fringe field capacitance between the data signal line 63 and the compensation signal line 64, thereby reducing the mutual influence between the data signal line 63 and the compensation signal line 64.

[0250] In an exemplary embodiment, the third conductive layer of each repeating unit in the display substrate may further include at least one first auxiliary electrode 65 and at least one auxiliary connecting bar 65 - 1 .

[0251] In an exemplary embodiment, the first auxiliary electrode 65 may be in a block shape (e.g., a rectangular shape) and may be disposed in the light-transmitting unit 120 near the second sub-pixel P2 and the fourth sub-pixel P4, and near the second power line 62. The auxiliary connection bar 65-1 may be in a bar shape extending along the first direction X and may be disposed between the second power line 62 and the first auxiliary electrode 65, with a first end of the auxiliary connection bar 65-1 connected to the second power line 62 and a second end of the auxiliary connection bar 65-1 connected to the first auxiliary electrode 65.

[0252] In an exemplary embodiment, in at least one repeating unit, two first auxiliary electrodes 65 may be disposed in the light transmitting unit 120 close to the second subpixel P2 , and the two first auxiliary electrodes 65 may be disposed on both sides of the anode connection electrode 56 in the second subpixel P2 in the second direction Y.

[0253] In an exemplary embodiment, in at least one repeating unit, two first auxiliary electrodes 65 may be disposed in the light transmitting unit 120 near the fourth subpixel P4 , and the two first auxiliary electrodes 65 may be disposed on both sides of the anode connection electrode 56 in the fourth subpixel P4 in the second direction Y.

[0254] In an exemplary embodiment, in at least one repeating unit, the second power line 62 , the plurality of first auxiliary electrodes 65 , and the plurality of auxiliary connection bars 65 - 1 may be an integral structure connected to each other.

[0255] In an exemplary embodiment, the first auxiliary electrode 65 is provided in the light-transmitting unit 120 to change the light-transmitting area into an irregular shape. When light passes through the irregularly shaped light-transmitting area, the positions at which diffraction stripes are generated are different, and the directions in which diffraction stripes are generated are different. Therefore, the diffraction stripes generated by the light do not diffuse in one direction, but diffuse in multiple directions, thereby greatly weakening the diffraction effect, avoiding the blurring of objects behind the screen, and improving the transparent display effect.

[0256] (6) Forming a flat layer and a fourth insulating layer pattern. In an exemplary embodiment, forming the flat layer and the fourth insulating layer pattern may include: first coating a flat film on the substrate on which the aforementioned pattern is formed, patterning the flat film through a patterning process, then depositing a fourth insulating film, patterning the fourth insulating film through a patterning process, forming a flat layer covering the third conductive layer and a fourth insulating layer pattern disposed on the flat layer, wherein the flat layer is provided with a flat opening, and the fourth insulating layer is provided with a plurality of via holes, such as Figure 11 shown.

[0257] In an exemplary embodiment, the planar layer covers the display unit 110 on one hand, and covers the area where the first scan signal line 31 and the second scan signal line 32 of the light-transmitting unit 120 are located on the other hand. The planar opening TV1 provided on the planar layer can be located outside the area of ​​the first scan signal line 31 and the second scan signal line 32 of the light-transmitting unit 120. The planar film within the planar opening TV1 is removed, exposing the third conductive layer.

[0258] In an exemplary embodiment, the shape of the flat opening TV1 can be rectangular, and the corners of the rectangle can be provided with grooves or chamfers. The anode connecting electrode 56 and the first auxiliary electrode 65 in the light-transmitting unit 120 can be located within the range of the flat opening TV1, that is, the flat film above the anode connecting electrode 56 and the first auxiliary electrode 65 is removed.

[0259] In an exemplary embodiment, the plurality of via holes of at least one repeating unit may include at least four twenty-first via holes V21 and four twenty-second via holes V22 .

[0260] In an exemplary embodiment, the twenty-first via hole V21 can be arranged in the light-transmitting unit 120, and the orthographic projection of the twenty-first via hole V21 on the substrate is located within the range of the orthographic projection of the anode connecting electrode 56 on the substrate. The fourth insulating layer in the twenty-first via hole V21 is etched away to expose the surface of the anode connecting electrode 56, and the twenty-first via hole V21 is configured to connect the subsequently formed first electrode to the anode connecting electrode 56 through the via hole.

[0261] In an exemplary embodiment, the orthographic projection of the twenty-first via hole V21 on the substrate is located within the range of the orthographic projection of the flat opening TV1 on the substrate.

[0262] In an exemplary embodiment, the twenty-second via hole V22 can be arranged in the light-transmitting unit 120, and the orthographic projection of the twenty-second via hole V22 on the substrate is located within the range of the orthographic projection of the first auxiliary electrode 65 on the substrate. The fourth insulating layer in the twenty-second via hole V22 is etched away to expose the surface of the first auxiliary electrode 65, and the twenty-second via hole V22 is configured to connect the subsequently formed second auxiliary electrode to the first auxiliary electrode 65 through the via hole.

[0263] In an exemplary embodiment, the orthographic projection of the twenty-second via hole V22 on the substrate is located within the range of the orthographic projection of the flat opening TV1 on the substrate.

[0264] (7) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate having the aforementioned pattern formed thereon, patterning the fourth conductive film through a patterning process to form a fourth conductive layer pattern, such as Figure 12A and Figure 12B As shown, Figure 12B for Figure 12A Schematic diagram of the fourth conductive layer in .

[0265] In an exemplary embodiment, the fourth conductive layer of each sub-pixel in the display substrate may include at least a first electrode 71 , and the first electrode 71 may serve as one electrode of an anode in a light emitting device.

[0266] In an exemplary embodiment, the first electrode 71 may include at least a first sub-electrode 71-1, a second sub-electrode 71-2, and a sub-connecting electrode 71-3. The first sub-electrode 71-1 and the second sub-electrode 71-2 may be rectangular in shape and may be disposed on a flat layer of the display unit 110. The first sub-electrode 71-1 and the second sub-electrode 71-2 may be sequentially disposed along the second direction Y, and the first sub-electrode 71-1 and the second sub-electrode 71-2 may be isolated from each other.

[0267] In an exemplary embodiment, the main portion of the sub-connecting electrode 71-3 may be disposed on the fourth insulating layer. The sub-connecting electrode 71-3 may be shaped like a "C," with a first end connected to the first sub-electrode 71-1, a second end connected to the second sub-electrode 71-2, and an area between the first and second ends connected to the anode connecting electrode 56 via a twenty-first via hole V21. Because the anode connecting electrode 56 is connected to the first electrode plate 11 via the board-level connecting electrode 14, the sub-connecting electrode 71-3 not only interconnects the first sub-electrode 71-1 and the second sub-electrode 71-2, but also connects the first electrode 71 to the second node N2 in the pixel driving circuit.

[0268] In an exemplary embodiment, when a bright spot defect occurs on the display substrate, the sub-connecting electrode 71-3 can be cut off by laser cutting, so that one of the first sub-electrode 71-1 and the second sub-electrode 71-2 is connected to the first electrode plate 11 and the other is floating, thereby repairing the bright spot defect.

[0269] In an exemplary embodiment, the orthographic projection of the twenty-first via hole V21 on the substrate does not overlap with the orthographic projections of the first sub-electrode 71-1 and the second sub-electrode 71-2 on the substrate, which not only improves the success rate of repairing bright spot defects and avoids the impact of the repair on the pixel driving circuit, but also ensures the flatness of the first electrode, improves the light output quality of the light-emitting device, and improves the display effect.

[0270] In an exemplary embodiment, the four first electrodes 71 in a repeating unit can be arranged in a square, with the upper left first electrode 71 connected to the pixel driving circuit in the first subpixel P1, the upper right first electrode 71 connected to the pixel driving circuit in the second subpixel P2, the lower left first electrode 71 connected to the pixel driving circuit in the third subpixel P3, and the lower right first electrode 71 connected to the pixel driving circuit in the fourth subpixel P4. In some possible implementations, the arrangement of the first electrodes can be adjusted according to actual needs and is not specifically limited in this disclosure.

[0271] In an exemplary embodiment, in at least one sub-pixel, the first sub-electrode 71 - 1 , the second sub-electrode 71 - 2 , and the sub-connection electrode 71 - 3 may be an integral structure connected to each other.

[0272] In an exemplary embodiment, the fourth conductive layer of at least one repeating unit may further include at least one second auxiliary electrode 66. The second auxiliary electrode 66 may be disposed in the light-transmitting unit 120 on one side of the second sub-pixel P2 and the fourth sub-pixel P4 in the first direction X. The second auxiliary electrode 66 may be in a block shape (e.g., a rectangle), and the orthographic projection of the second auxiliary electrode 66 on the substrate at least partially overlaps the orthographic projection of the first auxiliary electrode 65 on the substrate. The second auxiliary electrode 66 may be connected to the first auxiliary electrode 65 through a twenty-second via hole V22. The second auxiliary electrode 66 is configured to be connected to a third auxiliary electrode formed subsequently.

[0273] In an exemplary embodiment, the fourth conductive layer may be made of a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0274] (8) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer pattern may include: depositing a fifth conductive film on the substrate having the aforementioned pattern formed thereon, patterning the fifth conductive film through a patterning process, and forming the fifth conductive layer pattern, such as Figure 13A and Figure 13B As shown, Figure 13B for Figure 13A Schematic diagram of the fifth conductive layer in .

[0275] In an exemplary embodiment, the fifth conductive layer of each sub-pixel in the display substrate may include at least the second electrode 72 , which may serve as another electrode of the anode in the light emitting device.

[0276] In an exemplary embodiment, the second electrode 72 may include a third sub-electrode 72-1 and a fourth sub-electrode 72-2 arranged in sequence along the second direction Y. The shapes of the third sub-electrode 72-1 and the fourth sub-electrode 72-2 may be rectangular, and the third sub-electrode 72-1 and the fourth sub-electrode 72-2 are isolated from each other.

[0277] In an exemplary embodiment, the orthographic projection of the third sub-electrode 72-1 on the substrate at least partially overlaps the orthographic projection of the first sub-electrode 71-1 on the substrate, and the third sub-electrode 72-1 directly overlaps the first sub-electrode 71-1. The orthographic projection of the fourth sub-electrode 72-2 on the substrate at least partially overlaps the orthographic projection of the second sub-electrode 71-2 on the substrate, and the fourth sub-electrode 72-2 directly overlaps the second sub-electrode 71-2.

[0278] In an exemplary embodiment, the fifth conductive layer of at least one repeating unit may further include a third auxiliary electrode 67. The third auxiliary electrode 67 may be disposed in the light-transmitting unit 120 on one side of the second sub-pixel P2 and the fourth sub-pixel P4 in the first direction X. The third auxiliary electrode 67 may be in a block shape (e.g., a rectangle), and the orthographic projection of the third auxiliary electrode 67 on the substrate at least partially overlaps with the orthographic projection of the second auxiliary electrode 66 on the substrate, and the third auxiliary electrode 67 directly overlaps the second auxiliary electrode 66.

[0279] In exemplary embodiments, the stacked first auxiliary electrode 65 , the second auxiliary electrode 66 , and the third auxiliary electrode 67 may constitute an auxiliary cathode.

[0280] In an exemplary embodiment, the third auxiliary electrode 67 is configured to be connected to a subsequently formed third electrode, thereby achieving a connection between the second power line 62 and the third electrode. Considering the voltage drop (IR drop) problem that exists in large-scale transparent displays, the present disclosure provides a second power line that transmits a second voltage signal in each repeating unit. The second power line is connected to the third electrode in the subsequently formed light-emitting structure layer via an auxiliary cathode. This can effectively reduce the voltage drop of the third electrode, effectively solving the voltage drop problem that exists in large-scale transparent displays and ensuring display uniformity.

[0281] In an exemplary embodiment, the auxiliary cathode can adopt an isolation column (RIB) structure, and the cross-sectional shape of the auxiliary cathode can be an inverted trapezoid or an "I" shape, so that the subsequently formed organic light-emitting layer can be disconnected at the side edge of the auxiliary cathode to form an isolated and isolated organic light-emitting block, which can effectively avoid the interference of the organic light-emitting block on the outgoing light, improve the quality of the outgoing light, and help improve the display quality.

[0282] In an exemplary embodiment, the fifth conductive layer may be made of a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0283] (9) Sequentially forming a pixel definition layer, an organic light-emitting layer, and a third electrode pattern. In an exemplary embodiment, sequentially forming a pixel definition layer, an organic light-emitting layer, and a third electrode pattern may include: first forming a pixel definition layer, wherein the pixel definition layer is provided with at least a first pixel opening, a second pixel opening, and a light-transmitting opening, wherein the first pixel opening exposes the surface of the third sub-electrode, and the second pixel opening exposes the surface of the fourth sub-electrode, and the light-transmitting opening may be provided in the light-transmitting unit 120. Subsequently, an organic light-emitting layer pattern is formed in the display unit 110, and the organic light-emitting layer is connected to the third sub-electrode and the fourth sub-electrode through the first pixel opening and the second pixel opening, respectively. Subsequently, a third electrode is formed, wherein the third electrode of the display unit 110 is connected to the organic light-emitting layer, and the third electrode of the light-transmitting unit 120 is connected to the third auxiliary electrode. In an exemplary embodiment, the third electrode may be a cathode of the light-emitting device.

[0284] In an exemplary embodiment, the organic light-emitting layer may include an emission layer (EML), and any one or more of the following layers: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the organic light-emitting layer may be formed using a fine metal mask (FMM) or open mask evaporation, or using an inkjet process.

[0285] In an exemplary embodiment, the preparation process of the display substrate may further include forming an encapsulation structure layer pattern. The formation of the encapsulation structure layer pattern may include: first using an open mask to deposit a first inorganic thin film to form a first encapsulation layer. Subsequently, an organic material is inkjet printed on the first encapsulation layer using an inkjet printing process, and after curing into a film, a second encapsulation layer is formed. Subsequently, a second inorganic thin film is deposited using an open mask to form a third encapsulation layer, and the first encapsulation layer, the second encapsulation layer and the third encapsulation layer constitute an encapsulation structure layer. The first encapsulation layer and the third encapsulation layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), silicon carbide (SiC), silicon carbonitride (SiCN) and silicon oxynitride (SiON), and can be a single layer, a multilayer or a composite layer. The second encapsulation layer can be made of a resin material to form a laminated structure of inorganic material / organic material / inorganic material. The organic material layer is arranged between the two inorganic material layers to ensure that external water vapor cannot enter the light-emitting structure layer. At this point, the preparation of the display substrate of the exemplary embodiment of the present disclosure is completed.

[0286] In an exemplary embodiment, the preparation process of the display substrate may further include forming film layers such as a color filter layer and a black matrix. The black matrix has a plurality of opening areas arranged in a matrix, and the color filter layer is filled in the opening areas. This disclosure does not limit this.

[0287] In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may be, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The material of the semiconductor layer may be amorphous silicon (a-Si).

[0288] In an exemplary embodiment, the first conductive layer, the second conductive layer, and the third conductive layer can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single layer structure or a multilayer composite structure, such as Mo / Cu / Mo. The first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single layer, a multilayer, or a composite layer. The planar layer can be made of an organic material, such as a resin.

[0289] A display substrate exhibits display anomalies and other defects. Research has shown that display anomalies are caused by interference with the compensation signal. For transparent display substrates using external compensation pixel drive circuits, the compensation signal lines are highly sensitive in various sizes and scenarios. These lines are easily affected by external factors, which can interfere with the compensation value and cause display anomalies.

[0290] An exemplary embodiment of the present disclosure provides a display substrate. By setting electrode blocks and compensation blocks, the electrode blocks and the compensation blocks form parasitic capacitance, which effectively increases the parasitic capacitance of the compensation signal line, effectively increases the load of the compensation signal line, and effectively increases the anti-interference ability of the compensation signal line, thereby reducing the interference of the compensation signal by external factors, improving the accuracy of the pixel compensation value, and ensuring the display effect and display quality.

[0291] In the embodiment of the present disclosure, a first electrode plate is provided in the first conductive layer, a second electrode plate is provided in the second conductive layer, and a third electrode plate is provided in the third conductive layer. The first electrode plate and the second electrode plate form a first sub-capacitor, the second electrode plate and the third electrode plate form a second sub-capacitor, and the first sub-capacitor and the second sub-capacitor connected in parallel constitute the storage capacitor of the pixel driving circuit. On the one hand, the capacitance value of the storage capacitor can be effectively increased. On the other hand, the electrode plate area can be reduced while ensuring the capacitance value of the storage capacitor, thereby effectively reducing the occupied area of ​​the pixel driving circuit, which is conducive to achieving high-resolution display.

[0292] The embodiment of the present disclosure arranges the anode in a sub-pixel to include two sub-electrodes arranged at intervals, and the two sub-electrodes are connected by a sub-connecting electrode. This not only improves the success rate of repairing bright spot defects, avoids the impact of the repair on the pixel driving circuit, and does not cause other defects, but also has a high repair success rate. It can also ensure the flatness of the anode, improve the light output quality of the light-emitting device, and improve the display effect.

[0293] The exemplary embodiment of the present disclosure provides a second power line and an auxiliary cathode, and the second power line is connected to the cathode through the auxiliary cathode, which can effectively reduce the voltage drop of the second power supply and ensure display uniformity.

[0294] The embodiment of the present disclosure arranges the anode connection electrode and the auxiliary electrode in the light-transmitting unit, and uses the anode connection electrode and the auxiliary electrode to change the light-transmitting unit into an irregular shape, thereby effectively reducing the diffraction effect of the light-transmitting unit and effectively improving the transparent display effect.

[0295] The present disclosure exemplarily sets a one-to-four structure for the first power line and a one-to-four structure for the compensation signal line, thereby saving the number of signal lines and reducing the occupied space. It has a simple structure and a reasonable layout, fully utilizing the layout space, improving space utilization, and facilitating improved resolution.

[0296] The exemplary embodiments of the present disclosure can effectively increase the pixel aperture ratio and improve the display effect by adopting a first power line structure with a non-mesh structure.

[0297] The embodiment of the present disclosure provides a second power line and an auxiliary electrode, and the second power line is connected to the third electrode of the light-emitting device through the auxiliary electrode, which can effectively reduce the voltage drop of the power signal and ensure display uniformity.

[0298] The preparation process of the exemplary embodiment of the present disclosure is well compatible with the existing preparation process, and the process is simple to implement, easy to implement, high in production efficiency, low in production cost, and high in yield rate.

[0299] The structure and preparation process shown above in the present disclosure are merely exemplary. In exemplary embodiments, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs, and the present disclosure does not limit this.

[0300] In an exemplary embodiment, the display substrate of the present disclosure can be applied to a display device having a pixel driving circuit, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., which is not limited in the present disclosure.

[0301] The present disclosure further provides a display device including the aforementioned display substrate. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system, but the embodiments of the present invention are not limited thereto.

[0302] While the embodiments disclosed herein are as described above, it should be noted that the above embodiments are merely illustrative and not restrictive. Therefore, the present disclosure is not limited to what is specifically shown and described herein. Various modifications, substitutions, or omissions may be made to the forms and details of the embodiments without departing from the scope of the present disclosure.

Claims

1. A display substrate, characterized in that: It includes multiple repeating units, at least one repeating unit includes a display unit and a light-transmitting unit located on at least one side of the display unit, the display unit is configured to display an image, and the light-transmitting unit is configured to transmit light; the display unit includes multiple sub-pixels, at least one sub-pixel includes a pixel driving circuit and a compensation signal line, and the compensation signal line is configured to provide a compensation signal to the pixel driving circuit; in a direction perpendicular to the display substrate, the display substrate includes multiple conductive layers arranged on a base, a compensation block and the compensation signal line are provided in one conductive layer, the compensation block is connected to the compensation signal line, and an electrode block is provided in at least another conductive layer, the orthographic projection of the compensation block on the base at least partially overlaps with the orthographic projection of the electrode block on the base, and the compensation block and the electrode block form a parasitic capacitor.

2. The display substrate according to claim 1, wherein: The pixel driving circuit includes at least a first transistor, a gate electrode of the first transistor is connected to a first scanning signal line, and a first electrode of the first transistor is connected to a data signal line; the first scanning signal line is in the shape of a straight line or a broken line extending along a first direction, and the compensation signal line is in the shape of a straight line or a broken line extending along a second direction, and the first direction and the second direction intersect; in at least one repeating unit, a first electrode block is arranged on the first scanning signal line, the first electrode block and the first scanning signal line are an integrated structure connected to each other, and a first compensation block is arranged on the compensation signal line, the first compensation block and the compensation signal line are an integrated structure connected to each other, the orthographic projection of the first compensation block on the substrate at least partially overlaps with the orthographic projection of the first electrode block on the substrate, and the first compensation block and the first electrode block form a first parasitic capacitor.

3. The display substrate according to claim 2, wherein: The shape of the data signal line is a straight line or a broken line extending along the second direction, and the compensation signal line is arranged between two adjacent data signal lines in the first direction; in at least one repeating unit, the spacing between the compensation signal line and the adjacent data signal line is greater than the spacing between the first compensation block and the adjacent data signal line.

4. The display substrate according to claim 2, wherein: The compensation signal line has a signal line width, the first compensation block has a first compensation width, and a ratio of the first compensation width to the signal line width is 1.5 to 2.5; the signal line width and the first compensation width are dimensions in the first direction.

5. The display substrate according to claim 2, wherein: The plurality of sub-pixels include a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel, wherein the second sub-pixel is arranged on one side of the first direction of the first sub-pixel, the fourth sub-pixel is arranged on one side of the first direction of the third sub-pixel, the third sub-pixel is arranged on one side of the second direction of the first sub-pixel, and the fourth sub-pixel is arranged on one side of the second direction of the second sub-pixel; the first scan signal line is connected to the gate electrode of the first transistor in the third sub-pixel and the gate electrode of the first transistor in the fourth sub-pixel; at least one repeating unit further includes a first scan auxiliary line and a first scan connection line, and the first scan auxiliary line The first scanning auxiliary line is connected to the first scanning signal line through the first scanning connection line, and the first scanning auxiliary line is connected to the gate electrode of the first transistor in the first sub-pixel and the gate electrode of the first transistor in the second sub-pixel; a third electrode block is provided on the first scanning auxiliary line, and the third electrode block and the first scanning auxiliary line are an integrated structure connected to each other; a third compensation block is provided on the compensation signal line, and the third compensation block and the compensation signal line are an integrated structure connected to each other, the orthographic projection of the third compensation block on the substrate at least partially overlaps with the orthographic projection of the third electrode block on the substrate, and the third compensation block and the third electrode block form a third parasitic capacitor.

6. The display substrate according to claim 5, wherein: The shape of the data signal line is a straight line or a broken line extending along the second direction, and the compensation signal line is arranged between two adjacent data signal lines in the first direction; in at least one repeating unit, the spacing between the compensation signal line and the adjacent data signal line is greater than the spacing between the third compensation block and the adjacent data signal line.

7. The display substrate according to claim 5, wherein: The compensation signal line has a signal line width, the third compensation block has a third compensation width, and a ratio of the third compensation width to the signal line width is 1.5 to 2.5; the signal line width and the third compensation width are dimensions in the first direction.

8. The display substrate according to claim 5, wherein: The first scan signal line and the first scan auxiliary line are arranged in a same conductive layer, and the first scan connection line is arranged in another conductive layer.

9. The display substrate according to claim 1, wherein: The pixel driving circuit includes at least a third transistor, a gate electrode of the third transistor is connected to the second scanning signal line, and a first electrode of the third transistor is connected to the compensation signal line; the second scanning signal line is in the shape of a straight line or a broken line extending along the first direction, and the compensation signal line is in the shape of a straight line or a broken line extending along the second direction, and the first direction and the second direction intersect; in at least one repeating unit, a second electrode block is provided on the second scanning signal line, the second electrode block and the second scanning signal line are an integrated structure connected to each other, and a second compensation block is provided on the compensation signal line, the second compensation block and the compensation signal line are an integrated structure connected to each other, the orthographic projection of the second compensation block on the substrate at least partially overlaps with the orthographic projection of the second electrode block on the substrate, and the second compensation block and the second electrode block form a second parasitic capacitor.

10. The display substrate according to claim 9, wherein: The sub-pixel also includes a data signal line, which is configured to provide a data signal to the pixel driving circuit. The data signal line and the compensation signal line are in the shape of a straight line or a broken line extending along the second direction. The compensation signal line is arranged between two adjacent data signal lines in the first direction, and the first direction and the second direction intersect; in at least one repeating unit, the spacing between the compensation signal line and the adjacent data signal line is greater than the spacing between the second compensation block and the adjacent data signal line.

11. The display substrate according to claim 9, wherein The compensation signal line has a signal line width, the second compensation block has a second compensation width, and a ratio of the second compensation width to the signal line width is 1.5 to 2.5; the signal line width and the second compensation width are dimensions in the first direction.

12. The display substrate according to claim 9, wherein The plurality of sub-pixels include a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel, the second sub-pixel is arranged on one side of the first direction of the first sub-pixel, the fourth sub-pixel is arranged on one side of the first direction of the third sub-pixel, the third sub-pixel is arranged on one side of the second direction of the first sub-pixel, and the fourth sub-pixel is arranged on one side of the second direction of the second sub-pixel, and the first direction and the second direction intersect; the second scanning signal line is connected to the gate electrode of the third transistor in the third sub-pixel and the gate electrode of the third transistor in the fourth sub-pixel; at least one repeating unit further includes a second scanning auxiliary line and a second scanning connection line, The second scanning auxiliary line is connected to the second scanning signal line through the second scanning connection line, and the second scanning auxiliary line is connected to the gate electrode of the third transistor in the first sub-pixel and the gate electrode of the third transistor in the second sub-pixel; a fourth electrode block is provided on the second scanning auxiliary line, and the fourth electrode block and the second scanning auxiliary line are an integrated structure connected to each other; a fourth compensation block is provided on the compensation signal line, and the fourth compensation block and the compensation signal line are an integrated structure connected to each other, the orthographic projection of the fourth compensation block on the substrate at least partially overlaps with the orthographic projection of the fourth electrode block on the substrate, and the fourth compensation block and the fourth electrode block form a fourth parasitic capacitor.

13. The display substrate according to claim 12, wherein: The sub-pixel also includes a data signal line, which is configured to provide a data signal to the pixel driving circuit. The data signal line and the compensation signal line are in the shape of a straight line or a broken line extending along the second direction. The compensation signal line is arranged between two adjacent data signal lines in the first direction, and the first direction and the second direction intersect; in at least one repeating unit, the spacing between the compensation signal line and the adjacent data signal line is greater than the spacing between the fourth compensation block and the adjacent data signal line.

14. The display substrate according to claim 12, wherein: The compensation signal line has a signal line width, the fourth compensation block has a fourth compensation width, and a ratio of the fourth compensation width to the signal line width is 1.5 to 2.5; the signal line width and the fourth compensation width are dimensions in the first direction.

15. The display substrate according to claim 12, wherein: The second scan signal line, the second scan auxiliary line and the second scan connection line are arranged in the same conductive layer and are interconnected in an integrated structure.

16. The display substrate according to claim 1, wherein The pixel driving circuit includes a first transistor, a second transistor and a third transistor, the gate electrode of the second transistor is connected to the second electrode of the first transistor, the first electrode of the second transistor is connected to the first power line through the power connection electrode, and the second electrode of the second transistor is connected to the second electrode of the third transistor; at least one repeating unit also includes a fifth electrode block, the fifth electrode block is arranged between the power connection electrodes of two adjacent sub-pixels and is connected to the two power connection electrodes; at least one fifth compensation block is arranged on the compensation signal line, the orthographic projection of the fifth compensation block on the display substrate plane at least partially overlaps with the orthographic projection of the fifth electrode block on the display substrate plane, and the fifth compensation block and the fifth electrode block form a fifth parasitic capacitor.

17. The display substrate according to claim 16, wherein: The sub-pixel also includes a data signal line, which is configured to provide a data signal to the pixel driving circuit. The data signal line and the compensation signal line are in the shape of a straight line or a broken line extending along the second direction. The compensation signal line is arranged between two adjacent data signal lines in the first direction, and the first direction and the second direction intersect; in at least one repeating unit, the spacing between the compensation signal line and the adjacent data signal line is greater than the spacing between the fifth compensation block and the adjacent data signal line.

18. The display substrate according to claim 17, wherein: The compensation signal line has a signal line width, the fifth compensation block has a fifth compensation width, and a ratio of the fifth compensation width to the signal line width is 1.5 to 2.5; the signal line width and the fifth compensation width are dimensions in the first direction.

19. A display device, characterized in that: The display substrate comprises the display substrate according to any one of claims 1 to 18.

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