Memory storage device and copy / write circuit
By introducing a copy write circuit into the memory storage device, multiple data backups are achieved, solving the high error rate and low efficiency problems of low-order memory storage devices, and improving data reliability and memory efficiency.
Patent Information
- Application Number
- CN202421968652.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-14
- Publication Date
- 2025-10-10
- Estimated Expiration
- 2034-08-14
AI Technical Summary
Low-end memory storage devices cannot support Redundant Array of Independent Disks (RAID) technology, resulting in high error rates and low performance.
A copy-write circuit is introduced into the memory storage device to implement data copy-write through a cache buffer and a write component, and the data is written into multiple physical units respectively to back up the data.
Effectively reduce data error rates, maintain the performance of memory storage devices, and improve data recovery capabilities.
Smart Images
Figure CN223427245U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to a memory control technology, in particular to a memory storage device and a copy-write circuit. Background Art
[0002] Portable electronic devices such as mobile phones and notebook computers have experienced rapid growth in recent years, leading to a surge in consumer demand for storage media. Rewritable non-volatile memory modules (e.g., flash memory) are ideal for integration into various portable electronic devices, due to their non-volatility, power efficiency, compact size, and lack of mechanical structure.
[0003] Generally speaking, low-end memory storage devices cannot support Redundant Array of Independent Disks (RAID) technology, resulting in high error rates and low performance. Utility Model Content
[0004] The utility model provides a memory storage device and a copy-write circuit. When the hardware resources of the memory storage device are limited, the copy-write circuit is used to copy the written data to reduce the data error rate and maintain the performance of the memory storage device.
[0005] A memory storage device of the present invention includes a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The connection interface unit is connected to a host system. The memory control circuit unit is connected to the connection interface unit and the rewritable non-volatile memory module. The rewritable non-volatile memory module includes a memory array and a copy-write circuit. The memory array includes a plurality of physical units. The copy-write circuit includes a cache buffer and a write component. The write component is connected to the cache buffer. The cache buffer is configured to store data. The memory control circuit unit is configured to receive a write instruction from the host system, generate and transmit a copy-write instruction to the rewritable non-volatile memory module based on the write instruction, and write data corresponding to the write instruction into a first physical unit among the plurality of physical units and a cache buffer in the copy-write circuit. The write component is configured to write data in the cache buffer into a second physical unit among the plurality of physical units based on the copy-write instruction, wherein the first physical unit is different from the second physical unit.
[0006] In an exemplary embodiment of the present invention, the logical block address corresponding to the write command is mapped to a first physical block address corresponding to the first physical unit and a second physical block address corresponding to the second physical unit.
[0007] In the example embodiment of the present application, the memory control circuit unit is configured to write data into the first physical unit based on a first write mode.
[0008] In the example embodiment of the present application, the memory control circuit unit is configured to store data into a page buffer of the rewritable non-volatile memory module, and write the data in the page buffer into the first physical unit based on the first write mode.
[0009] In the example embodiment of the present application, the first write mode is a single-level cell (SLC) write mode.
[0010] In the example embodiment of the present application, the write component is configured to write the data in the cache buffer into a second physical unit based on a second write mode according to the copy write instruction.
[0011] In the example embodiment of the present application, the second write mode is a triple-level cell (TLC) write mode.
[0012] The copy write circuit of the present application is disposed in a rewritable non-volatile memory module. The copy write circuit includes a cache buffer and a write component. The cache buffer is configured to store data corresponding to a write instruction. The write component is configured to write the data in the cache buffer into a physical unit in the rewritable non-volatile memory module according to a copy write instruction.
[0013] Based on the above, the memory storage device and the copy write circuit of the present application can write data corresponding to a write instruction into different physical units respectively through the memory control circuit unit of the memory storage device and the write component of the copy write circuit, so as to backup the data. In this way, when data error occurs, the memory controller can use the backup data to perform data rescue operation, which can effectively reduce the data error rate and maintain the performance of the memory storage device.
[0014] In order to make the above features and advantages of the present application more obvious and easy to understand, the following example embodiments are described in detail below, and the accompanying drawings are described as follows. BRIEF DESCRIPTION OF DRAWINGS
[0015] Figure 1 is a schematic diagram of a host system, a memory storage device and an input / output (I / O) device according to an example embodiment of the present application;
[0016] Figure 2 is a schematic diagram of a host system, a memory storage device and an input / output device according to an example embodiment of the present application; is a schematic diagram of a host system, a memory storage device and an input / output device according to an example embodiment of the present application;
[0017] Figure 3 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention;
[0018] Figure 4 is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention;
[0019] Figure 5 is a schematic diagram of managing a memory array according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION
[0020] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, like reference numerals are used in the drawings and the description to refer to like or similar parts.
[0021] Generally speaking, a memory storage device (also known as a memory storage system) includes a rewritable non-volatile memory module and a controller (also known as a control circuit). The memory storage device can be used with a host system to enable the host system to write data to the memory storage device or read data from the memory storage device.
[0022] Figure 1 is a schematic diagram showing a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment of the present invention. Figure 2 FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input / output device according to an exemplary embodiment of the present invention.
[0023] Please refer to Figure 1 and Figure 2 The host system 11 may include a processor 111 , a random access memory (RAM) 112 , a read only memory (ROM) 113 , and a data transmission interface 114 . The processor 111 , the RAM 112 , the ROM 113 , and the data transmission interface 114 may be coupled to a system bus 110 .
[0024] In an example embodiment, the host system 11 can be coupled with the memory storage device 10 through a data transfer interface 114. For example, the host system 11 can store data to or read data from the memory storage device 10 via the data transfer interface 114. In addition, the host system 11 can be coupled with the I / O device 12 through the system bus 110. For example, the host system 11 can transmit output signals to or receive input signals from the I / O device 12 via the system bus 110.
[0025] In an example embodiment, the processor 111, the random access memory 112, the read only memory 113, and the data transfer interface 114 can be disposed on a motherboard 20 of the host system 11. The number of the data transfer interface 114 can be one or more. Through the data transfer interface 114, the motherboard 20 can be coupled to the memory storage device 10 via wired or wireless manner.
[0026] In an example embodiment, the memory storage device 10 can be, for example, a USB flash drive 201, a memory card 202, a solid state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 can be, for example, a near field communication (NFC) memory storage device, a WiFi memory storage device, a Bluetooth memory storage device, or a Bluetooth low energy memory storage device (e.g., iBeacon), or the like memory storage device based on various wireless communication technologies. In addition, the motherboard 20 can also be connected to various I / O devices, such as a global positioning system (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, and the like, through the system bus 110. For example, in an example embodiment, the motherboard 20 can access the wireless memory storage device 204 through the wireless transmission device 207.
[0027] In an example embodiment, the host system 11 is a computer system. In an example embodiment, the host system 11 can be any system that can substantially cooperate with the memory storage device 10 to store data. In an example embodiment, the memory storage device 10 and the host system 11 can respectively comprise Figure 3 a memory storage device 30 and a host system 31.
[0028] Figure 3 is a schematic diagram of a host system and a memory storage device according to an example embodiment of the present application. Please refer to Figure 3, the memory storage device 30 can be used in conjunction with a host system 31 to store data. For example, the host system 31 can be a system such as a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer. For example, the memory storage device 30 can be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded storage device 34 includes various types of embedded storage devices that directly connect the memory module to the substrate of the host system, such as an embedded Multi Media Card (eMMC) 341 and / or an embedded Multi Chip Package (eMCP) storage device 342.
[0029] Figure 4 is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention. Figure 4 The memory storage device 10 includes a connection interface unit 41 , a memory control circuit unit 42 , and a rewritable non-volatile memory module 43 .
[0030] The connection interface unit 41 is configured to connect to the host system 11. The memory storage device 10 can communicate with the host system 11 via the connection interface unit 41. In an exemplary embodiment, the connection interface unit 41 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. However, it must be appreciated that the present application is not limited thereto, and the connection interface unit 41 can also be compatible with the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard, or other suitable standards. The connection interface unit 41 can be packaged in a chip together with the memory control circuit unit 42, or the connection interface unit 41 can be disposed outside a chip that includes the memory control circuit unit 42.
[0031] The memory control circuit unit 42 is connected to the connection interface unit 41 and the rewritable non-volatile memory module 43. The memory control circuit unit 42 is configured to execute a plurality of logic gates or control instructions implemented in a hardware type or a firmware type and perform data writing, reading, erasing, and other operations in the rewritable non-volatile memory module 43 according to instructions from the host system 11.
[0032] The memory control circuit unit 42 includes a host interface 421, a memory controller 422, a memory interface 423, an error checking and correction circuit 424, a buffer memory 425, and a power management circuit 426.
[0033] The host interface 421 is connected to the memory controller 422. The memory controller 422 can communicate with the host system 11 through the host interface 421. The host interface 421 can be used to obtain and identify instructions and data from the host system 11. For example, instructions and data from the host system 11 can be transmitted to the memory controller 422 through the host interface 421. In addition, the memory controller 422 can transmit data to the host system 11 through the host interface 421. In this exemplary embodiment, the host interface 421 is compatible with the PCI Express standard. However, it should be understood that the present invention is not limited to this, and the host interface 421 can also be compatible with the SATA standard, the PATA standard, the IEEE 1394 standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard, or other suitable data transmission standards.
[0034] The memory controller 422 is used to control the overall operation of the memory control circuit unit 42. Specifically, the memory controller 422 has multiple control instructions, and when the memory storage device 10 operates, these control instructions are executed to perform operations such as writing, reading, and erasing data. The following description of the operation of the memory controller 422 is equivalent to describing the operation of the memory control circuit unit 42.
[0035] In one exemplary embodiment, the control instructions of the memory controller 422 are implemented in firmware. For example, the memory controller 422 includes a microprocessor unit (not shown) and a read-only memory (ROM) (not shown), and these control instructions are recorded in the ROM. When the memory storage device 10 is operating, these control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data. In another exemplary embodiment, the control instructions of the memory controller 422 are implemented in hardware, but the present invention is not limited thereto.
[0036] In one exemplary embodiment, the control instructions of the memory controller 422 may also be stored in a specific area of the rewritable non-volatile memory module 43 (e.g., a system area of the memory module dedicated to storing system data) in the form of program code. Furthermore, the memory controller 422 includes a microprocessor unit (not shown), a read-only memory (not shown), and a random access memory (RAM) (not shown). Specifically, the read-only memory includes a boot code. When the memory controller 422 is enabled, the microprocessor unit first executes this boot code to load the control instructions stored in the rewritable non-volatile memory module 43 into the RAM of the memory controller 422. The microprocessor unit then executes these control instructions to perform operations such as writing, reading, and erasing data.
[0037] The memory interface 423 is connected to the memory controller 422 and is used to access the rewritable non-volatile memory module 43. For example, the memory controller 422 can access the rewritable non-volatile memory module 43 through the memory interface 423. In other words, data to be written to the rewritable non-volatile memory module 43 is converted into a format acceptable to the rewritable non-volatile memory module 43 via the memory interface 423. Specifically, if the memory controller 422 wants to access the rewritable non-volatile memory module 43, the memory interface 423 will transmit a corresponding command sequence. For example, these command sequences may include a write command sequence instructing to write data, a read command sequence instructing to read data, an erase command sequence instructing to erase data, and corresponding command sequences for instructing various memory operations (e.g., changing a read voltage level or performing a garbage collection (GC) operation). These command sequences are generated by the memory controller 422 and transmitted to the rewritable non-volatile memory module 43 through the memory interface 423. These instruction sequences may include one or more signals or data on a bus. These signals or data may include instruction codes or program codes. For example, in a read instruction sequence, information such as an identification code and a memory address to be read may be included.
[0038] The error checking and correction circuit 424 is connected to the memory controller 422 and is used to perform error checking and correction operations to ensure data accuracy. Specifically, when the memory controller 422 receives a write command from the host system 11, the error checking and correction circuit 424 generates an error correcting code (ECC) and / or an error detecting code (EDC) corresponding to the data corresponding to the write command, and the memory controller 422 writes the data corresponding to the write command and the corresponding error correcting code and / or error detecting code to the rewritable non-volatile memory module 43. Subsequently, when the memory controller 422 reads data from the rewritable non-volatile memory module 43, it also reads the error correcting code and / or error detecting code corresponding to the data, and the error checking and correction circuit 424 performs error checking and correction operations on the read data based on the error correcting code and / or error detecting code.
[0039] The buffer memory 425 is connected to the memory controller 422 and is used to cache data. The power management circuit 426 is connected to the memory controller 422 and is used to control the power supply of the memory storage device 10.
[0040] The rewritable non-volatile memory module 43 is used to store data written by the host system 11. The rewritable non-volatile memory module 43 is used to operate under the control of the memory control circuit unit 42. For example, the rewritable non-volatile memory module 43 is used to receive a control command and an address corresponding to the control command from the memory control circuit unit 42 for access.
[0041] The rewritable non-volatile memory module 43 includes a memory array 431 , a row decoder 432 , a column decoder 433 , a page buffer 434 , a sense amplifier 435 , an input / output circuit 436 , and a copy-write circuit 437 .
[0042] The memory array 431 may include multiple physical cells. For example, the memory array 431 may include a single-level cell (SLC) NAND flash memory module (i.e., a flash memory module in which one memory cell can store one bit), a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module in which one memory cell can store two bits), a triple-level cell (TLC) NAND flash memory module (i.e., a flash memory module in which one memory cell can store three bits), a quad-level cell (QLC) NAND flash memory module (i.e., a flash memory module in which one memory cell can store four bits), other flash memory modules, or other memory modules with similar characteristics. The memory cells of the memory array 431 may constitute multiple physical programming units, and these physical programming units may constitute multiple physical erasing units.
[0043] In one exemplary embodiment, memory cells in the same word line may constitute one or more physical programming cells. If each memory cell can store more than two bits, the physical programming cells in the same word line may be classified into at least lower physical programming cells and upper physical programming cells.
[0044] In one exemplary embodiment, a physical programming unit is the smallest unit of programming. That is, a physical programming unit is the smallest unit for writing data. For example, a physical programming unit may be a physical page or a physical sector. If a physical programming unit is a physical page, then these physical programming units may include a data bit area and a redundancy bit area. The data bit area includes multiple physical sectors for storing user data, while the redundancy bit area is used to store system data (e.g., management data such as error correction codes). In one exemplary embodiment, the data bit area includes 32 physical sectors, and the size of each physical sector is 512 bytes (bytes). However, in other exemplary embodiments, the data bit area may include 8, 16, or a larger or smaller number of physical sectors, and the size of each physical sector may be larger or smaller. On the other hand, a physical erase unit is the smallest unit of erase. That is, each physical erase unit contains the minimum number of memory cells to be erased together. For example, a physical erase unit is a physical block.
[0045] Each memory cell in the memory array 431 stores one or more bits by changing the voltage (hereinafter also referred to as the critical voltage). Specifically, there is a charge trapping layer between the control gate and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the critical voltage of the memory cell. This operation of changing the critical voltage of the memory cell is also called "writing data to the memory cell" or "programming the memory cell." As the critical voltage changes, each memory cell in the memory array 431 has multiple storage states. By applying a read voltage, it is possible to determine which storage state a memory cell belongs to, thereby obtaining the one or more bits stored in the memory cell.
[0046] The row decoder 432 and the column decoder 433 are connected to the memory array 431. The row decoder 432 and the column decoder 433 are used to decode an address from the memory control circuit unit 42, decode the address, and access the memory array 431 based on the decoded block address. For example, during operations such as writing, reading, and erasing data, data can be written to, read from, or erased from the memory array 431 based on the block address decoded by the row decoder 432 and the column decoder 433. For example, during a data write operation, the row decoder 432 and the column decoder 433 can select a physical cell (e.g., a physical programmed cell) from the memory array 431 based on the decoded block address and transmit a write voltage to the word line comprising the selected physical cell to change the threshold voltage of the memory cell in the word line.
[0047] The page buffer 434 is connected to the memory array 431, the sense amplifier 435, and the input / output circuit 436. The page buffer 434 is used to temporarily store write data for a write operation or read data for a read operation. The sense amplifier 435 is used to amplify the read data temporarily stored in the page buffer 434 or to amplify the read data read from the memory array 431. The input / output circuit 436 is used to transmit the write data written to the memory array 431 and the read data read from the memory array 431.
[0048] In one exemplary embodiment, the page buffer 434 communicates with the I / O circuit 436. For example, during a write operation, the page buffer 434 may receive write data through the I / O circuit 436. For example, during a read operation, the I / O circuit 436 may transmit the read data stored in the page buffer 434 to the memory control circuit unit 42.
[0049] In one exemplary embodiment, the number of page buffers 434 and sense amplifiers 435 is related to the number of physical planes formed by the multiple physical blocks in the memory array 431. For example, if the memory array 431 includes two physical planes, the rewritable non-volatile memory module 43 may include two page buffers 434 and two sense amplifiers 435.
[0050] The copy-write circuit 437 includes a cache buffer 4371 and a write component 4372. The cache buffer 4371 is used to store data corresponding to a write instruction. The write component 4372 is used to write the data in the cache buffer 4371 to the physical unit in the memory array 431 according to the copy-write instruction.
[0051] Figure 5 FIG is a schematic diagram of a memory array management system according to an exemplary embodiment of the present invention. Figure 5 The memory controller 422 may logically group the physical units 510 ( 0 ) to 510 (B) in the memory array 431 into a storage area 501 and a spare area 502 .
[0052] In one exemplary embodiment, a physical unit refers to a physical address or a physical programming unit. In one exemplary embodiment, a physical unit may also be composed of multiple consecutive or discontinuous physical addresses. In one exemplary embodiment, a physical unit may also refer to a virtual block (VB). A virtual block may include multiple physical addresses or multiple physical programming units. In one exemplary embodiment, a virtual block may include one or more physical erase units.
[0053] The physical units 510(0) to 510(A) in the storage area 501 are used to store user data (e.g. Figure 1 user data of the host system 11). For example, the physical units 510(0) to 510(A) in the storage area 501 can store valid data and invalid data. The physical units 610(A+1) to 610(B) in the idle area 502 do not store data (e.g., valid data). For example, if a physical unit does not store valid data, the physical unit can be associated (or added) to the idle area 502. In addition, the physical units in the idle area 502 (or the physical units that do not store valid data) can be erased. When writing new data, one or more physical units can be extracted from the idle area 502 to store the new data. In one exemplary embodiment, the idle area 502 is also called a free pool.
[0054] The memory controller 422 can configure logical units 512(0)-512(C) to map physical units 510(0)-510(A) in the memory area 501. In one exemplary embodiment, each logical unit corresponds to a logical address. For example, a logical address may include one or more logical block addresses (LBAs) or other logical management units. In one exemplary embodiment, a logical unit may also correspond to a logical programming unit or may be composed of multiple consecutive or non-consecutive logical addresses.
[0055] Note that a logical unit can be mapped to one or more physical units. If a physical unit is currently mapped by a logical unit, the data currently stored in the physical unit is valid. Conversely, if a physical unit is not currently mapped by any logical unit, the data currently stored in the physical unit is invalid.
[0056] The memory controller 422 may record management data describing the mapping relationship between logical units and physical units (also known as logical-to-physical mapping information) in at least one logical-to-physical mapping table. When the host system 11 wishes to read data from or write data to the memory storage device 10, the memory controller 422 may access the memory array 431 based on the information in the logical-to-physical mapping table.
[0057] To reduce data error rates and maintain the performance of the memory storage device 10, the present invention provides a copy-write circuit 437 disposed within the rewritable non-volatile memory module 43. The copy-write circuit 437 includes a write component 4371 and a cache buffer 4372. The write component 4371 may be, for example, a logic circuit with write functionality well known to those skilled in the art. The cache buffer 4372 may be one or more. While the memory controller 422 writes data to a physical cell in the memory array 431, the write component 4371 of the copy-write circuit 437 simultaneously writes the data to another physical cell in the memory array 431 to back up the data. This allows the memory controller 422 to use the backed-up data for data recovery in the event of a data error, effectively reducing the error rate and maintaining the performance of the memory storage device 10. Furthermore, the present invention can also increase the amount of data available for cache write operations by appropriately increasing the number of cache buffers 4372, thereby improving the performance of the memory storage device 10.
[0058] In one exemplary embodiment, the memory controller 422 may be configured to receive a write command from the host system 11, generate and transmit a copy-write command to the rewritable non-volatile memory module 43 based on the write command, and write data corresponding to the write command to a first physical unit of a plurality of physical units in the memory array 431 and to a cache buffer 4372 in the copy-write circuit 437. Specifically, the memory controller 422 may map a logical block address corresponding to the write command to a plurality of physical block addresses (PBAs) corresponding to different physical units. For example, the memory controller 422 may map the logical block address corresponding to the write command to a first physical block address of a first physical unit and a second physical block address of a second physical unit. In other words, the first physical unit is different from the second physical unit.
[0059] Next, the memory controller 422 may write the data corresponding to the write command into the first physical unit and the cache buffer 4372. Furthermore, the memory controller 422 may also generate a copy write command corresponding to the second physical block address and transmit the copy write command to the write component 4371 of the rewritable non-volatile memory module 43, instructing the write component 4371 to perform a data backup operation. Accordingly, the write component 4371 may write the data in the cache buffer 4372 into the second physical unit in the memory array 431 according to the copy write command, thereby completing the data backup operation.
[0060] In this way, if an error occurs in the data stored in the first physical unit (or the second physical unit) in subsequent operations, the memory controller 422 can perform data rescue operations on the data in the first physical unit (or the second physical unit) through the data stored in the second physical unit (or the first physical unit), thereby effectively reducing the error rate and maintaining the performance of the memory storage device 10.
[0061] In one exemplary embodiment, while the memory controller 422 writes data corresponding to a write command to a first physical cell in the memory array 431, the write component 4371 may write data in the cache buffer 4372 to a second physical cell in the memory array 431 that is different from the first physical cell according to a copy write command. Specifically, the memory controller 422 may write the data corresponding to the write command to the first physical cell according to a first write mode, and the write component 4371 may write the data in the cache buffer 4372 to the second physical cell according to a second write mode according to the copy write command. In one exemplary embodiment, the first write mode may be, for example, a single-level cell (SLC) write mode, and the second write mode may be, for example, a second-level cell (MLC) write mode, a third-level cell (TLC) write mode, or a fourth-level cell (QLC) write mode. In another exemplary embodiment, the first write mode may be, for example, a second-level cell write mode, a third-level cell write mode, or a fourth-level cell write mode, and the second write mode may be, for example, a single-level cell write mode.
[0062] Based on the above, the memory storage device 10 can write data corresponding to a write command to the first physical unit and the second physical unit in the memory array 431 through the memory controller 422 and the write component 4371, respectively, to perform a backup operation for the data corresponding to the write command. Accordingly, if an error occurs in the data stored in one physical unit during a subsequent operation, the memory controller 422 can perform a data recovery operation on the physical unit using the same data stored in another physical unit, thereby effectively reducing the error rate and maintaining the performance of the memory storage device 10.
[0063] In one exemplary embodiment, the second write mode is any write mode other than the first write mode. For example, the first write mode is a single-level cell write mode, and the second write mode is a triple-level cell write mode. After receiving a write command from the host system 11, the memory controller 422 may generate and transmit a copy write command to the rewritable non-volatile memory module 43 based on the write command, and store the data corresponding to the write command in the page buffer 434 and the cache buffer 4372.
[0064] Specifically, the memory controller 422 can temporarily store data corresponding to the write command in the page buffer 434 and the cache buffer 4372 via the input / output device 426 according to the write command. Subsequently, while the memory controller 422 writes the data in the page buffer 434 to the first physical unit based on the first write mode, the write component 4371 can simultaneously write the data in the cache buffer 4372 to the second physical unit based on the second write mode to back up the data. In other words, at the same time, the memory storage device 10 can be used to simultaneously perform different write modes. The memory storage device 10 can simultaneously perform a single-level memory cell write mode and a triple-level memory cell write mode to efficiently complete the backup operation for the data corresponding to the write command.
[0065] In this way, if an error occurs in the data stored in the first physical unit (or the second physical unit) in subsequent operations, the memory controller 422 can perform data rescue operations on the data in the first physical unit (or the second physical unit) through the data stored in the second physical unit (or the first physical unit), thereby effectively reducing the error rate and maintaining the performance of the memory storage device 10.
[0066] In one exemplary embodiment, the first write mode and the second write mode are the same write mode. For example, the first write mode and the second write mode are both third-level memory cell write modes. After receiving a write command from the host system 11, the memory controller 422 can generate and transmit a copy write command based on the write command to the rewritable non-volatile memory module 43, and store the data corresponding to the write command in the page buffer 434 and the cache buffer 4372.
[0067] Specifically, the memory controller 422 may temporarily store data corresponding to the write command in the page buffer 434 and the cache buffer 4372 via the input / output device 426 according to the write command. Subsequently, the memory storage device 10 may sequentially write the data corresponding to the write command into the memory array 431 via the memory controller 422 and the write component 4371 based on a third-level cell write pattern. For example, after the memory controller 422 (or the write component 4371) writes the data in the page buffer 434 (or the cache buffer 4372) to the first physical unit (or the second physical unit) based on the third-level cell write pattern, the write component 4371 (or the memory controller 422) may write the data in the cache buffer 4372 (or the page buffer 434) to the second physical unit (or the first physical unit) based on the third-level cell write pattern to perform a data backup operation.
[0068] Therefore, if an error occurs in the data stored in the first physical unit (or the second physical unit) in a subsequent operation, the memory controller 422 can effectively reduce the error rate and maintain the performance of the memory storage device 10 by performing a data rescue operation on the data in the first physical unit (or the second physical unit) using the data stored in the second physical unit (or the first physical unit).
[0069] In summary, the memory storage device and the copy-write circuit of the present application can backup data corresponding to a write instruction. Therefore, when an error occurs in the data, the memory controller can effectively reduce the data error rate and maintain the performance of the memory storage device by performing a data rescue operation using the backup data.
[0070] Finally, it should be noted that: the above example embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; although the present application has been described in detail with reference to the foregoing example embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing example embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the example embodiments of the present application.
Claims
1. A memory storage device, characterized in that: include: Connecting the interface unit to the host system; A rewritable non-volatile memory module includes a memory array and a copy-write circuit, wherein the copy-write circuit is connected to the memory array, wherein the memory array includes a plurality of physical units; as well as a memory control circuit unit connected to the connection interface unit and the rewritable non-volatile memory module, configured to receive a write command from the host system, generate and transmit a copy-write command to the rewritable non-volatile memory module based on the write command, and write data corresponding to the write command into a first physical unit among the plurality of physical units and a cache buffer in the copy-write circuit; The copy-write circuit includes: The cache buffer is configured to store the data; as well as A write component is connected to the cache buffer and configured to write the data in the cache buffer to a second physical unit among the plurality of physical units according to the copy write instruction, wherein the first physical unit is different from the second physical unit.
2. The memory storage device according to claim 1, wherein: A logical block address corresponding to the write command is mapped to a first physical block address corresponding to the first physical unit and a second physical block address corresponding to the second physical unit.
3. The memory storage device according to claim 1, wherein: The memory control circuit unit is configured to write the data into the first physical unit based on a first write mode.
4. The memory storage device according to claim 3, wherein: The memory control circuit unit is configured to store the data in a page buffer of the rewritable non-volatile memory module, and write the data in the page buffer into the first physical unit based on the first writing mode.
5. The memory storage device according to claim 3, wherein: The first programming mode is a single-level memory cell programming mode.
6. The memory storage device according to claim 1, wherein: The write component is configured to write the data in the cache buffer into the second physical unit based on a second write mode according to the copy write instruction.
7. The memory storage device according to claim 6, wherein: The second programming mode is a three-level memory cell programming mode.
8. A copy-write circuit, provided in a rewritable non-volatile memory module, characterized in that: include: a cache buffer configured to store data corresponding to a write instruction; as well as The writing component is connected to the cache buffer and is configured to write the data in the cache buffer into the physical unit in the rewritable non-volatile memory module according to a copy write instruction.