Semiconductor die

Abstract

A semiconductor die is provided that includes a dense region and an isolation region having a plurality of under bump metal (UBM) pads in the dense region and in the isolation region, and a plurality of external electrical connectors in contact with the under bump metal pads. The external electrical connectors have a preselected vertical height.

Description

Technical Field

[0001] The present disclosure relates to semiconductor dies with bumps and associated methods of manufacturing semiconductor devices. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, for example, personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconducting layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form multiple circuit components and multiple components thereon. Typically, dozens or hundreds of integrated circuits are manufactured on a single semiconductor wafer. The individual dies are singulated by sawing the multiple integrated circuits along the scribe lines. The individual dies are then packaged separately, for example individually or in multi-chip modules, or in other types of packages.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. In some applications, these smaller electronic components, such as integrated circuit dies, may also require smaller packages (which utilize less area than previous packages). Utility Model Content

[0004] Some embodiments of the present disclosure provide a semiconductor die comprising: a dense region, a plurality of first external electrical connectors, an isolated region, and a plurality of second external electrical connectors. The dense region includes a plurality of first under-bump metallurgy (UBM) pads, wherein the dense region has a first ratio of the plurality of first under-bump metallurgy (UBM) pads per unit area. The plurality of first external electrical connectors contact the plurality of first under-bump metallurgy (UBM) pads, wherein each first external electrical connector has a first vertical height. The isolated region includes a plurality of second under-bump metallurgy (UBM) pads, wherein the isolated region has a second ratio of the plurality of second under-bump metallurgy (UBM) pads per unit area, wherein the first ratio is greater than the second ratio. The plurality of second external electrical connectors contact the plurality of second under-bump metallurgy (UBM) pads, wherein each second external electrical connector has a second vertical height. The semiconductor die is configured such that the first vertical height is equal to the second vertical height.

[0005] Other embodiments of the present disclosure provide a semiconductor die comprising: a dense region, a plurality of first external electrical connectors, an isolation region, and a plurality of second external electrical connectors. The dense region includes a plurality of first under-bump metallurgy (UBM) pads, wherein the dense region has a first ratio of the plurality of first under-bump metallurgy (UBM) pads per unit area. The plurality of first external electrical connectors contact the plurality of first under-bump metallurgy (UBM) pads, wherein each of the plurality of first external electrical connectors has a first vertical height. The isolation region includes a plurality of second under-bump metallurgy (UBM) pads and a plurality of dummy under-bump metallurgy (DBM) pads, wherein the isolation region has a second ratio of the plurality of second under-bump metallurgy (UBM) pads per unit area, wherein the first ratio is greater than the second ratio. The plurality of second external electrical connectors contact the plurality of second under-bump metallurgy (UBM) pads and the plurality of dummy under-bump metallurgy (DBM) pads, wherein each of the plurality of second external electrical connectors has a second vertical height. The semiconductor die is configured such that the first vertical height is equal to the second vertical height.

[0006] Still other embodiments of the present disclosure provide a semiconductor die comprising: a dense region, a plurality of first external electrical connectors, an isolated region, a plurality of second external electrical connectors, an intermediate region, and a plurality of third external electrical connectors. The dense region includes a plurality of first under-bump metal (UBM) pads. The plurality of first external electrical connectors contact the plurality of first under-bump metal pads, wherein each of the plurality of first external electrical connectors has a first vertical height. The isolated region includes a plurality of second under-bump metal (UBM) pads and a plurality of first dummy under-bump metal pads. The plurality of second external electrical connectors contact the plurality of second under-bump metal pads and the plurality of first dummy under-bump metal pads, wherein each of the plurality of second external electrical connectors has a second vertical height. The intermediate region is disposed between the dense region and the isolated region, and includes a plurality of third under-bump metal pads and a plurality of second dummy under-bump metal pads. A plurality of third external electrical connectors are in contact with the plurality of third under bump metallurgy pads and the plurality of second dummy under bump metallurgy pads, wherein each of the plurality of third external electrical connectors has a third vertical height, wherein the first vertical height, the second vertical height, and the third vertical height are equal. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present disclosure can be seen in the following detailed description and in conjunction with the accompanying Figure 1 Please read together for the best understanding. It is noted that, according to standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figures 1 to 8are cross-sectional views of a plurality of intermediate steps during a process for forming a package structure according to some embodiments;

[0009] Figures 9 to 16 are cross-sectional views of a plurality of intermediate steps during a process for forming a package structure according to some embodiments;

[0010] Figure 17 are layout diagrams of under bump metal (UBM) structures and solder bump locations in a plurality of regions of a die according to some embodiments;

[0011] Figure 18 and Figure 19 are cross-sectional views of under bump metal (UBM) structures and solder bumps in different regions in Figure 17

[0012] Figure 20 are layout diagrams of under bump metal (UBM) structures and solder bump locations in a plurality of regions of a die according to some embodiments;

[0013] Figures 21 to 23 are cross-sectional views of under bump metal (UBM) structures and solder bumps in different regions in Figure 20

[0014] Figure 24 are layout diagrams of under bump metal (UBM) structures and solder bump locations in a plurality of regions of a die according to some embodiments;

[0015] Figure 25 are layout diagrams of shapes of under bump metal (UBM) structures according to some embodiments;

[0016] Figure 26 are flow diagrams of methods according to some embodiments.

[0017]

Symbol Explanation

[0018] 20: carrier substrate

[0019] 22: release layer

[0020] 24: adhesive

[0021] 26: die

[0022] 28: pad

[0023] 30: passivation film

[0024] 32: die connector

[0025] ​​34: Dielectric material (dielectric layer)

[0026] 36: Sealant

[0027] 38: Dielectric layer

[0028] 40:Metalized pattern

[0029] 42: Guide hole

[0030] 44: dielectric layer

[0031] 46: Opening

[0032] 48: Seed layer

[0033] 50: Photoresist

[0034] 52: Opening

[0035] 60: Underbump Metal

[0036] 61: Active under-bump metal (under-bump metal, under-bump metal structure)

[0037] 62: dummy under-bump metal (dummy under-bump metal structure)

[0038] 63: dummy under-bump metal (dummy under-bump metal structure)

[0039] 70: Lower structure

[0040] 100: Package (package structure)

[0041] 140: conductive contacts

[0042] 142: Opening

[0043] 144: passivation layer

[0044] 145: Insulation material

[0045] 148: Conductive material

[0046] 150: Photoresist

[0047] 151: Opening

[0048] 158: Conductive material

[0049] 160: Underbump metal structure (underbump metal, underbump metal pad)

[0050] 161: Active under-bump metal structure (under-bump metal pad)

[0051] 161': Active under-bump metal structure

[0052] 162: dummy under-bump metal structure (dummy under-bump metal pad)

[0053] 163: dummy under-bump metal structure (dummy under-bump metal pad)

[0054] 170: External electrical connector

[0055] 201: dense area (first area, area)

[0056] 202: Isolation area (second area, area)

[0057] 203: Middle area (third area, area)

[0058] 900: Method

[0059] D1: Distance

[0060] D2: Distance

[0061] D8: Distance between structures

[0062] D9: Distance between active structures

[0063] H1: Height

[0064] H2: Height

[0065] P1: First spacing

[0066] P2: Second spacing

[0067] S902: Operation

[0068] S904: Operation

[0069] S906: Operation

[0070] S908: Operation

[0071] S910: Operation

[0072] W1: Critical dimension (lateral width) DETAILED DESCRIPTION

[0073] The ensuing description provides numerous different embodiments or examples for implementing various features of the provided subject matter. The following description is made in connection with the described examples, but is not intended to limit the application. For example, in the ensuing description, forming a first feature directly above or over a second feature can include embodiments in which the first feature and the second feature are formed to be in direct contact, and can also include embodiments in which additional features can be formed between the first feature and the second feature such that the first feature and the second feature can not be in direct contact. As used herein, "directly above" refers to vertical alignment of features such that a vertical axis passes through both features when the feature above is directly over the feature below. Additionally, the present disclosure can refer back to the same reference numerals and / or letters in various embodiments. Such references are for the purpose of simplicity and clarity and the repetition itself does not imply a relationship between and / or among the various embodiments discussed.

[0074] Further, to facilitate description of the relationship between an element or feature and another element or feature as depicted in the drawings, spatially relative terms such as "directly above", "above", "overlying", "higher", "upward", "top", "below", "underlying", "beneath", "lower", "bottom", "side", "positive slope", and "negative slope", and the like, can be used. The spatially relative terms are intended to encompass different orientations of the device in use or operation, and so the device can be oriented in more ways than those depicted in the figures. The device can be oriented in other ways (rotated at 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0075] All numbers expressing quantities, ratios, physical properties, and / or use of terms herein are to be understood as approximations based on the nature of the quantities, ratios, physical properties, and / or use of terms used by persons skilled in the art. Unless otherwise stated, all such numbers are to be understood as being modified in all instances by a term selected from the group of "about", "approximately", "substantially", and "nearly". When modifying a numerical value in the specification or claims, "about" indicates a range of accuracy familiar and acceptable to one skilled in the art. Generally, such a range of accuracy is ±10 percent. Thus, "about ten" means nine to eleven.

[0076] In certain embodiments herein, a "material structure" comprises at least 50% by weight of the identified material, such as at least 60% by weight of the identified material, at least 75% by weight of the identified material, at least 90% by weight of the identified material, at least 95% by weight of the identified material, or at least 99% by weight of the identified material; and a structure formed from a "material" comprises at least 50% by weight of the identified material, such as at least 60% by weight of the identified material, at least 75% by weight of the identified material, at least 90% by weight of the identified material, at least 95% by weight of the identified material, or at least 99% by weight of the identified material. For example, in certain embodiments, each of a tungsten structure and a structure formed from tungsten is at least 50%, at least 60%, at least 75%, at least 90%, at least 95%, or at least 99% by weight of tungsten.

[0077] For the sake of brevity, known techniques related to the manufacture of semiconductor devices may not be described in detail herein. In addition, the various tasks and processes described herein may be incorporated into more comprehensive programs or processes having additional functions that are not described in detail herein. Specifically, the various processes in the manufacture of semiconductor devices are well known, and therefore, for the sake of brevity, many processes will only be briefly mentioned or omitted entirely herein without providing known process details. It will be apparent to those skilled in the art, after reading this disclosure in its entirety, that the multiple structures disclosed herein can be used with various technologies and can be incorporated into various semiconductor devices and products. Further, it is noted that the semiconductor device structure includes different numbers of components, and that a single component shown in the accompanying drawings may represent multiple components.

[0078] The various embodiments discussed herein may be discussed in a specific context, namely, packaging structures having fan-out or fan-in wafer-level packaging. Other embodiments contemplate other applications, such as different package types or different configurations, which will be apparent to a person of ordinary skill in the art reading this disclosure. It should be noted that the various embodiments discussed herein do not necessarily depict every component or feature that may be present in the structure. For example, multiple components may be omitted from the drawings, such as when a discussion of one of the components is sufficient to convey multiple aspects of the embodiment. Furthermore, the various method embodiments discussed herein may be discussed as being performed in a particular order; however, other method embodiments may be performed in any logical order.

[0079] In various embodiments herein, external electrical connectors (i.e., bumps) are formed with uniform heights in dense areas and in isolated areas, although such multiple bumps tend to be formed with different heights, i.e., higher heights in isolated areas and lower heights in dense areas. This can be achieved in two ways. First, multiple under bump metal pads in isolated areas can be formed to have larger critical dimensions than multiple under bump metal pads in dense areas. As a result, the multiple bumps formed above the multiple under bump metal pads in the isolated areas have a lower height, similar to or the same as those in the dense areas. Second, multiple dummy under bump metal pads can be formed in the isolated areas to effectively increase the pad and bump density in such areas. As a result, multiple bumps are formed with uniform heights in both dense and isolated areas.

[0080] Thus, various embodiments herein provide for forming multiple external electrical connectors above under-bump metallization (UBM) or under-ball metallization (UBMs) with improved height uniformity in dense and isolated regions of a semiconductor die. These external electrical connectors may include a low-temperature reflowable material, such as solder, such as lead-free solder. In some embodiments, the external electrical connectors are ball grid array (BGA) solder balls, controlled collapse chip connection (C4) bumps, microbumps, or the like, or metal pillars. For example, various embodiments herein counteract the tendency for multiple external electrical connectors formed in a dense external electrical connector area to be lower in height than multiple external electrical connectors formed in an isolated external electrical connector area during a process for forming multiple external electrical connectors spanning two regions. In some embodiments, the under-bump metallization (UBM) and the external electrical connectors formed thereon in the dense region are formed to have a first critical dimension; and the under-bump metallization (UBM) and the external electrical connectors formed thereon in the isolated region are formed to have a second critical dimension that is greater than the first critical dimension. In some embodiments, a dummy UBM is formed adjacent to an isolated active UBM to reduce the relative isolation of the isolated active UBMs. As a result, external electrical connectors over the active and dummy UBMs are formed in the same or more similar manner, resulting in the external electrical connectors having the same, more similar, or uniform heights.

[0081] Figures 1 to 8 Depicted are various cross-sectional views of various intermediate steps during a process for forming the package structure 100 , according to some embodiments. Figure 1A carrier substrate 20 and a release layer 22 formed on the carrier substrate 20 are shown. The carrier substrate 20 may be a glass carrier substrate, a ceramic carrier substrate, or the like. The carrier substrate 20 may be a wafer. The release layer 22 may be formed from a polymer-based material that can be removed along with the carrier substrate 20 from a cover structure to be formed in a subsequent step. In some embodiments, the release layer 22 is an epoxy-based thermal release material that loses its adhesive properties when heated, such as a light-to-heat-conversion (LTHC) release coating. In other embodiments, the release layer 22 may be an ultraviolet (UV) adhesive that loses its adhesive properties when exposed to UV light. The release layer 22 may be dispensed and cured in liquid form, may be a laminating film laminated to the carrier substrate 20, or may be a similar material. An adhesive 24 may be formed or dispensed on the release layer 22. The adhesive 24 may be a die attach film (DAF), glue, a polymer material, or the like.

[0082] The integrated circuit die 26 is adhered to the carrier substrate 20 via an adhesive 24 (e.g., through a release layer 22). As shown, one integrated circuit die 26 is adhered, and in other embodiments, more integrated circuit dies may be adhered. Prior to being adhered to the carrier substrate 20, the integrated circuit die 26 may be processed according to an applicable manufacturing process to form an integrated circuit in the integrated circuit die 26. For example, the integrated circuit die 26 may comprise a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, a multilayer or gradient substrate, or the like. The semiconductor of the substrate may include any semiconductor material, such as an elemental semiconductor, such as silicon, germanium, or the like; a compound or alloy semiconductor, including SiC, GaAs, GaP, InP, InAs, indium antimonide, SiGe, GaAsP, AlInAs, AlGaAs, GalnAs, GaInP, and / or GaInAsP; the like; or a combination thereof. Devices such as transistors, diodes, capacitors, resistors, etc. may be formed in and / or on a semiconductor substrate and may be interconnected via interconnect structures formed, for example, by a plurality of metallization patterns in one or more dielectric layers on the semiconductor substrate to form an integrated circuit.

[0083] The integrated circuit die 26 also includes pads 28, such as aluminum pads, for connecting to external connections. The pads 28 may be on the so-called active side of the integrated circuit die 26. A passivation film 30 is provided on the integrated circuit die 26 and on portions of the plurality of pads 28. A plurality of openings extend through the passivation film 30 to the plurality of pads 28. Die connectors 32, such as conductive posts (e.g., comprising a metal such as copper), are located within the openings through the passivation film 30 and are mechanically and electrically coupled to respective pads 28. The die connectors 32 may be formed, for example, by plating or the like. The die connectors 32 electrically couple the integrated circuits of the integrated circuit die 26. For clarity and simplicity, one pad 28 and one die connector 32 are depicted on the integrated circuit die 26, and one skilled in the art will readily appreciate that more than one pad 28 and more than one die connector 32 may be present.

[0084] Dielectric material 34 is disposed on the active side of integrated circuit die 26, such as on passivation film 30 and die connector 32. Dielectric material 34 laterally encapsulates die connector 32 and is laterally co-terminal with integrated circuit die 26. Dielectric material 34 may be a polymer, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like. In other embodiments, dielectric material 34 is formed from a nitride, such as silicon nitride; an oxide, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like; or a similar material. Dielectric material 34 may be formed via any acceptable deposition process, such as spin coating, chemical vapor deposition (CVD), lamination, the like, or a combination thereof. The plurality of integrated circuit dies 26 may be singulated, for example, by sawing or dicing, and adhered to the carrier substrate 20 via the adhesive 24 using, for example, a pick-and-place tool.

[0085] exist Figure 2 In the embodiment of the present invention, encapsulant 36 is formed on adhesive 24 around integrated circuit die 26 and / or on various components on integrated circuit die 26. Encapsulant 36 can be a molding compound, epoxy, or the like, and can be applied via compression molding, transfer molding, or the like. After curing, encapsulant 36 can undergo a grinding process to expose die connector 32. After the grinding process, the top surfaces of die connector 32, dielectric material 34, and encapsulant 36 are coplanar. In some embodiments, for example, if die connector 32 is already exposed, grinding can be omitted.

[0086] exist Figure 3 In the embodiment, a dielectric layer 38 and a metallization pattern 40 of a redistribution structure are formed. Figure 3 , and subsequent figures depict example configurations of redistribution structures, and in other implementations, the redistribution structure may include any number of dielectric layers, metallization patterns, and vias.

[0087] Dielectric layer 38 is formed over encapsulant 36, dielectric material 34, and die connector 32. In some embodiments, dielectric layer 38 is formed from a polymer, which may be a photosensitive material such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like, which can be easily patterned using a lithographic mask. In other embodiments, dielectric layer 38 is formed from a nitride such as silicon nitride; an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like. Dielectric layer 38 may be formed by spin coating, lamination, chemical vapor deposition, the like, or a combination thereof. Dielectric layer 38 is then patterned to form openings to expose portions of die connector 32. Patterning may be via an acceptable process, such as by exposing the dielectric layer 38 to light when the dielectric layer is a photosensitive material, or by etching using, for example, an anisotropic etch.

[0088] A metallization pattern 40 having guide holes 42 is formed on the dielectric layer 38. As an embodiment of forming the metallization pattern 40 and the guide holes 42, a seed layer (not shown) is formed above the dielectric layer 38. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer comprising a plurality of sublayers formed from different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer above the titanium layer. The seed layer can be formed using, for example, physical vapor deposition (PVD) or the like. A photoresist is then formed on the seed layer and patterned. The photoresist can be formed by spin coating or the like and can be exposed to patterning. The pattern of the photoresist corresponds to the metallization pattern 40. The patterning forms multiple openings through the photoresist to expose the seed layer. A conductive material is formed in the multiple openings of the photoresist and on the exposed multiple portions of the seed layer. The conductive material can be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may comprise a metal such as copper, titanium, tungsten, aluminum, or the like. The photoresist and portions of the seed layer (on which the conductive material is not formed) are then removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, the exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching. The remaining portions of the seed layer and the conductive material form the metallization pattern 40 and the vias 42. The vias 42 are formed in openings through the underlying layer (e.g., the dielectric layer 38).

[0089] By repeating the process used to form dielectric layer 38 and metallization pattern 40, one or more additional metallization patterns and vias and dielectric layers can be formed in the redistribution structure. As discussed, vias can be formed during the formation of the metallization patterns. Thus, the vias can interconnect and electrically couple the various metallization patterns. The depiction of one dielectric layer (e.g., dielectric layer 38) and one metallization pattern (e.g., metallization pattern 40) is for ease of illustration and simplicity.

[0090] exist Figure 4 In the embodiment of the present invention, a dielectric layer 44 is formed over the metallization pattern 40 and the dielectric layer 38. In some embodiments, the dielectric layer 44 is formed of a polymer, which can be a photosensitive material such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like, which can be easily patterned using a lithographic mask. In other embodiments, the dielectric layer 44 is formed of a nitride such as silicon nitride; or an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (PSG), or the like. The dielectric layer 44 can be formed by spin coating, lamination, chemical vapor deposition, the like, or a combination thereof. The dielectric layer 44 is then patterned to form a plurality of openings 46 to expose portions of the metallization pattern 40. Patterning can be done by any acceptable process, such as by exposing the dielectric layer 44 to light when the dielectric layer is a photosensitive material, or by etching using, for example, an anisotropic etch. Figure 4 In FIG, a single opening 46 is formed; however, a suitable number of openings 46 may be formed. For example, in Figures 6 to 8 , two openings 46 are shown.

[0091] Figures 5 to 8 The formation of under ball metallizations (UBMs) 56 is shown for connection to external electrical connectors, as described in subsequent figures.

[0092] exist Figure 5 In the embodiment of the present invention, a seed layer 48 is formed over dielectric layer 44 and in opening 46, for example, on the sidewalls of dielectric layer 44 and on metallization pattern 40. In some embodiments, seed layer 48 is a metal layer, which can be a single layer or a composite layer including multiple sublayers formed of different materials. In some embodiments, seed layer 48 includes a titanium layer and a copper layer overlying the titanium layer. Seed layer 48 can be formed using, for example, physical vapor deposition or the like.

[0093] Note that, in Figure 4 and Figure 5 In FIG, a single opening 46 is shown; however, any number of suitable openings 46 may be formed. For example, in Figures 6 to 8, two openings 46 are shown.

[0094] exist Figure 6 In the embodiment, a photoresist 50 is formed on the seed layer 48. In this embodiment, the photoresist 50 is a negative photoresist material. The photoresist 50 can be formed on the seed layer by spin coating, or the like.

[0095] exist Figure 7 In the embodiment of the present invention, a photoresist 50 is patterned on the seed layer 48. The photoresist 50 can be exposed and then developed to perform the patterning. Using a negative photoresist, exposed portions of the photoresist 50 remain after patterning. After exposure, the photoresist 50 is developed to remove soluble portions of the photoresist 50, so that insoluble portions of the photoresist 50 remain on the seed layer 48 with a plurality of openings 52 passing through the photoresist 50. The pattern of the photoresist 50 corresponds to the under bump metallurgy 60 or other metallization pattern to be formed.

[0096] exist Figure 8 , under bump metallurgy 60 is formed in corresponding openings 52 of photoresist 50 and on seed layer 48. Conductive material is formed in openings 52 of photoresist 50 and on exposed portions of seed layer 48, for example, by plating, such as electroplating or electroless plating, or the like. The conductive material may include a metal such as copper, titanium, tungsten, aluminum, or the like.

[0097] Figures 1 to 8 The formation of three under bump metals (UBMs) 60 above the semiconductor die 26 is depicted: an active UBM 61, a dummy UBM 62, and a dummy UBM 63. After further processing, the seed layer 48 below the UBM 60 will be etched into different sections that are insulated from each other. Specifically, portions of the seed layer 48 not covered by the UBM 60 will be removed. As shown, the UBM 61 is electrically connected to the active side of the integrated circuit die 26 through the pad 28, the die connector 32, the via 42, the metallization pattern 40, and the seed layer 48. The dummy UBM 62 is formed on a portion of the seed layer 48 above the dielectric layer 44 and, after etching, is disconnected from any electrical path. The dummy UBM 63 is formed on a portion of the seed layer 48 located above a portion of the metallization pattern 40 and, after etching, is disconnected from any electrical path.

[0098] Although Figures 1 to 8 The formation of the plurality of UBMs 60 is depicted at a level above the seed layer 48 , but in other embodiments, the plurality of UBMs 60 may be formed at a higher or lower level. For example, Figures 1 to 8The formation of two dielectric layers 34 and 44, as well as metallization pattern 40 and vias 42, is depicted. However, additional dielectric layers and upper metallization patterns and vias may be formed, with underbump metallization 60 formed above the upper metallization patterns. Alternatively, underbump metallization 60 may be formed on pads 28 at a lower level.

[0099] Now refer to Figures 9 to 16 , provides multiple focused views of the UBM 160 during processing of the semiconductor die 26. Figures 9 to 16 In the embodiment, the under bump metal 160 is formed on the conductive contact 140. The under bump metal 160 may be formed according to the embodiment of the present invention. Figures 1 to 8 The conductive contacts 140 are formed by the metallization pattern 40 by the process described in Figures 1 to 8 The pads 28 described in the foregoing, or the conductive contacts 140 may be formed by a higher metallization level (in Figures 1 to 8 (not shown).

[0100] exist Figures 9 to 16 In the embodiment, the conductive contact 140 is located below the conductive contact 140. Figures 1 to 8 The underlying structures are collectively and generally designated by the reference numeral 70 and may include conductive interconnect structures extending through various dielectric layers or structures.

[0101] As in Figure 9 As shown in FIG, a passivation layer 144 is formed over the integrated circuit die 26 and over portions of the conductive contacts 140. A plurality of openings 142 are formed through the passivation layer 144 to the plurality of conductive contacts 140.

[0102] exist Figure 10 Insulating material 145 is formed on the active side of integrated circuit die 26, for example, on passivation layer 144. Insulating material 145 can be a polymer, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like. In other embodiments, insulating material 145 is formed of a nitride, such as silicon nitride; an oxide, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like; or a similar material. Insulating material 145 can be formed by any acceptable deposition process, such as spin coating, chemical vapor deposition (CVD), lamination, the like, or a combination thereof.

[0103] exist Figure 11 In the embodiment of the present invention, a conductive material 148 is then formed over the conductive contacts 140 and the insulating material 145, for example, by sputtering. The conductive material 148 may include a metal such as copper, titanium, tungsten, aluminum, or the like. The conductive material 148 may be a seed layer.

[0104] As shown in Figure 12 resist 150 is formed over the conductive material 148 and patterned. Forming the photoresist 150 can be via spin coating, or the like, and can be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern conductive contacts 140. Patterning forms openings 151 through the photoresist 150 to expose the conductive material 148. As shown, the openings 151 are formed to have a lateral width Wl or critical dimension.

[0105] In Figure 13 , a conductive material 158 is formed in the openings of the photoresist 150 and on the exposed portions of the conductive material 148. Forming the conductive material 158 can be via plating, such as electroplating or electroless plating, or the like. The conductive material 158 can include a metal, such as nickel, tin, silver, copper, titanium, tungsten, aluminum, or the like. In some embodiments, the conductive material 158 is nickel or a tin and silver alloy. The conductive material 158 can form and define an under bump metal structure 160 or pad, or the under bump metal structure 160 can include the conductive material 158 and the conductive material 148.

[0106] Further, in Figure 13 , an external electrical connector 170 is formed on the under bump metal structure 160 through the openings in the photoresist 150. In some embodiments, the external electrical connector 170 can include a low temperature reflowable material, such as a solder, such as a lead-free solder, formed on the under bump metal 160 using an acceptable ball drop process. In some embodiments, the external electrical connector 170 is a ball grid array (BGA) ball, a controlled collapse chip connection (C4) bump, a micro bump, or the like. In additional embodiments, the external electrical connector 170 can include a metal stud.

[0107] As shown in Figure 13 , the external electrical connector 170 is formed to have an uppermost surface at a height Hl above an uppermost surface of the photoresist 150.

[0108] In Figure 14 , the photoresist 150 is removed. Removing the photoresist can be via an acceptable ashing or stripping process, such as using an oxygen plasma, or the like.

[0109] After the photoresist 150 is removed, the exposed portions of the conductive material 148 are removed, as in Figure 15As shown in . Removal of exposed portions of conductive material 148 may be performed using an acceptable etching process, such as wet or dry etching. The remaining portions of conductive material 148 and conductive material 158 may form under bump metallurgy structure 160. Cross Reference Figure 12 and Figure 15 , the UBM structure 160 is formed to have a lateral width or critical dimension W1.

[0110] exist Figure 16 In the embodiment of the present invention, a reflow process is performed to reform the material of the external electrical connectors 170. The reflow process can be used to form a metal interconnect phase between the material of the underbump metallurgy 160 and the external electrical connectors 170. In some embodiments, the reflow process forms the external electrical connectors 170 into homogeneous solder balls. As shown in the figure, after the reflow process, each external electrical connector 170 has a height H2, which is measured from the uppermost surface of the external electrical connector 170 to the uppermost surface of the insulating material 145.

[0111] Further processing can then be performed to complete the package. Figures 1 to 8 In the structure of package 100 in FIG, carrier substrate de-bonding may be performed to separate (peel) carrier substrate 20 from the package structure. According to some embodiments, de-bonding includes projecting light, such as laser light or ultraviolet light, onto release layer 22, causing release layer 22 to decompose under the heating of the light, and carrier substrate 20 may be removed.

[0112] Then, this structure can be turned over and placed on tape and divided. Those skilled in the art will understand that many such package structures can be formed on the carrier substrate 20 at the same time, so that individual packages can be separated from other packages, for example, via sawing or cutting.

[0113] Various embodiments herein provide methods for forming multiple external electrical connectors 170 having the same height H1 and / or the same height H2 despite being located in regions of the integrated circuit die 26 having different under bump metallurgy densities, i.e., different external electrical connector densities.

[0114] Figure 17 A schematic top view of an integrated circuit die 26 including a first region 201 and a second region 202 is provided. Figure 18 is a cross-sectional view of the UBM structure 160 in the first region 201, Figure 19 is a cross-sectional view of the UBM structure 160 in the second region 202. Figure 17As shown in the middle, the under-bump metallurgy structures 160 are more densely arranged in the first region 201 than in the second region 202. For example, the first region 201 can be a dense region 201, and the second region 202 can be an isolated region. The first region 201 has a first ratio of under-bump metallurgy structures per unit area, and the second region 202 has a second ratio of under-bump metallurgy structures per unit area. As shown, the first ratio is greater than the second ratio.

[0115] It has been found that the formation of the plurality of external electrical connectors 170 over the under-bump metallurgy structures 160 in the dense region 201 generally results in the plurality of external electrical connectors 170 having a relatively short height (in H1 in Figure 13 and / or H2 in Figure 16 ), and the formation of the plurality of external electrical connectors 170 over the under-bump metallurgy structures 160 in the isolated region 202 results in the plurality of external electrical connectors 170 having a relatively high height (in H1 in Figure 13 and / or H2 in Figure 16 ).

[0116] The various embodiments herein counteract the tendency to form the plurality of external electrical connectors 170 having different heights in the dense region 201 and in the isolated region 202. Specifically, the various embodiments herein compensate for such tendency via altering the structure and / or layout of the under-bump metallurgy structures 160 in at least one of the regions 201 and / or 202. As a result, the plurality of external electrical connectors 170 are formed to have the same height in the dense region 201 and in the isolated region 202.

[0117] For example, in Figure 17 and Figure 18 , the plurality of under-bump metallurgy structures 160 in the dense region 201 are formed to have a lateral width or critical dimension W1 equal to a distance D1, while in Figure 17 and Figure 19 , the plurality of under-bump metallurgy structures 160 in the isolated region 202 are formed to have a lateral width or critical dimension W1 equal to a distance D2. As shown, the distance D2 is greater than the distance D1. In some embodiments, the distance D1 or D2 is about 1 to 20 microns, such as at least 1, at least 2, at least 3, at least 4, at least 5, at least 6, at least 7, at least 8, at least 9, at least 10, at least 11, at least 12, at least 13, at least 14, at least 15, at least 16, at least 17, at least 18, or at least 19 microns; and at most 2, at most 3, at most 4, at most 5, at most 6, at most 7, at most 8, at most 9, at most 10, at most 11, at most 12, at most 13, at most 14, at most 15, at most 16, at most 17, at most 18, at most 19, or at most 20 microns.

[0118] In some embodiments, distance D1 is from 10% to 90% of distance D2. For example, distance D1 can be at least 10%, at least 20%, at least 30%, at least 40%, at least 50%, at least 60%, at least 70%, at least 80%, or at least 90% of distance D2. In some embodiments, distance D1 can be at most 15%, at most 20%, at most 30%, at most 40%, at most 50%, at most 60%, at most 70%, at most 80%, at most 90%, or at most 95% of distance D2.

[0119] As in Figure 18 and Figure 19 As shown in FIG, a plurality of external electrical connectors 170 are formed to have the same height H1 in the dense area 201 and the isolated area 202 .

[0120] exist Figures 17 to 19 In the embodiment, all UBM structures 160 may be active UBM structures 161, such as Figure 8 Specifically, the active UBM structure 161 is electrically interconnected with other conductive structures in the die 26 .

[0121] exist Figures 20 to 23 An alternative or additional embodiment is shown in FIG. Figure 20 A schematic top view of an integrated circuit die 26 including a first dense region 201, a second isolated region 202, and a third intermediate region 203 is provided. Figure 20 As shown in FIG, the integrated circuit die 26 is formed to have an active UBM structure 161 and a dummy UBM structure 162, for example, Figure 8 The dummy UBM structure 62 and the dummy UBM structure 163, for example, Figure 8 The dummy under bump metal structure 63 in FIG.

[0122] Figure 21 is a cross-sectional view of the UBM structure 161 in regions 201 , 202 , and 203 . Figure 22 is a cross-sectional view of an inactive or dummy UBM structure 162 , which may be located in region 202 and region 203 . Figure 23 is a cross-sectional view of an inactive or dummy UBM structure 163 , which may be located in region 202 and region 203 .

[0123] As in Figure 20As shown in FIG, the UBM structures 161 are more densely packed in the first region 201 than in the third region 203. Furthermore, the UBM structures 161 are more densely packed in the third region 203 than in the second region 202. The first region 201 has a first ratio of UBM structures per unit area, the second region 202 has a second ratio of UBM structures per unit area, and the third region 203 has a third ratio of UBM structures per unit area. As shown in the figure, the first ratio is greater than the third ratio, and the third ratio is greater than the second ratio.

[0124] As further shown, a plurality of inactive or dummy UBM structures 162 and / or 163 are provided in the second region 202 and the third region 203 to increase the density of the total plurality of UBM structures 160 therein. As a result, the difference between the plurality of ratios of the total plurality of UBM structures 160 (including active and dummy structures) across the regions 201, 202, and 203 is less than the difference between the plurality of ratios of the plurality of active UBM structures 161. For example, the first region 201 may have a first ratio of the total plurality of UBM structures 160 per unit area, the second region 202 may have a second ratio of the total plurality of UBM structures 160 per unit area, and the third region 203 may have a third ratio of the total plurality of UBM structures 160 per unit area. The first ratio of the total number of UBM structures 160 per unit area, the second ratio of the total number of UBM structures 160 per unit area, and the third ratio of the total number of UBM structures 160 per unit area can be equal, or can be within 1%, 2%, 3%, 4%, 5%, 10%, 15%, or 20%. In some embodiments, the plurality of local sub-regions within regions 201, 202, and 203 have equal ratios of the total number of UBM structures 160 per unit area, or such ratios are within 1%, 2%, 3%, 4%, 5%, 10%, 15%, or 20%.

[0125] Another way to assess the relative density or isolation of the UBM structures 161 relates to the inter-structure distance, which is the distance from each UBM structure 161 to the corresponding nearest neighboring UBM structure 161. Figure 20 As shown in FIG, the selected UBM structure 161 ′ in the region 202 is located at an inter-active structure distance D9 from the relatively nearest adjacent UBM structure 161 .

[0126] In the dense region 201, the UBM structure 161 may be located at a maximum first inter-active structure distance from the corresponding nearest-neighboring UBM structure 161. In the isolated region 202, the UBM structure 161 may be located at a second maximum first inter-active structure distance from the corresponding nearest-neighboring UBM structure 161. In the intermediate region 203, the UBM structure 161 may be located at a third maximum first inter-active structure distance from the corresponding nearest-neighboring UBM structure 161. In some embodiments, the first maximum first inter-active structure distance is less than the third maximum first inter-active structure distance, and less than the second maximum first inter-active structure distance. In some embodiments, the third maximum first inter-active structure distance is less than the second maximum first inter-active structure distance.

[0127] In the dense region 201, the UBM structure 161 may be located at a minimum first inter-active structure distance from the corresponding nearest-neighboring UBM structure 161. In the isolated region 202, the UBM structure 161 may be located at a second minimum first inter-active structure distance from the corresponding nearest-neighboring UBM structure 161. In the intermediate region 203, the UBM structure 161 may be located at a third minimum first inter-active structure distance from the corresponding nearest-neighboring UBM structure 161. In some embodiments, the first minimum first inter-active structure distance is less than the third minimum first inter-active structure distance, and less than the second minimum first inter-active structure distance. In some embodiments, the third minimum first inter-active structure distance is less than the second minimum first inter-active structure distance.

[0128] As in Figure 20 As shown in FIG, inactive or dummy UBM structures 162 and / or 163 are provided in the second region 202 and the third region 203 to reduce the distance between each active UBM structure 161 and the nearest UBM structure 160 (including inactive or dummy UBM structures 162 and / or 163). As a result, the isolation of each active UBM structure 161 is reduced. For example, the dummy UBM structures 162 and / or 163 are located at an inter-structure distance D8 from a selected active UBM structure 161'. As shown, the inter-structure distance D8 is less than the active inter-structure distance D9. In addition, the inter-structure distance D8 can be equal to or less than a selected threshold value for the inter-structure distance. For example, the thresholds selected for the inter-structure distances in region 202 and region 203 may be based on the active inter-structure distances in region 201, such as based on the average or median active inter-structure distance in region 201, the maximum active inter-structure distance in region 201, or the minimum active inter-structure distance in region 201.

[0129] In some embodiments, each inter-structure distance D8 in region 202 and region 203 is equal to or less than the maximum active inter-structure distance in region 201. In some embodiments, each inter-structure distance D8 in region 202 and region 203 is within 1%, within 2%, within 3%, within 4%, within 5%, within 10%, within 15%, or within 20% of the maximum active inter-structure distance in region 201.

[0130] In some embodiments, each inter-structure distance D8 in region 202 and region 203 is equal to the average or median active inter-structure distance in region 201. In some embodiments, each inter-structure distance D8 in region 202 and region 203 is within 1%, within 2%, within 3%, within 4%, within 5%, within 10%, within 15%, or within 20% of the average or median active inter-structure distance in region 201.

[0131] In some embodiments, each active UBM structure 161 within region 202 and region 203 that is located at an inter-active structure distance D9 from the nearest active UBM structure 161 (greater than a selected threshold) is provided with a proximal inactive or dummy UBM structure (or structures) 162 and / or 163 to reduce the relative isolation of the active UBM structures 161. By providing the inactive or dummy UBM structures 162 and / or 163 in the second region 202 and the third region 203, the relative isolation of each active UBM structure 161 in the second region 202 and the third region 203 is reduced.

[0132] By reducing the relative isolation of each UBM structure 160, i.e., no UBM structure 160 is further away from its corresponding nearest neighbor than a selected threshold, variations in height between the plurality of external electrical connectors 170 formed above the UBM structure 160 are reduced or eliminated.

[0133] As in Figures 21 to 23 As shown in FIG, each of the plurality of external electrical connectors 170 formed above the active under bump metal structure 161, above the dummy under bump metal structure 162, and above the dummy under bump metal structure 163 is formed to have an uppermost surface that is at the same height H1 above the uppermost surface of the photoresist 150.

[0134] Note that, Figures 17 to 19 The embodiments of the present invention limit the vertical height of the plurality of external electrical connectors 170 by forming a plurality of under bump metal pads 160 having different critical dimensions, and Figures 20 to 23The embodiments of the present invention limit the vertical height of the plurality of external electrical connectors 170 by forming a plurality of dummy UBM pads 162-163 adjacent to the relatively isolated active UBM pads 161. In addition, it is noted that the die 26 can be provided with Figures 17 to 19 and Figures 20 to 23 The combination of multiple embodiments enables, in some embodiments, multiple UBM pads 160 to be formed to have different critical dimensions, and multiple dummy UBM pads are formed to reduce the isolation of multiple relatively isolated active UBM pads.

[0135] Now refer to Figure 24 , further describing a process for forming an active UBM structure 161 and a process for forming dummy UBM structures 162 and / or 163. During the formation of the active UBM structure 161, this process may use a first pitch P1. However, the formation of multiple dummy UBM structures 162 and / or 163 may be performed using a second pitch P2 that is different from the first pitch P1. As a result, the formation process can be smoother and cavity defects can be prevented.

[0136] Figure 25 A top view of an UBM structure 160 is provided. As shown, the UBM structure 160 can be provided to have a circular, oval, or hexagonal shape. The UBM structure 160 is not limited to a circular, oval, or hexagonal shape. Specifically, the UBM structure 160 can be formed into any suitable shape, including a triangle, a square, a rectangle, a pentagon, an octagon, an irregular shape, etc. Further, it is noted that each active UBM structure 161, each dummy UBM structure 162, and each dummy UBM structure 163 can be formed into any selected shape, regardless of the shape of the other active UBM structures 161, the dummy UBM structures 162, and the dummy UBM structures 163 on the die 26.

[0137] Figure 26 A flow chart is provided for method 900. As shown, method 900 includes determining an integrated circuit (IC) layout design at operation S902.

[0138] Method 900 also includes determining relative isolation of the UBM structures at operation S904. For example, the integrated circuit layout design may include a dense region including a plurality of external electrical connectors densely arranged on the UBM structure and an isolated region including a plurality of external electrical connectors isolated on the UBM structure. Determining the relative isolation of the UBM structures may include determining an inter-active structure distance of each active UBM structure.

[0139] At operation S906, the method 900 determines an effect on bump height from relative isolation of the under bump metallurgy structures. For example, the method 900 can determine that a plurality of external electrical connectors formed over the isolated under bump metallurgy structures will be formed with an increased height relative to a plurality of external electrical connectors formed over the densely packed under bump metallurgy structures. Determining an effect on bump height from relative isolation of the under bump metallurgy structures can include basing the active structure-to-structure distance or device density or a repository of known height effects from isolation references.

[0140] At operation S908, the method 900 changes the integrated circuit layout design to improve bump height uniformity. For example, the integrated circuit layout design can be changed to provide a plurality of external electrical connectors densely arranged on an under bump metallurgy (UBM) pad with a first height and to provide a plurality of external electrical connectors isolated on an under bump metallurgy (UBM) pad with a second height equal to the first height. In other words, operation S908 can limit the plurality of external electrical connectors to a preselected vertical height, i.e., the first height.

[0141] For example, at operation S908, the method 900 can increase a critical dimension of the under bump metallurgy structures and / or openings over the under bump metallurgy structures in the isolated region. Additionally or alternatively, at operation S908, the method 900 can decrease a critical dimension of the under bump metallurgy structures and / or openings over the under bump metallurgy structures in the dense region. Additionally or alternatively, at operation S908, the method 900 can add dummy under bump metallurgy structures to the integrated circuit layout design to decrease the structure-to-structure distance of the plurality of under bump metallurgy structures in the isolated region.

[0142] At operation S910, the method 900 fabricates an integrated circuit (IC) according to the changed integrated circuit layout design. Fabricating the integrated circuit includes forming a plurality of under bump metallurgy (UBM) pads in the dense region and in the isolated region; and forming a plurality of external electrical connectors over the plurality of under bump metallurgy (UBM) pads in the dense region and in the isolated region.

[0143] As a result of operation S908, an integrated circuit with improved bump height uniformity is fabricated. For example, the external electrical connectors in the integrated circuit can be formed with the same height, or heights within 1% of each other, within 2% of each other, within 3% of each other, within 4% of each other, within 5% of each other, within 10% of each other, or within 20% of each other, whether in the dense region or in the isolated region.

[0144] In one embodiment, a method includes forming a semiconductor die having a plurality of under bump metallurgy (UBM) pads in dense areas and in isolated areas; forming a plurality of external electrical connectors in contact with the UBM pads; and limiting the external electrical connectors to a preselected vertical height.

[0145] In some embodiments, the method further includes forming an opening above the under bump metallurgy pad; wherein forming an external electrical connector in contact with the under bump metallurgy pad includes forming the external electrical connector in the opening.

[0146] In some embodiments of the method, forming the external electrical connector includes dropping solder balls into the openings.

[0147] In some embodiments of this method, limiting the plurality of external electrical connectors to a preselected vertical height includes forming a plurality of openings having a first critical dimension above the plurality of under bump metal pads in a dense area; forming a plurality of openings having a second critical dimension greater than the first critical dimension above the plurality of under bump metal pads in an isolated area, and forming the plurality of external electrical connectors in contact with the plurality of under bump metal pads includes forming the plurality of external electrical connectors in the plurality of openings.

[0148] In some embodiments of the method, limiting the external electrical connector to a preselected vertical height includes forming a plurality of under bump metallurgy pads having a first critical dimension in a dense area; and forming a plurality of under bump metallurgy pads having a second critical dimension greater than the first critical dimension in an isolated area.

[0149] In some embodiments of this method, each under bump metallurgy pad in the dense region is separated from its nearest neighboring under bump metallurgy pad by a first distance; at least one under bump metallurgy pad in the isolated region is separated from its nearest neighboring under bump metallurgy pad by a second distance greater than the first distance; and limiting the external electrical connector to a preselected vertical height includes forming a dummy pad in the isolated region at a third distance from the at least one under bump metallurgy pad, wherein the third distance is less than the second distance; and forming the external electrical connector in contact with the dummy pad simultaneously with forming the external electrical connector in contact with the under bump metallurgy pad. In some embodiments, the third distance is within 20% of the first distance. In some embodiments, the third distance is equal to the first distance.

[0150] In some embodiments of the method, each under bump metal pad in the dense region is separated from a nearest neighbor under bump metal pad by a first distance; at least one under bump metal pad in the isolated region is separated from an opposite nearest neighbor under bump metal pad by a second distance that is greater than the first distance; and limiting the external electrical connectors to the preselected vertical height comprises forming a plurality of under bump metal pads having a first critical dimension in the dense region; forming a plurality of under bump metal pads having a second critical dimension that is greater than the first critical dimension in the isolated region; forming a dummy pad at a third distance from the at least one under bump metal pad in the isolated region, wherein the third distance is less than the second distance; and forming the external electrical connectors in contact with the dummy pad while forming the external electrical connectors in contact with the under bump metal pads.

[0151] In another embodiment, a method includes determining an integrated circuit layout design, wherein the integrated circuit layout design includes a dense region and an isolated region, the dense region including densely arranged external electrical connectors on under bump metal (UBM) pads, the isolated region including a plurality of external electrical connectors isolated on a plurality of under bump metal (UBM) pads, wherein determining the integrated circuit layout design includes providing densely arranged a plurality of external electrical connectors having a first height on under bump metal (UBM) pads, and wherein determining the integrated circuit layout design includes providing isolated a plurality of external electrical connectors having a second height equal to the first height on the plurality of under bump metal (UBM) pads; forming a plurality of under bump metal (UBM) pads in the dense region and in the isolated region; and forming a plurality of external electrical connectors over the plurality of under bump metal (UBM) pads in the dense region and in the isolated region.

[0152] In some embodiments of the method, determining the integrated circuit layout design includes providing under bump metal (UBM) pads having a first lateral critical dimension in the dense region and providing under bump metal (UBM) pads having a second lateral critical dimension different from the first lateral critical dimension in the isolated region. In some embodiments, the second lateral critical dimension is greater than the first lateral critical dimension.

[0153] In some embodiments of the method, determining the integrated circuit layout design includes providing a dummy under bump metal (UBM) pad in the isolated region.

[0154] In some embodiments of the method, the under bump metal pads in the dense region, the under bump metal pads in the isolated region, and the dummy under bump metal pad have the same lateral critical dimension.

[0155] In some embodiments of the method, the dense region has a first ratio of UBM pads per unit area; the isolated region has a combined ratio of UBM pads and dummy UBM pads per unit area; and the first ratio is equal to the combined ratio.

[0156] In another embodiment, a semiconductor die includes a dense region comprising a plurality of first under bump metallurgy (UBM) pads, wherein the dense region has a first ratio of the plurality of first under bump metallurgy (UBM) pads per unit area; a first plurality of external electrical connectors contacting the first under bump metallurgy (UBM) pads, wherein each first external electrical connector has a first vertical height; an isolation region comprising a plurality of second under bump metallurgy (UBM) pads, wherein the isolation region has a second ratio of the plurality of second under bump metallurgy (UBM) pads per unit area, wherein the first ratio is greater than the second ratio; and a plurality of second external electrical connectors contacting the plurality of second under bump metallurgy (UBM) pads, wherein each second external electrical connector has a second vertical height; wherein the semiconductor die is configured such that the first vertical height is equal to the second vertical height.

[0157] In some embodiments of the semiconductor die, the plurality of first external electrical connectors have a first lateral critical dimension, and the semiconductor die is configured such that the first vertical height is equal to the second vertical height by providing the plurality of second external electrical connectors with a second lateral critical dimension different from the first lateral critical dimension.

[0158] In some embodiments of the semiconductor die, the second lateral critical dimension is greater than the first lateral critical dimension.

[0159] In some embodiments of the semiconductor die, the first critical dimension is from 10% to 90% of the second critical dimension.

[0160] In some embodiments, the semiconductor die includes a dielectric layer covering the dense area and the isolated area, and a plurality of openings are formed in the dielectric layer covering the first under-bump metal pad and the second under-bump metal pad, wherein the openings limit the first external electrical connector to a first lateral critical dimension and limit the second external electrical connector to a second lateral critical dimension.

[0161] In some embodiments of the semiconductor die, the semiconductor die is configured such that a first vertical height is equal to a second vertical height by including a dummy under bump metallurgy (UBM) pad in the isolation region, wherein a third ratio of a total plurality of under bump metallurgy pads including a plurality of second under bump metallurgy pads and a plurality of dummy under bump metallurgy pads per unit area is present in the isolation region, wherein the third ratio is greater than the second ratio.

[0162] Other embodiments of the present disclosure provide a semiconductor die comprising: a dense region, a plurality of first external electrical connectors, an isolation region, and a plurality of second external electrical connectors. The dense region includes a plurality of first under-bump metallurgy (UBM) pads, wherein the dense region has a first ratio of the plurality of first under-bump metallurgy (UBM) pads per unit area. The plurality of first external electrical connectors contact the plurality of first under-bump metallurgy (UBM) pads, wherein each first external electrical connector has a first vertical height. The isolation region includes a plurality of second under-bump metallurgy (UBM) pads and a plurality of dummy under-bump metallurgy (DBM) pads, wherein the isolation region has a second ratio of the plurality of second under-bump metallurgy (UBM) pads per unit area, wherein the first ratio is greater than the second ratio. The plurality of second external electrical connectors contact the plurality of second under-bump metallurgy (UBM) pads and the plurality of dummy under-bump metallurgy (DBM) pads, wherein each second external electrical connector has a second vertical height. The semiconductor die is configured such that the first vertical height is equal to the second vertical height.

[0163] Still other embodiments of the present disclosure provide a semiconductor die comprising: a dense region, a plurality of first external electrical connectors, an isolated region, a plurality of second external electrical connectors, an intermediate region, and a plurality of third external electrical connectors. The dense region includes a plurality of first under-bump metallurgy (UBM) pads. The plurality of first external electrical connectors contact the plurality of first under-bump metallurgy (UBM) pads, wherein each first external electrical connector has a first vertical height. The isolated region includes a plurality of second under-bump metallurgy (UBM) pads and a plurality of first dummy under-bump metallurgy (UBM) pads. A plurality of second external electrical connectors contact the plurality of second under-bump metallurgy (UBM) pads and the plurality of first dummy under-bump metallurgy (UBM) pads, wherein each second external electrical connector has a second vertical height. The intermediate region is disposed between the dense region and the isolated region, and includes a plurality of third under-bump metallurgy (UBM) pads and a plurality of second dummy under-bump metallurgy (UBM) pads. A plurality of third external electrical connectors contact the plurality of third under-bump metallurgy (UBM) pads and the plurality of second dummy under-bump metallurgy (UBM) pads, wherein each third external electrical connector has a third vertical height. The first vertical height, the second vertical height and the third vertical height are equal.

[0164] In some embodiments of the semiconductor die, the dense region has a first ratio of the plurality of first under-bump metal pads per unit area; the isolated region has a second ratio of the plurality of second under-bump metal pads per unit area; and the intermediate region has a third ratio of the plurality of third under-bump metal pads per unit area; wherein the first ratio is greater than the third ratio, and the third ratio is greater than the second ratio.

[0165] In some embodiments of the semiconductor die, the dense region has a first total ratio of the plurality of first under bump metallization pads per unit area; the isolated region has a second total ratio of the plurality of second under bump metallization pads and the plurality of first dummy under bump metallization pads per unit area; the intermediate region has a third total ratio of the plurality of third under bump metallization pads and the plurality of second dummy under bump metallization pads per unit area; wherein the difference between the first total ratio and the second total ratio is within 20%, and the difference between the second total ratio and the third total ratio is within 20%.

[0166] The foregoing outlines features of several embodiments so that those skilled in the art can better understand the various aspects of the disclosure. Those skilled in the art should appreciate that they can readily use the disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the disclosure, and that they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the disclosure.

Claims

1. A semiconductor crystal grain, characterized in that: Include: a dense region comprising a plurality of first under bump metallurgy pads, wherein the dense region has a first ratio of the plurality of first under bump metallurgy pads per unit area; a plurality of first external electrical connectors contacting the plurality of first under bump metallurgy pads, wherein each of the first external electrical connectors has a first vertical height; an isolation region comprising a plurality of second UBM pads, wherein the isolation region has a second ratio of the plurality of second UBM pads per unit area, wherein the first ratio is greater than the second ratio; and a plurality of second external electrical connectors contacting the plurality of second under bump metallurgy pads, wherein each second external electrical connector has a second vertical height; The semiconductor die is configured so that the first vertical height is equal to the second vertical height.

2. The semiconductor crystal grain according to claim 1, wherein The first external electrical connectors have a first lateral critical dimension, and the semiconductor die is configured such that the first vertical height is equal to the second vertical height, by providing the second external electrical connectors with a second lateral critical dimension different from the first lateral critical dimension.

3. The semiconductor crystal grain according to claim 2, wherein: The second lateral critical dimension is greater than the first lateral critical dimension.

4. The semiconductor crystal grain according to claim 2, wherein The first lateral critical dimension is from 10% to 90% of the second lateral critical dimension.

5. The semiconductor crystal grain according to claim 2, wherein: Also includes: a dielectric layer covering the dense area and the isolated area, wherein a plurality of openings are formed in the dielectric layer covering the plurality of first under bump metallization pads and covering the plurality of second under bump metallization pads, and wherein the plurality of openings limit the plurality of first external electrical connectors to the first lateral critical dimension and limit the plurality of second external electrical connectors to the second lateral critical dimension.

6. The semiconductor crystal grain according to claim 1, wherein The semiconductor die is configured such that the first vertical height is equal to the second vertical height by including a plurality of dummy under bump metal pads in the isolation region, wherein the isolation region has a third ratio of the total plurality of under bump metal pads, including the plurality of under bump metal pads and the plurality of dummy under bump metal pads per unit area, wherein the third ratio is greater than the second ratio.

7. A semiconductor crystal grain, characterized in that: Include: a dense region comprising a plurality of first under bump metallurgy pads, wherein the dense region has a first ratio of the plurality of first under bump metallurgy pads per unit area; a plurality of first external electrical connectors contacting the plurality of first under bump metallurgy pads, wherein each of the plurality of first external electrical connectors has a first vertical height; an isolation region comprising a plurality of second UBM pads and a plurality of dummy UBM pads, wherein the isolation region has a second ratio of the plurality of second UBM pads per unit area, wherein the first ratio is greater than the second ratio; and a plurality of second external electrical connectors contacting the plurality of second UBM pads and the plurality of dummy UBM pads, wherein each of the plurality of second external electrical connectors has a second vertical height; The semiconductor die is configured so that the first vertical height is equal to the second vertical height.

8. A semiconductor crystal grain, characterized in that: Include: a dense area comprising a plurality of first under bump metal pads; a plurality of first external electrical connectors contacting the plurality of first under bump metallurgy pads, wherein each of the plurality of first external electrical connectors has a first vertical height; an isolation region comprising a plurality of second under bump metal pads and a plurality of first dummy under bump metal pads; as well as a plurality of second external electrical connectors contacting the plurality of second UBM pads and the plurality of first dummy UBM pads, wherein each of the plurality of second external electrical connectors has a second vertical height; a middle area disposed between the dense area and the isolated area, the middle area including a plurality of third under bump metal pads and a plurality of second dummy under bump metal pads; a plurality of third external electrical connectors contacting the plurality of third under bump metallurgy pads and the plurality of second dummy under bump metallurgy pads, wherein each of the plurality of third external electrical connectors has a third vertical height; The first vertical height, the second vertical height and the third vertical height are equal.

9. The semiconductor crystal grain according to claim 8, wherein in: The dense region has a first ratio of the plurality of first under bump metal pads per unit area; The isolation region has a second ratio of the plurality of second under bump metal pads per unit area; The middle region has a third ratio of the plurality of third under bump metal pads per unit area; The first ratio is greater than the third ratio, and the third ratio is greater than the second ratio.

10. The semiconductor crystal grain according to claim 8, wherein in: The dense region has a first total ratio of the plurality of first under bump metal pads per unit area; The isolation region has a second total ratio of the plurality of second UBM pads to the plurality of first dummy UBM pads per unit area; The middle region has a third total ratio of the third UBM pads to the second dummy UBM pads per unit area; The first total ratio differs from the second total ratio by less than 20%, and the second total ratio differs from the third total ratio by less than 20%.

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